JPS5858354U - Lead frame for semiconductor devices - Google Patents
Lead frame for semiconductor devicesInfo
- Publication number
- JPS5858354U JPS5858354U JP15385881U JP15385881U JPS5858354U JP S5858354 U JPS5858354 U JP S5858354U JP 15385881 U JP15385881 U JP 15385881U JP 15385881 U JP15385881 U JP 15385881U JP S5858354 U JPS5858354 U JP S5858354U
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- plating layer
- metal plating
- die pad
- semiconductor devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のリードフレームを示す平面図、第２図は
このようなリードフレームを用いた半導体装置の組立て
の一段階を示す正断面図、第３図および第４図は従来の
リードフレームを用いた場合の半導体チッパとダイパッ
ド保持部とをワイヤボンド接続した状況を示す斜視図で
、第３図は理想的な場合、第４図は従来の欠点を示すも
のである。第５図はこの考案の一実施例を示す平面図、
第６図はこの実施例のリードフレームを用いた場合の半
導体チップとダイパッド保持部とをワイヤボンド接続し
た状況を示す斜視図である。
図において、１はリードフレーム、２はグイパッド部、
３はダイパッド保持部、５ａはグイパッド部の金属メッ
キ層、５ｂはダイパッド保持部の金属メッキ層、６は半
導体チップ、７はろう材、８は金属細線である。なお、
図中同一符号は同一または相当部分を示す。Fig. 1 is a plan view showing a conventional lead frame, Fig. 2 is a front cross-sectional view showing one stage of assembly of a semiconductor device using such a lead frame, and Figs. 3 and 4 are conventional lead frames. FIG. 3 is a perspective view showing a situation in which a semiconductor chipper and a die pad holding part are connected by wire bonding when a semiconductor chipper and a die pad holding part are used. FIG. 3 shows an ideal case, and FIG. 4 shows a conventional drawback. FIG. 5 is a plan view showing an embodiment of this invention.
FIG. 6 is a perspective view showing a state in which a semiconductor chip and a die pad holding portion are connected by wire bonding when the lead frame of this embodiment is used. In the figure, 1 is a lead frame, 2 is a pad part,
Reference numeral 3 designates a die pad holding portion, 5a a metal plating layer of the guide pad portion, 5b a metal plating layer of the die pad holding portion, 6 a semiconductor chip, 7 a brazing material, and 8 a thin metal wire. In addition,
The same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
う付けされるグイパッド部、及びこのグイパッド部を保
持するとともに表面に形成された金属メッキ層と上記半
導体チップの電極端子とが金属細線でボンディング接続
されるダイパッド保持部を備えたものにおいて、上記グ
イパッド部の金属メッキ層と上記ダイパッド保持部の金
属メッキ層とが連続せず互いに分離して形成されたこと
を特徴とする半導体装置用リードフレーム。A pad part to which a semiconductor chip is brazed onto a metal plating layer formed on the surface, and a metal plating layer that holds this pad part and formed on the surface and electrode terminals of the semiconductor chip are bonded with thin metal wires. A lead frame for a semiconductor device comprising a die pad holding portion to be connected, wherein the metal plating layer of the die pad portion and the metal plating layer of the die pad holding portion are not continuous but formed separately from each other. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15385881U JPS5858354U (en) | 1981-10-14 | 1981-10-14 | Lead frame for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15385881U JPS5858354U (en) | 1981-10-14 | 1981-10-14 | Lead frame for semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5858354U true JPS5858354U (en) | 1983-04-20 |
Family
ID=29946459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15385881U Pending JPS5858354U (en) | 1981-10-14 | 1981-10-14 | Lead frame for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5858354U (en) |
-
1981
- 1981-10-14 JP JP15385881U patent/JPS5858354U/en active Pending
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