JPS5853146U - integrated circuit device - Google Patents

integrated circuit device

Info

Publication number
JPS5853146U
JPS5853146U JP1981147943U JP14794381U JPS5853146U JP S5853146 U JPS5853146 U JP S5853146U JP 1981147943 U JP1981147943 U JP 1981147943U JP 14794381 U JP14794381 U JP 14794381U JP S5853146 U JPS5853146 U JP S5853146U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
element mounting
back surface
adhesive paste
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1981147943U
Other languages
Japanese (ja)
Inventor
松島　政数
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP1981147943U priority Critical patent/JPS5853146U/en
Publication of JPS5853146U publication Critical patent/JPS5853146U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の集積回路装置の断面図、第２図は第１図
の集積回路素子とこれを搭載したリードフレームの素子
搭載部の部分を示す拡大図、第３図ａ、　　ｂ、　　ｃ
はそれぞれ本考案の一実施例に係る集積回路素子の裏面
図、そのＡ−Ａ断面図、およびリードフレームの素子搭
載部に搭載した状態を示す断面図、第４図ａ、　　ｂ、
　　ｃはそれぞれ本考案　−の他の実施例に係る集積回
路素子の裏面図、そのＡ−Ａ断面図、およびリードフレ
ームの素子搭載部に搭載した状態を示す断面図である。 １・・・・・・リードフレームの素子搭載部、２・・・
・・・接着用ペースト、３．　１３．　２３・・・・・
・集積回路素子、４・・・・・・外部導出リード、５・
・・・・・ボンディング電極、５′・・・・・・回路配
線、６・・・・・・ボンディングワイヤ、１４．２４・
・・・・・集積回路素子裏面の凹部。Fig. 1 is a sectional view of a conventional integrated circuit device, Fig. 2 is an enlarged view showing the integrated circuit element in Fig. 1 and the element mounting portion of a lead frame on which it is mounted, and Fig. 3 a, b, c.
4a and 4b are respectively a back view of an integrated circuit element according to an embodiment of the present invention, a cross-sectional view taken along line A-A thereof, and a cross-sectional view showing a state in which it is mounted on an element mounting portion of a lead frame.
3c is a rear view of an integrated circuit device according to another embodiment of the present invention, a cross-sectional view taken along line A-A, and a cross-sectional view showing a state in which the integrated circuit device is mounted on an element mounting portion of a lead frame. 1... Element mounting part of lead frame, 2...
...adhesive paste, 3. 13. 23...
・Integrated circuit element, 4...External lead, 5.
...Bonding electrode, 5'...Circuit wiring, 6...Bonding wire, 14.24.
...A recess on the back side of an integrated circuit element.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 集積回路素子裏面を素子搭載部材の素子搭載部に接着用
ペーストを用いて接着固定してなる集積回路装置におい
て、前記集積回路素子裏面には前記接着用ペーストが入
り込む凹部が設けられていることを特徴とする集積回路
装置。In an integrated circuit device in which a back surface of an integrated circuit element is adhesively fixed to an element mounting portion of an element mounting member using an adhesive paste, the back surface of the integrated circuit element is provided with a recess into which the adhesive paste enters. Features of integrated circuit devices.
JP1981147943U 1981-10-05 1981-10-05 integrated circuit device Pending JPS5853146U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981147943U JPS5853146U (en) 1981-10-05 1981-10-05 integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981147943U JPS5853146U (en) 1981-10-05 1981-10-05 integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5853146U true JPS5853146U (en) 1983-04-11

Family

ID=29940778

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981147943U Pending JPS5853146U (en) 1981-10-05 1981-10-05 integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5853146U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01135101U (en) * 1988-03-08 1989-09-14

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01135101U (en) * 1988-03-08 1989-09-14
JPH0530801Y2 (en) * 1988-03-08 1993-08-06

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