JPS5858343U - hybrid integrated circuit - Google Patents

hybrid integrated circuit

Info

Publication number
JPS5858343U
JPS5858343U JP15164281U JP15164281U JPS5858343U JP S5858343 U JPS5858343 U JP S5858343U JP 15164281 U JP15164281 U JP 15164281U JP 15164281 U JP15164281 U JP 15164281U JP S5858343 U JPS5858343 U JP S5858343U
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
package made
covered
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15164281U
Other languages
Japanese (ja)
Inventor
鳴海　雄二
Original Assignee
株式会社リコー
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社リコー filed Critical 株式会社リコー
Priority to JP15164281U priority Critical patent/JPS5858343U/en
Publication of JPS5858343U publication Critical patent/JPS5858343U/en
Pending legal-status Critical Current

Links

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の混成集積回路のパッケージング構造を示
す断面図、第２図は本考案による混成集積回路のパッケ
ージング構造の第１実施例を示す断面図、第３図は第２
の実施例を示す断面図である。 １・・・絶縁基板、２・・・部品、３・・・第１のパッ
ダー゛　ジ、５・・・第２のパッケージ。FIG. 1 is a sectional view showing a conventional packaging structure for a hybrid integrated circuit, FIG. 2 is a sectional view showing a first embodiment of a packaging structure for a hybrid integrated circuit according to the present invention, and FIG.
FIG. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Components, 3... First padage, 5... Second package.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 絶縁基板を含む実装部品全体を絶縁材料からなる第１の
パッケージで覆い、さらにその全体を磁性材料を含む材
料からなる第２のパッケージで覆ったことを特徴とする
混成集積回路。A hybrid integrated circuit characterized in that the entire mounted component including an insulating substrate is covered with a first package made of an insulating material, and the whole is further covered with a second package made of a material containing a magnetic material.
JP15164281U 1981-10-14 1981-10-14 hybrid integrated circuit Pending JPS5858343U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15164281U JPS5858343U (en) 1981-10-14 1981-10-14 hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15164281U JPS5858343U (en) 1981-10-14 1981-10-14 hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS5858343U true JPS5858343U (en) 1983-04-20

Family

ID=29944331

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15164281U Pending JPS5858343U (en) 1981-10-14 1981-10-14 hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS5858343U (en)

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