JPS5857807B2 - Data Ayamari Shiyorihoushiki - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a processing method for processing data after a blockout occurs in data written on a magnetic recording medium, such as a magnetic tape.Magnetic tape storage devices are difficult to handle. In recent years, information processing systems are expected to be smaller and cheaper, such as cassette tape devices, which are easy to record and have high recording accuracy.For computers, they can be used as a medium to replace conventional paper tapes and punch cards, and as auxiliary memory, input/output devices, various terminal devices, etc. used for 5
be.

The cassette tape has two tracks for recording, and in order to write data on it, a fixed pattern (01010101) indicating the beginning and end is added to each track as shown in FIG.・It is called an ampoule.

Also, before the postamble, that is, after the write data, 16
CRC (Cyclic Red
A CRC code is added, and this CRC code checks data during recording and playback.

In the case of a cassette tape device, the cassette tape has two tracks, but data is actually recorded on only one track, and there are no regulations regarding the other track.

That is, the same data as in one track may be written into the other track, or a data search signal may be written into the other track.

The user is free to decide how to use it.

By the way, for example, when the same data is recorded on both tracks as shown in FIG. 1, the data from one of the tracks is generally read.

If an error such as a dropout occurs in that track, data processing proceeds by reading data from the other track.

At this time, especially if the data is recorded using the phase modulation method, if dropout occurs, the phase (0", "1") of the data after dropout will be reversed, and the error probability will be Therefore, it is not possible to proceed with data processing by adopting this.

If a dropout occurs on only one track, you can use the data from the other track, but if a dropout also occurs on the other track, neither data can be used, and the data The process must be stopped and some recovery process performed.

An object of the present invention is to provide a dropout processing power formula that allows correct data to be obtained even if an error such as a dropout that makes subsequent data unreliable occurs independently on both tracks.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 2A is a block diagram of a data reading section on a magnetic recording medium, in which 1 is a magnetic head, 2 is an amplifier, 3 is a peak detector, and 4 is a demodulator.

FIG. 2B is a block diagram of an embodiment of the present invention, in which 5
and 6 are data input terminals, I and 8 are registers, 9 and 10 are data recovery detection circuits, and 11 generates a pulse to instruct the transfer of the contents of register 7 to register 8 or the contents of register 8 to register 7. 12 and 13 are AND circuits, 14 is a check circuit, 1
5 is a NOT circuit, 16 is an OR circuit, and 17 is a read data sending terminal.

As shown in FIG. 2A, data of two phase-modulated tracks read by the magnetic head 1 is amplified by an amplifier 2, passed through a peak detector 3, and demodulated by a demodulator 4. 2 data are applied to input terminals 5 and 6 in FIG. 2B, respectively.

- In FIG. 2B, the second and first data input to the input terminals 5 and 6 are respectively input to the second register 7.
The signal is input to the register 8 and is also input to the second data recovery detection circuit 9 and the first data recovery detection circuit 10.

Note that registers 7 and 8 are shift registers.

The second data recovery detection circuit 9 and the first data recovery circuit 10 (will be explained in detail later).

) is applied to the set clock 11, and this set clock 11 causes the second
The contents of register 2 and register 1 are transferred as necessary.

The outputs of the first register 8 and the second register 7 are input to the first input terminals of AND circuits 12 and 13, respectively, and are input to the check circuit 14 at the other end.

The output of the check circuit 14 is applied to the second input terminal of the AND circuit 12 and is also input to the second input terminal of the AND circuit 13 via the NOT circuit 15.

The outputs of AND circuits 12 and 13 are outputted to output terminal 17 via OR circuit 16 as read data.

Next, the dropout processing method configured as shown in FIG. 2B will be explained in detail with reference to FIGS. 3 and 4.

In Fig. 3, data D21 t D2□+D23
Second track data including r... and data D
ll l DI□.

Dl3. The first track data and the second track data including...
The interrelationship of the points 18 and 19 at which the dropout occurs in the track and the first track and the points 20 and 21 of the occurrence of the dropout pulse, ie the pulse for recovery, is made clear.

Data D , D , D , . . . in FIG. 3
...Dl.

21 22 23 D12 j Dl31 . . . each consists of a code of several pits, and forms, for example, a data block shown in FIG.

FIG. 4a shows the second data points corresponding to each track from the time point 18 when the second track causes a dropout, through the data restoration time point 20 after the dropout of the second track, to the time point 19 when the first track causes a dropout. register 7
and No. 8 (showing the accumulated contents of FIG. 2B).

In FIG. 4a, 22 indicates dropout.

Figure 4 shows a state in which the data D21 of the second track in which the dropout occurred, which was accumulated in the second register due to the generation of the data return pulse 20, is cleared and the contents of the register are set in the second register. shows.

FIG. 4C corresponds to each track from the time point 19 when a dropout occurs in the data D1□ of the first track, through the time point 21 when the data returns after the dropout of the first track, until the dropout occurs in the second track. Second
The contents accumulated in register 7 and register 8 are shown.

In FIG. 4C, 23 indicates dropout.

FIG. 4d shows that the data D1□ of the first track in which the dropout occurred, which was accumulated in the second register, is cleared by the generation of the data return pulse 21, and the contents of the second register are changed to the first track.
Indicates the state in which the register is set.

FIG. 4e shows the finally accumulated data in the first register and the second register.

The data for both tracks has been obtained in the above manner, but in consideration of the case where there is a dropout at the beginning or end of the data, the outputs of the second register 7 and the second register 8 are guided to the check circuit 14, and each data The data of the contents of the first and second registers are checked using the CRC code of When a dropout occurs in a channel, the data of the channel in which no dropout occurs is adopted and read data is output to the output terminal 17.

Next, when a dropout occurs, the data recovery detection circuits 9 and 10 of FIG. 2g will be explained below, taking the phase modulation recording method as an example.

FIG. 5 is a block diagram of the data recovery detection circuit in FIG. 2g, FIG. 6 is an explanatory diagram of the operation of the block diagram in FIG. 5th if there was
FIG. 2 is an explanatory diagram of the operation of the block diagram in the figure.

In FIG. 5, 51 is a rising pulse generation circuit CLI;
52 is a falling pulse generation circuit CL2.53°54 and 5
8 is monostable multi-by-break MSI, MS2
, MS3, 55 is a flip-flop FF, and 56 is a circuit CL4 that creates a falling pulse from the output of MS2.
．． 57 is a comparison circuit COM.

Reference numerals 59 and 60 indicate AND circuits AI, and A2.61 and 62 indicate OR circuits ORI and OR2, respectively.

6 and 7, a to f represent common elements in both FIGS. 6 and 7, and a is a phase-modulated read amplifier output waveform (hereinafter simply referred to as a phase-modulated waveform).

), b is the output waveform of the rising pulse generating circuit CLI in FIG. 5, and C is the falling pulse generating circuit C in FIG.
The output waveform of L2, d is the output waveform of the OR circuit 61 in FIG. 5, e is the output waveform of the monostable multi-by-break MSI in FIG. 5, and f is the output waveform of the flip-flop FF in FIG.

6g shows the output waveform of the OR gate 62 in FIG. 5, and g in FIG. 7 shows the output waveform of the monostable multi-by-break MS2 in FIG.
h is the output waveform of the falling pulse generation circuit CL4 in FIG. 5, i is the output waveform of the comparator circuit 7, j is the output waveform of the monostable multi-vibration rail MS3 in FIG. 5,
k indicates the output waveform of the OR circuit 62, respectively.

First, the normal operation will be explained with reference to FIGS. 5 and 6.

In the circuit of FIG. 5, the phase modulated waveform as shown in FIG.
When applied to the PE terminal in the figure, the rising pulse generation circuit 5
1 and a falling pulse generating circuit 52 generates a rising pulse CLI and a falling pulse CL2 as shown in FIGS. As a result, a waveform CL3 as shown in FIG. 6d is obtained.

This waveform CL3 is a monostable multi-by-break M
S1 is applied to trigger this multi-MS1.

This monostable multi-MSI has a time constant tw, :4
t (t is one period of the phase modulation waveform as shown in FIG. 6g), so when the waveform CL3 as shown in FIG. 6d is applied, the output becomes the waveform MS1 as shown in FIG. 6e. Become.

That is, since the monostable multi-MSI has a time constant tw1, it returns to zero only when no clock pulse is input until time t W 1 has elapsed since the last manual pulse.

As already mentioned, there is a rule that there is approximately one cycle at the point where the write data changes from '0'' to '1'' or from 1'' to On, so the falling point of the mono step multi-by-break MSI is defined as the data. is '0'' to 1''
Alternatively, it is a conversion point that changes from 1'' to 0''.

The data of the phase modulation waveform as shown in FIG. 6g thus read out appears at the output of the data flip-flop FF55 of FIG. 5 as a waveform as shown in FIG. 6f.

This is the read data.

FIG. 6g is a read clock in which rising pulse CL1, falling pulse CL2, and the output of data flip-flop FF are applied by AND circuits 59 and 60 and OR circuit 62 as the output of OR circuit OR2.

The normal operation of the block diagram of FIG. 5 in the case of no dropout has been described above. Next, the case of error correction in the case of dropout will be explained with reference to FIGS. 5 and 7.

The waveforms in Fig. 7 a, b, c, and d are those in Fig. 6 a, b.

This is exactly the same as c and d, and has been added redundantly for convenience of explanation.

If a dropout occurs in this case, as shown in Figure 7e, the output of the monostable multi-MS ■ will fall when the dropout time 3/t has elapsed, as if there had been a data change point. The output waveform FF of the data flip-flop shown in FIG. An error occurs with a probability of 1.

This is because, as already mentioned, in the phase modulation method, the beginning of data is defined as 0''.

Here, when the output of MSl is 0'', the PE waveform changes from O'' to Pa1'' or from 1'' to 011, and if the PE waveform continues for one cycle at 1'', then
This indicates that the information has changed from 0 to "1", and if the PE waveform continues at "0" for one cycle, it indicates that the information has changed from 1" to "0''.

Therefore, the output waveform of the flip-flop 55 must be ``1'' in the former case, and tl 011 in the latter case.

If this is not the case, there is an error in the data.

Furthermore, if there is an error, it can be seen that it is because the output waveform of the flip-flop 55 has been inverted.

Therefore, in the present invention, when an error is detected, the output waveform of the flip-flop is inverted again.

To set the timing for error detection, a monostable multi MS2 having a time constant tw2÷τt is provided as shown in FIG. 5, and this monostable multi MS2 is triggered by the fall of the output of the monostable multi MSI.

Therefore, the output waveform is a waveform M as shown in Fig. 7g.
S2, and by the falling pulse of this waveform MS2, a falling pulse CL4 as shown in Fig. 7 is obtained.

Then, by inputting this falling pulse CL4, the waveform PE of FIG. 7g and the FF waveform of f are compared in the comparison circuit, and if these pulses are not equivalent, the comparison circuit 57 as shown in FIG. This is the fifth
By applying the voltage to the monostable multi MS3 shown in the figure, the time constant 4w3 as shown in FIG.
The output of the flip-flop, ie, the data, is modified by generating a modifying pulse MS3 having a time t and applying it to the data flip-flop circuit FF to reset the data flip-flop.

If the waveform PE in FIG.
(see Figure 2B).

The read clock shown in FIG. 7k is obtained in the same manner as in FIG. 6g.

In addition, in the above explanation, P at the falling edge of the output waveform of MS2
The E waveform and FF waveform are compared, but this
This time point was selected by taking into consideration the logic delay time caused by the FF.

The output pulse of the monostable multi-by-break 58 is input to the set clock circuit shown in FIG. 2B.

As described above, according to the present invention, by keeping the contents of at least one register as correct data, even if an error such as a dropout that makes subsequent data unreliable occurs, as long as the error occurs at a different time, , can be obtained as correct data, so the reliability of the data can be improved and the data processing efficiency can be substantially improved.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a data block, FIGS. 2A and B are block diagrams of the method according to the present invention, FIGS. 3 and 4 are operation explanatory diagrams of the block diagram in FIG. 2B, and FIG. The figure is a block diagram of one embodiment of the data recovery detection circuit in Figure 2B, Figure 6 is an explanatory diagram of the operation of the circuit in Figure 5 when there is no dropout, and Figure 7 is an illustration of the operation of the circuit in Figure 5 when there is dropout. FIG. 6 is an explanatory diagram of the operation of the circuit shown in FIG. 5; In the figure, 7 and 8 are registers, 9 and 10 are data recovery detection circuits, and 11 is a set clock circuit.

Claims (1)

[Scope of Claims] 1. A magnetic recording and reproducing device that individually reads the same data written in a plurality of tracks of a magnetic recording medium using a phase modulation method and outputs the read data as read data, comprising: an accumulation means for individually accumulating read data from the plurality of tracks; an error detection circuit for detecting a dropout error in the read data from the plurality of tracks; and an error detection circuit for detecting a dropout error in the read data from the plurality of tracks; and a correction means for correcting subsequent read data, and according to the output from the error detection circuit,
The content of the accumulation means corresponding to the track where the error has occurred is set to the accumulation means corresponding to other tracks where the error does not occur until the end of the data block of the unit, and the read data of the track where the error has occurred is corrected by the correction means. A data error processing method characterized by: