JPS5856528A - Driving circuit for semiconductor - Google Patents

Driving circuit for semiconductor

Info

Publication number
JPS5856528A
JPS5856528A JP56153634A JP15363481A JPS5856528A JP S5856528 A JPS5856528 A JP S5856528A JP 56153634 A JP56153634 A JP 56153634A JP 15363481 A JP15363481 A JP 15363481A JP S5856528 A JPS5856528 A JP S5856528A
Authority
JP
Japan
Prior art keywords
current
semiconductor
drive
winding
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56153634A
Other languages
Japanese (ja)
Other versions
JPH0226813B2 (en
Inventor
Kenichi Onda
謙一 恩田
Kimihito Abe
阿部 公仁
Kohei Yabuno
薮野 光平
Takeshi Uemura
植村 剛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56153634A priority Critical patent/JPS5856528A/en
Priority to US06/424,369 priority patent/US4499530A/en
Priority to EP82109012A priority patent/EP0075947B1/en
Priority to DE8282109012T priority patent/DE3273040D1/en
Publication of JPS5856528A publication Critical patent/JPS5856528A/en
Publication of JPH0226813B2 publication Critical patent/JPH0226813B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/22Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)
  • Dc-Dc Converters (AREA)
  • Power Conversion In General (AREA)

Abstract

PURPOSE:To obtain a power converter with small size and high efficiency while attaining high-speed turn-off, by supplying a positive driving current from a driving circuit power supply at turn-on to a control gate of a semiconductor and a negative driving current from a main circuit at turn-off. CONSTITUTION:A transistor (TR)Q1 turns on with a control circuit 3, a voltage is induced to windings n4, n5 of a base driving rransformer TB and a power TRQM is turned on by being supplied with a positive base current. Thus, the base.emitter of a TRQ2 are back-biased with a voltage drop of a diode D2 and the TRQ2 is turned off and a voltage is remained induced in a winding n3 of a main transformer TM. In interrupting a base current to the TRQ1 from the circuit 3, the Q1 is turned off. Thus, the TRQ2 turns on and a negative base current flows to the TRQM through the Q2 from the winding n3 to rapidly turn on the QM. Since the negative base current is obtained from a main circuit at the QM turned off, a driving power supply has only to supply required power for turning-on of the QM, allowing to attain small size.

Description

【発明の詳細な説明】 本発明は半導体の駆動回路に係り、特にパワトランジス
タ、GTO,MOS FET等の半導体素子を高速でタ
ーンオフさせるに好適な駆動回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor drive circuit, and particularly to a drive circuit suitable for turning off semiconductor elements such as power transistors, GTOs, and MOS FETs at high speed.

従来ノパワトランジスタの駆動回路は、ベース駆動用変
圧器を介して駆動する方式が広く用いられている。この
方式は、ベース駆動用変圧器中に蓄積される励磁電流の
放出によって逆方向にべ一スミ流を流し、ターンオフ時
間の短縮を図っている。しかしこの方式では、ベース駆
動用変圧器中に蓄積される励磁電流が、トランジスタの
導通時間を制御する制御時間に比例して変化する為、導
通時間を短かく制御しようとする程逆方向のベース電流
が減少し、トランジスタのターンオフ時間が長くなる欠
点があった。
Conventional drive circuits for no-power transistors have widely used a system in which they are driven via a base drive transformer. This method aims to shorten the turn-off time by causing a base current to flow in the opposite direction by releasing the excitation current accumulated in the base drive transformer. However, in this method, the excitation current accumulated in the base drive transformer changes in proportion to the control time that controls the conduction time of the transistor. This has the disadvantage that the current decreases and the turn-off time of the transistor becomes longer.

まだ、GTOのターンオフに必要なゲート電流(以下オ
フゲート電流)は、立上りの速いパルス電流を流す程タ
ーンオフ時間を短かくできる。オフゲート電流の立上シ
を速くするには、オフゲート電流を供給する電源の電圧
を高くすることで可能となるが、GTOのゲート、カソ
ード間の耐電圧が20V程度であり、オフゲート電流を
供給する電源の電圧に制限を与える。この為、従来のG
TOのゲート回路は、GTOを高速度でターンオフさせ
る為、オフゲート電流の流れ始めは高い電圧を出力でき
、ターンオフの進行に従ってゲート回路の出力電圧を低
下させる方式等が用いられており、ゲート回路の複雑化
を招いていた。
However, as for the gate current (hereinafter referred to as off-gate current) required for turning off the GTO, the turn-off time can be shortened by passing a pulse current with a faster rise. To speed up the rise of the off-gate current, it is possible to increase the voltage of the power supply that supplies the off-gate current, but the withstand voltage between the gate and cathode of the GTO is about 20V, Limit the voltage of the power supply. For this reason, the conventional G
In order to turn off the GTO at high speed, the gate circuit of the TO can output a high voltage at the beginning of the off-gate current flow, and as the turn-off progresses, the output voltage of the gate circuit is reduced. This led to complications.

さらに、MOSFETの大容量化に伴って、Mo5FE
T内部に存在する等価容量も大きくなっている。MOS
 Ii”ETのスイッチング時間は、MO8FET内部
のゲート電極とノース電極間に存在する等価容量(ゲー
ト入力容量)の充放電時間で決定される為、MOSFE
Tの特徴である高速スイッチング特性を十分活用するに
は、スイッチング時にピーク値の大きな電流を流す必要
が生じ、ゲート駆動電力の増大、ゲート回路の大型化を
招いている。
Furthermore, with the increase in capacity of MOSFET, Mo5FE
The equivalent capacitance existing inside T is also larger. M.O.S.
The switching time of Ii"ET is determined by the charging and discharging time of the equivalent capacitance (gate input capacitance) that exists between the gate electrode and the north electrode inside the MO8FET, so the MOSFE
In order to fully utilize the high-speed switching characteristics that characterize T, it is necessary to flow a current with a large peak value during switching, resulting in an increase in gate drive power and an increase in the size of the gate circuit.

この様に、パワトランジスタ、GTO。In this way, power transistor, GTO.

MOS、FET等の半導体素子は、いずれもターンオフ
時に立上シが速く、ピーク値の大きな負極性の駆動電流
を供給する程、ターンオフ時間が短縮し、高周波駆動が
可能となるが、駆動電力の増大、これに伴う回路の大型
化や、駆動回路の複雑化を招き、高周波駆動を容易に実
現できない欠点があった。
Semiconductor devices such as MOS and FET all start up quickly at turn-off, and the more a negative polarity drive current with a large peak value is supplied, the shorter the turn-off time becomes and the higher the frequency drive becomes possible, but the lower the drive power becomes. This has led to an increase in the size of the circuit and the complexity of the drive circuit, which has the disadvantage that high-frequency drive cannot be easily realized.

本発明の目的は、簡単な構成で立上シが速く、ビー、り
値の大きな負極性の駆動電流を主回路から得る様にし、
半導体を高速にターンオフさせて高周波動作を容易にす
ると共に、半導体の駆動回路用電源の電力を低減させ、
小型、高効率の電力変換装置を提供することにある。
The object of the present invention is to provide a simple configuration, fast start-up, and to obtain a negative polarity drive current with a large beam value from the main circuit.
Turns off the semiconductor at high speed to facilitate high-frequency operation, and reduces the power consumption of the power supply for the semiconductor drive circuit.
The purpose of the present invention is to provide a small, highly efficient power conversion device.

本発明は、半導体にターンオフ指令が出力された後も、
蓄積時間の間は半導体が導通状態を保っていることを利
用したものである。主変圧器を介して負荷に電力の供給
を行う場合、半導体の蓄積時間は、主変圧器の各巻線に
電圧が誘起されたままになっている。このため、半導体
に負極性の駆動電流を流す巻線をもうけ、半導体に与え
られるターオフ指令によって負極性の駆動電流を流す様
にすれば、蓄積時間の間は負極性の駆動電流を得ること
ができる。
In the present invention, even after a turn-off command is output to the semiconductor,
This method takes advantage of the fact that the semiconductor remains conductive during the storage time. When power is supplied to the load via the main transformer, the semiconductor storage time is such that voltage remains induced in each winding of the main transformer. Therefore, if a winding is provided in the semiconductor to flow a negative drive current, and the turn-off command given to the semiconductor is used to cause the negative drive current to flow, it is possible to obtain a negative drive current during the accumulation time. can.

半導体がターンオフした後は、主変圧器の各巻線に誘起
していた電圧が無くなる為、ターンオフ動作を終了した
半導体の制御電極に過大な逆電圧が印加される心配が無
い。この為、主変圧器に設けた負極性の駆動電流を流す
巻線から出力される電圧は十分高い値に設定でき、立上
りの速い負極性の駆動電流を得ることができる。
After the semiconductor is turned off, the voltage induced in each winding of the main transformer disappears, so there is no need to worry about excessive reverse voltage being applied to the control electrode of the semiconductor that has finished its turn-off operation. Therefore, the voltage output from the winding provided in the main transformer through which negative polarity drive current flows can be set to a sufficiently high value, and a negative polarity drive current with a fast rise can be obtained.

以下、本発明の一実施例を第1図によって説明する。第
1図は、1石フォワード型のスイッチングレギュレータ
であシ、半導体としてトランジスタQMを使用した場合
である。図において1は整流回路、CMは入力平滑コン
デンサ、TMは主変圧器であシ、01  ! n2 t
 03は主変圧器に設けた巻線であり、それぞれ1次巻
線、出力巻線、負極性Ωベース電流を供給する巻線であ
る。2は制御回路3及び、[・ランジスタQMに正極性
のペース電流を供給する駆動用電源、3は、出力電圧横
用信号Vsによって、出力電圧を一定に保つ様にQMを
駆動する信号を形成する制御回路である。
An embodiment of the present invention will be described below with reference to FIG. FIG. 1 shows a case where a single-transistor forward type switching regulator is used, and a transistor QM is used as the semiconductor. In the figure, 1 is the rectifier circuit, CM is the input smoothing capacitor, TM is the main transformer, and 01! n2 t
03 is a winding provided in the main transformer, which is a primary winding, an output winding, and a winding that supplies a negative Ω base current, respectively. 2 is a control circuit 3 and a drive power source that supplies a positive pace current to the transistor QM; 3 is a horizontal output voltage signal Vs that forms a signal that drives the QM so as to keep the output voltage constant; This is a control circuit that

4の出力整流ダイオード、5は出力平滑りアク]・/l
−6の電流を還流させるダイオード、7は出力平滑コン
デンサである。8,9はそれぞれ、QMのター/オフ時
に、TM中の励磁電流を放出させるダイオードと抵抗で
ある。DlはTMの励磁電流を阻止するダイオード、R
Iは負極性のペース電流を制限する抵抗、Q2は巻線n
、の出力電流を、QMをターンオフさせる時点まで阻止
するトランジスタである。TBは、QMの正極性のベー
ス電流を絶縁して流す為のベース駆動用変圧器、R2は
正極性のベース電流制限抵抗、Qlは、3からの出力に
応じてスイッチングし、QMを駆動するトランジスタ、
R2は、Qlのターンオフ時に放出されるTBの励磁電
流を、Q2のベース電流とする為のダイオードであり、
同時に正極性のベース電流供給時には、Q2のエミッタ
、ベース間を順方向電圧降下によって逆バイアスする役
割も持つ。R8はQ2のベース電流制限抵抗である。
4 is the output rectifier diode, 5 is the output smoothing ac]・/l
-6 is a diode that circulates the current, and 7 is an output smoothing capacitor. 8 and 9 are a diode and a resistor, respectively, which release the excitation current in the TM when the QM is turned off/off. Dl is a diode that blocks the excitation current of TM, R
I is a resistor that limits the negative pace current, Q2 is the winding n
, which blocks the output current of QM until it turns off. TB is a base driving transformer for insulating and passing the positive base current of QM, R2 is a positive base current limiting resistor, and Ql is switched according to the output from 3 to drive QM. transistor,
R2 is a diode that uses the excitation current of TB released when Ql is turned off as the base current of Q2,
At the same time, when supplying a positive base current, it also has the role of reverse biasing the emitter and base of Q2 by a forward voltage drop. R8 is the base current limiting resistor of Q2.

本構成のスイッチングレギュレータの動作は一般に良く
知られているので、動作の説明は省略し、QMのスイッ
チング時の動作のみ述べることにする。
Since the operation of the switching regulator of this configuration is generally well known, a description of the operation will be omitted and only the operation during QM switching will be described.

制御回路3から、QLにベース電流が供給されると、Q
lがターンオンし、ベース駆動用トランスTnの巻線n
4 e R5には、図示黒丸を正極性とする電圧が誘起
され、QMに正極性のベース電流が供給されて、QMが
ター/オンする。QMのターンオンによって、TMの各
巻線には図示黒丸を正極性とする電圧が誘起し、巻線n
、、n2に電流が流れる。これと同時に巻線n、にも図
示黒丸を正極性とする電圧が誘起している。しかし、ト
ランジスタQ2は、QMに供給している正極性のベース
電流がダイオードD2に流れる為、R2の電゛圧降下に
よってエミッタ、ベース間が逆バイアスされていること
により、正極性のベース電流がQMに与えられている間
は確実にオフ状態を持続する。このため、’QMのオン
期間には、巻線n3に電圧が誘起されるだけで電流はQ
2がターンオンするまで流れることができない。
When the base current is supplied to QL from the control circuit 3, Q
l is turned on, and the winding n of the base driving transformer Tn
4 e A voltage having positive polarity as shown in the black circle is induced in R5, a positive base current is supplied to QM, and QM is turned on. By turning on the QM, a voltage with positive polarity indicated by the black circle in the figure is induced in each winding of the TM, and the voltage of the winding n
, , a current flows through n2. At the same time, a voltage with positive polarity indicated by the black circle in the figure is also induced in the winding n. However, in transistor Q2, since the positive base current supplied to QM flows to diode D2, the positive base current is reverse biased between the emitter and base due to the voltage drop of R2. The off state is maintained reliably while being given to QM. Therefore, during the ON period of 'QM, only a voltage is induced in the winding n3 and the current is QM.
It cannot flow until 2 is turned on.

次KQ、rのターンオフ時について述べる。制御回路3
からトランジスタQ1に供給されるベース電流がしゃ断
されると、QLがターンオフする。
Next, the turn-off of KQ and r will be described. Control circuit 3
When the base current supplied to transistor Q1 from QL is cut off, QL is turned off.

これにより、Q、の導通時に変圧器TB中に流れていた
励磁電流によって巻線n4 + ”5には図示黒丸と逆
方向を正極性とする電圧が発生し、巻線n、から抵抗R
a 、Q2のベース、エミッタ、QMのエミッタ、ベー
スを通る電流が流れ、Q2がター7オンする。Q2がタ
ーンオンした時点では、QMの正極性のベース電流はし
ゃ断されているが、QMはただちにターンオフできず、
蓄積時間の間はオン状態を接続しているため、主変圧器
TMの各巻線には図示黒丸を正極性とする電圧が誘起し
たままとなっている。従って、Q2のターンオンによシ
、巻線n3からはQ2のコレクタ、エミッタ、QMのエ
ミッタ、ベース、抵抗R11ダイオードD1を通る電流
が流れ、QMに負極性のベース電流を流す。Q2のター
ンオンによって巻線n、を流れる電流IRは、回路各部
の電圧降下を無視すれば次式で与えられる。
As a result, a voltage whose polarity is opposite to the black circle shown in the figure is generated in the winding n4 + ``5 due to the exciting current flowing in the transformer TB when Q is conductive, and a voltage is generated from the winding n to the resistor R.
A, current flows through the base and emitter of Q2, and the emitter and base of QM, turning Q2 on. When Q2 turns on, the positive base current of QM is cut off, but QM cannot turn off immediately.
Since the ON state is maintained during the accumulation time, a voltage whose polarity is positive as indicated by the black circles in the figure remains induced in each winding of the main transformer TM. Therefore, when Q2 is turned on, a current flows from the winding n3 through the collector and emitter of Q2, the emitter and base of QM, and the resistor R11 and diode D1, causing a negative base current to flow through QM. The current IR flowing through the winding n when Q2 is turned on is given by the following equation, if voltage drops at various parts of the circuit are ignored.

ここに、vCMはコンデンサCMの充電々圧、n、、R
3はそれぞれの巻線数である。
Here, vCM is the charging voltage of capacitor CM, n, , R
3 is the number of windings in each.

(1)式より、QMの負極性のベース電流はR3の巻線
数、抵抗R1の値によって自由に選定でき、十分大きな
負極性のベース電流をQvに供給できる。
From equation (1), the negative base current of QM can be freely selected depending on the number of turns of R3 and the value of resistor R1, and a sufficiently large negative base current can be supplied to Qv.

負極性のベース電流によってQMのターンオフ時間が短
縮され、QMがターンオフすると、TM中に流れていた
励磁電流が抵抗9、ダイオード8を通して放出されるが
、この時、TMの各巻線には図示黒丸と逆方向を正極性
とする電圧が発生する。巻線3に発生したこの電圧は、
ダイオードD、によって阻止される。従って、QMに与
えられる負極性のべ一ヌ電流は、QMのターンオフと同
時にしゃ断されることにより、ターンオフを終了したQ
、のベース電極に過大な逆電圧を印加する心配がない。
The turn-off time of the QM is shortened by the negative base current, and when the QM is turned off, the excitation current flowing in the TM is discharged through the resistor 9 and the diode 8, but at this time, each winding of the TM has a black circle as shown in the figure. A voltage with positive polarity in the opposite direction is generated. This voltage developed in winding 3 is
is blocked by diode D. Therefore, the negative polarity base current applied to the QM is cut off at the same time as the QM is turned off.
, there is no need to worry about applying excessive reverse voltage to the base electrode.

このことは、巻線n3の出力電圧を十分大きく選定して
も、QMのベース電極に過大な逆電圧が印加されないこ
とを意味している。
This means that even if the output voltage of the winding n3 is selected to be sufficiently large, an excessive reverse voltage will not be applied to the base electrode of the QM.

従って、巻線n3の出力電圧はQ、のベース、エミッタ
間逆耐電圧よりも十分大きく選定でき、Tyの洩れイン
ダクタンスや、配線のインダクタンス等が存在しても、
立上シの速い負極性のベース電流を流すことができる。
Therefore, the output voltage of winding n3 can be selected to be sufficiently larger than the reverse withstand voltage between the base and emitter of Q, and even if there is leakage inductance of Ty, wiring inductance, etc.
A negative base current with a fast rise time can be passed.

次に、Qlがターンオンし、QMに正極性のベース電流
が供給されると、ダイオードD2の電圧降下によって、
Qlは速やかに、かつ確実にターンオフする。
Next, when Ql is turned on and a positive base current is supplied to QM, the voltage drop across diode D2 causes
Ql turns off quickly and reliably.

以上の様に、本実施例に依れば、Q、のターンオフ時に
、負極性のベース電流を主回路から得ることができるの
で、駆動用電源2は、QMのターンオンに必要な電力を
供給すれば良く、従来の様にTB中に蓄積した励磁電流
によってQMに負極性のベース電流を供給する方式に比
べ、駆動用電源2の必要電力は大略1/2で良い。これ
に伴ってTs、Q+の小型化を図れることはtうまでも
無い。
As described above, according to this embodiment, when Q is turned off, a negative base current can be obtained from the main circuit, so the drive power supply 2 has to supply the power necessary for turning on Q. The power required for the driving power source 2 can be approximately 1/2 compared to the conventional method of supplying a negative base current to the QM using the excitation current accumulated in the TB. It goes without saying that along with this, Ts and Q+ can be made smaller.

また、本実施例ではターンオフを終了したQMのベース
電極に過大な逆電圧が印加される心配が無い為、巻線n
、の出力電圧を十分高く選定でき、QMの負極性のベー
ス電流の立上シを速くすることができると共に、(I)
式で示される如(R,及びn3の選定によってピーク値
の大きな電流を得ることができるので、QMのターンオ
フ時間を大幅に短縮することができる。−実験例に依れ
ば、従来方式で1.5μSeCのターンオフ時間である
QMを、本実施例では0.3μsecのター/オフ時間
にできる効果を確認している。
In addition, in this embodiment, there is no concern that an excessive reverse voltage will be applied to the base electrode of the QM that has completed turn-off, so the winding n
, the output voltage of (I) can be selected to be sufficiently high, and the rise of the negative base current of QM can be made faster.
As shown in the equation (by selecting R and n3, it is possible to obtain a current with a large peak value, so the turn-off time of the QM can be significantly shortened. In this embodiment, it has been confirmed that the QM, which is a turn-off time of .5 μSec, can be reduced to a turn-off time of 0.3 μsec.

第2図に、GTOを用いた場合の実施例を示す。FIG. 2 shows an embodiment using GTO.

回路各部の動作は第1図の場合と同様である。The operation of each part of the circuit is the same as in the case of FIG.

周知の通力、GTOはターンオフ時に短時間ではあるが
、ピーク値の大きなオフゲート電流を必要とし、このた
めに駆動用電源2の電力増大や、ゲート回路の複雑化を
招いている。また、GTOを高速ターンオフするには、
オフゲート電流の立上シを速くして、ピーク値の十分大
きな電流を供給することが必須不可欠である。
The well-known power supply, GTO, requires an off-gate current with a large peak value, albeit for a short time at turn-off, which results in an increase in the power of the driving power source 2 and a complicated gate circuit. Also, to turn off the GTO at high speed,
It is essential to speed up the rise of the off-gate current and supply a current with a sufficiently large peak value.

本実施例では、GTOのオフゲート電流を主回路から得
られる為、駆動電源2の電力低減と共に回路の小型化、
簡略化が可能である。寸だ、第1図の動作で述べた通り
、GTOのターンオフと供に、巻線n8の出力電圧が反
転する為、GTOのゲート電極に過大な逆電圧を印加す
る心配が無く、巻線n3の出力電圧をゲート、カソード
間逆耐電圧以上に選定できる。このことは、ピーク値の
大きな立上シの速いオフゲート電流を流せることを意味
し、GTOを高速ターンオフさせ得ることになる。
In this embodiment, since the off-gate current of the GTO can be obtained from the main circuit, the power of the drive power supply 2 is reduced and the circuit is miniaturized.
Simplification is possible. As mentioned in the operation in Figure 1, the output voltage of the winding n8 is reversed when the GTO turns off, so there is no need to worry about applying an excessive reverse voltage to the gate electrode of the GTO, and the output voltage of the winding n3 is reversed. The output voltage can be selected to be higher than the reverse withstand voltage between gate and cathode. This means that an off-gate current with a large peak value and a fast rise can flow, and the GTO can be turned off quickly.

第3図にMOS FETを用いた場合の実施例を示す。FIG. 3 shows an example in which a MOS FET is used.

図示しだMOS FETはNチャンネルのへ10s F
ETであり、ゲート電極が、ソース電極に対して正極性
にバイアスされると導通し、バイアス電圧が取り去られ
るとターンオフする半導体素子である。本実施例は、第
1図の実施例のQMがMoB2に、Q2がMOS2に、
QlがMOS3にそれぞれ置き換えたもので、回路動作
は第1図、第2図の場合と同様である。
The MOS FET shown in the diagram is 10s F to N channel.
ET, which is a semiconductor device that conducts when the gate electrode is positively biased with respect to the source electrode and turns off when the bias voltage is removed. In this embodiment, QM in the embodiment of FIG. 1 is MoB2, Q2 is MOS2,
Ql is replaced with MOS3, and the circuit operation is the same as in FIGS. 1 and 2.

MOS FETの特徴は、トランジスタやG T O等
と比べ、スイッチング速度が速い、ゲートドライブ電力
が小さい等の優れた特徴を持つ。
Compared to transistors, GTOs, etc., MOS FETs have superior features such as faster switching speed and lower gate drive power.

MOS FETのスイッチング速度は、八f’s FE
T内部に存在する等価容量に大きく依存し、ゲート、ソ
ース電極間に存在する等価容量(以下人力容重)の充放
電時間でスイッチング速度が決定される。
The switching speed of MOS FET is 8f's FE
The switching speed is largely dependent on the equivalent capacitance existing inside the T, and is determined by the charging/discharging time of the equivalent capacitance (hereinafter referred to as human power capacity) existing between the gate and source electrodes.

また、MOS FETの駆動電力も人力容量の充放電エ
ネルギーで決定される。
Further, the driving power of the MOS FET is also determined by the charging/discharging energy of the human power capacity.

最近へ408 PETの大容量化が進み、従って入力容
量も大きくなる傾向にある。
Recently, the capacity of 408 PET has been increasing, and accordingly, the input capacity has also tended to increase.

これに伴い、MOSFETの高速スイッチング特性、低
駆動電力等の特徴を十分活用するには、ピーク値の大き
なゲート電流を低損失で供給できるゲート回路が必要と
なっている。
Accordingly, in order to fully utilize the characteristics of MOSFETs such as high-speed switching characteristics and low driving power, a gate circuit that can supply a gate current with a large peak value with low loss is required.

本実施例に依れば、入力容量を充電する電力だけを駆動
用電源2から得、放電させる電力は主回路から得るため
、MOSFETの入力容量が増大しても、駆動用電源2
の電力を大幅に増大させること無い。また、第1図、第
2図の実施例で述べた通り、入力容量を放電させる電力
を主回路から得るため、短時間で入力容量の放電が可能
であり、MOSFETの入力容量が増大しても高速ター
ンオフ特性を失うことが無い。
According to this embodiment, only the power for charging the input capacitance is obtained from the drive power supply 2, and the power for discharging is obtained from the main circuit, so even if the input capacitance of the MOSFET increases, the drive power supply 2
without significantly increasing power. In addition, as described in the embodiments shown in Figures 1 and 2, since the power to discharge the input capacitance is obtained from the main circuit, the input capacitance can be discharged in a short time, and the input capacitance of the MOSFET increases. However, the high-speed turn-off characteristics are not lost.

第4図に、本発明をインバータに適用した場合の一実施
例を示す。図においてCM[+ CM2は入力平滑ダイ
オード、QM [y QM 2は主スイツチングトラン
ジスタ、TBI 、TB2はそれぞれQMl 、QM2
を駆動するためのベース駆動用変圧器、n41 + n
51 + ”42 + ”52はそれぞれTnI。
FIG. 4 shows an embodiment in which the present invention is applied to an inverter. In the figure, CM[+CM2 is the input smoothing diode, QM[y QM2 is the main switching transistor, TBI and TB2 are QMl and QM2, respectively.
Base drive transformer for driving n41 + n
51 + "42 + "52 are each TnI.

Tn2に設けた1次、2次巻線、TMは主変圧器、nl
 + n2 + n31 + n32はTyに設けた巻
線、D5 、Doは巻線n3□、n32の出力を整流す
るダイオード、R4−R5はそれぞれQMt + QM
 2の負極性のベース電流を制限する抵抗、Qa。
Primary and secondary windings installed in Tn2, TM is the main transformer, nl
+ n2 + n31 + n32 is the winding provided on Ty, D5 and Do are diodes that rectify the output of windings n3□ and n32, and R4-R5 are QMt + QM, respectively.
A resistor Qa limits the negative polarity base current of No. 2.

Q4はそれぞれQM t t QM 2の負極性のベー
ス電流をスイッチングするトランジスタ、D3’+D4
はそれぞれTn L 、 TB 2の励磁電流が放出さ
れる時、この電流をQs、 Q、のベース電流とする為
のダイオード、Ra 、 R,はそれぞれQ31Q4の
ベース電流制限抵抗、Q、、QeはそれぞれQM(、Q
M2の駆動用ダイオード、D、。
Q4 is a transistor that switches the negative polarity base current of QM t t QM 2, respectively, D3'+D4
are the diodes for making this current the base current of Qs and Q when the excitation current of Tn L and TB 2 is released, Ra and R are the base current limiting resistors of Q31 and Q4, respectively, and Q, , and Qe are the base current limiting resistors of Q31 and Q4, respectively. QM(,Q
M2 driving diode, D.

D8は出力整流用ダイオードである。D8 is an output rectifying diode.

図示した回路は、ハーフブリッジインバータの回路とし
て広く知°られておシ、インバータ動作の説明は省略す
る。制御回路3から、トランジスタQ、にベース電流が
供給されると、Qaがターンオンし、駆動用電源2から
ベース駆動用変圧器Tnlを介してQMIに正極性のベ
ース電流が供給され、QMIが導通状態となる。QMI
の導通に依って、コンデンサCMIからTMの巻線n1
に電流が流れ、02巻線から負荷に電力の供給がなされ
ると共に、巻線n31+03□には図示黒丸を正極性と
する電圧が誘起する。巻線n31の電流はトランジスタ
Q3で、巻線n32の電流はダイオードD6で阻止され
ている為、両方の巻線には電圧が誘起されるだけで電流
は流れない。
The illustrated circuit is widely known as a half-bridge inverter circuit, and a description of the inverter operation will be omitted. When a base current is supplied from the control circuit 3 to the transistor Q, Qa is turned on, and a positive base current is supplied from the drive power supply 2 to QMI via the base drive transformer Tnl, making QMI conductive. state. QMI
Due to the conduction of the capacitor CMI to the winding n1 of TM
A current flows through the winding 02, power is supplied to the load from the winding 02, and a voltage whose polarity is positive as shown by the black circle is induced in the winding n31+03□. Since the current in the winding n31 is blocked by the transistor Q3 and the current in the winding n32 is blocked by the diode D6, only a voltage is induced in both windings and no current flows.

次に、制御回路3からQ、に供給されていたベース電流
がしゃ断され、Qaがターンオフすると、 。
Next, when the base current supplied from the control circuit 3 to Q is cut off and Qa is turned off,

Q、のオン期間にTnI中に蓄積された励磁電流が抵抗
Ra 、 Qaのベース、エミッタ、QMIのエミッタ
、ベースを通して放出され、Qaがターンオンする。Q
、のターンオン直後ハ、QM l (7)蓄積時間によ
シ、主変圧器TMの各巻線には図示黒丸を正極性とする
電圧が誘起されておシ、巻線n31からQaのコレクタ
、エミッタ、QMI のエミッタ、ベースを通して電流
が流れ、QMIを高速度でターンオフする。QMI の
ターンオフによって、TMの各巻線には図示黒丸と逆方
向を正極性とする電圧が誘起するが、巻線n3tの電圧
はダイオードD、で、巻線n32の電圧はトランジスタ
Q4で阻止する為、電流は流れない。QM2が動作する
時も同様に各部が働き、QM2を高速度でター/オフさ
せる。
During the ON period of Q, the excitation current accumulated in TnI is released through the resistors Ra, the base and emitter of Qa, and the emitter and base of QMI, turning Qa on. Q
Immediately after the turn-on of , QM l (7) Depending on the accumulation time, a voltage whose polarity is positive as indicated by the black circle in the figure is induced in each winding of the main transformer TM, and from the winding n31 to the collector and emitter of Qa. , the current flows through the emitter and base of QMI, turning it off at high speed. When QMI is turned off, a voltage with positive polarity in the opposite direction to the black circle shown is induced in each winding of TM, but the voltage of winding n3t is blocked by diode D, and the voltage of winding n32 is blocked by transistor Q4. , no current flows. When QM2 operates, each part works in the same way, turning QM2 on and off at high speed.

本実施例によっても、第1図と同様の効果を得ることが
できる。
According to this embodiment as well, the same effects as in FIG. 1 can be obtained.

また、第2図、第3図に示・した様にノ・−7ブリツジ
インバ一タ回路にGTO,MOS FETを使用した場
合も、同様に本発明が実施できる。
Furthermore, the present invention can be implemented in the same manner when GTO and MOS FET are used in the No.-7 bridge inverter circuit as shown in FIGS. 2 and 3.

また、本実施例は、プッシュプルインノく一夕やブリッ
ジインバータ、1石フンイバツフコンノ(−タ等にも適
用できることは第1図〜第4図の実施例から明らかであ
る。
Further, it is clear from the embodiments shown in FIGS. 1 to 4 that this embodiment can be applied to a push-pull inverter, a bridge inverter, a one-stone power converter, etc.

本発明によれば、立上シが速く、ピーク値の大きな負極
性の駆動電流を主回路から半導体に供給できるため、半
導体を従来の回路方式に比較し5倍程度の高速度でター
ンオフさせることができ、高周波動作を簡単な駆動回路
で実現できる。tた半導体の駆動回路用電源の電力を従
来の1/2以下にでき、小型、高効率の電力変換装置を
提供できる効果がある。
According to the present invention, since the start-up is fast and a negative drive current with a large peak value can be supplied from the main circuit to the semiconductor, the semiconductor can be turned off at a speed approximately five times faster than in conventional circuit systems. , and high-frequency operation can be achieved with a simple drive circuit. The power of the power supply for the semiconductor drive circuit can be reduced to 1/2 or less of the conventional power supply, which has the effect of providing a compact and highly efficient power conversion device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す図、第2図〜第4図は
本発明の他の実施例を示す図である。 QMI QM l + QM2・・・主スイツチングト
ランジスタ、GTO・・・ゲートター/オフサイリスタ
、MO8I・・・MOS FET、TM・・・主変圧器
、TB・・・ベース駆動用変圧器、n3 p ”31 
+ n32・・・負極性駆動電流供給巻線、Q2 、”
MOS2.Qs 、Q4・・・負  1第 2 図
FIG. 1 is a diagram showing one embodiment of the invention, and FIGS. 2 to 4 are diagrams showing other embodiments of the invention. QMI QM l + QM2...Main switching transistor, GTO...Gator/off thyristor, MO8I...MOS FET, TM...Main transformer, TB...Base drive transformer, n3 p" 31
+ n32...Negative polarity drive current supply winding, Q2,"
MOS2. Qs, Q4...Negative 1 Fig. 2

Claims (1)

【特許請求の範囲】 1、半導体の制@1電極にターンオン時には正極性の駆
動電流を供給し、ターンオフ時には負極性の駆動電流を
供給する半導体の駆動回路において、上記正極性の駆動
電流は駆動回路用電源から供給し、上記負極性の駆動電
流は主回路から供給する様にしたことを特徴とする半導
体の駆動回路。 2、特許請求の範囲第1項において、前記負極性の駆動
電流は、負荷に電力の供給を行なう変圧器に設けた巻線
から供給する様にしたことを特徴とする半導体の駆動回
路。 3、特許請求の範囲第2項において、前記負極性の駆動
電流を供給する巻線は、半導体スイッチと第1のダイオ
ードを介して前記半導体の制御電極と、一方の主電極に
接続することを特徴とする半導体の駆動回路。 4、特許請求の範囲第3項において、前記正極性の駆動
電流は駆動回路用電源から駆動用変圧器を介して供給す
ると共に、前記半導体スイッチは上記駆動用変圧器の励
磁電流の放出によってターンオンする様にしたことを特
徴とする半導体の駆動回路。 5、特許請求の範囲第4項において、前記駆動用変圧器
の出力巻線は、一方が半導体の制御電極に接続され、他
方は第2のダイオードを介して半導体の一方の主電極に
接続されると共に、前記半導体スイ゛ツチの制御電極は
、上記第2のダイオードのカソード側に、上記一方の主
電極はアノード側に接続されることを特徴とする半導体
の駆動回路。
[Scope of Claims] 1. In a semiconductor drive circuit that supplies a positive drive current to a semiconductor control @1 electrode at turn-on and a negative drive current at turn-off, the positive drive current is A semiconductor drive circuit, characterized in that a drive current of negative polarity is supplied from a main circuit, and the drive current of negative polarity is supplied from a main circuit. 2. A semiconductor drive circuit according to claim 1, wherein the negative drive current is supplied from a winding provided in a transformer that supplies power to a load. 3. In claim 2, the winding that supplies the negative drive current is connected to the semiconductor control electrode and one main electrode via a semiconductor switch and a first diode. Characteristic semiconductor drive circuit. 4. In claim 3, the positive polarity drive current is supplied from the drive circuit power source via a drive transformer, and the semiconductor switch is turned on by discharge of excitation current from the drive transformer. A semiconductor drive circuit characterized by being configured to perform the following functions. 5. In claim 4, the output winding of the drive transformer is connected at one end to a semiconductor control electrode and at the other end to one main electrode of the semiconductor through a second diode. A semiconductor drive circuit characterized in that the control electrode of the semiconductor switch is connected to the cathode side of the second diode, and the one main electrode is connected to the anode side.
JP56153634A 1981-09-30 1981-09-30 Driving circuit for semiconductor Granted JPS5856528A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP56153634A JPS5856528A (en) 1981-09-30 1981-09-30 Driving circuit for semiconductor
US06/424,369 US4499530A (en) 1981-09-30 1982-09-27 Switching power supply apparatus
EP82109012A EP0075947B1 (en) 1981-09-30 1982-09-29 Switching power supply apparatus
DE8282109012T DE3273040D1 (en) 1981-09-30 1982-09-29 Switching power supply apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56153634A JPS5856528A (en) 1981-09-30 1981-09-30 Driving circuit for semiconductor

Publications (2)

Publication Number Publication Date
JPS5856528A true JPS5856528A (en) 1983-04-04
JPH0226813B2 JPH0226813B2 (en) 1990-06-13

Family

ID=15566792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56153634A Granted JPS5856528A (en) 1981-09-30 1981-09-30 Driving circuit for semiconductor

Country Status (1)

Country Link
JP (1) JPS5856528A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6114213A (en) * 1984-06-30 1986-01-22 Yokohama Rubber Co Ltd:The Ultraviolet-curable resin composition
JPS6160764A (en) * 1984-09-03 1986-03-28 Dainichi Seika Kogyo Kk Coating composition for thin metallic film
JPS61187124U (en) * 1985-05-14 1986-11-21
JPS63272222A (en) * 1987-04-30 1988-11-09 Fanuc Ltd Pre-driving circuit
CN104202036A (en) * 2014-08-15 2014-12-10 广东易事特电源股份有限公司 Lossless thyristor driving circuit

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5081666A (en) * 1973-11-21 1975-07-02
JPS5228852A (en) * 1975-08-29 1977-03-04 Matsushita Electric Ind Co Ltd Power switching transistor drive circuit
JPS5235569A (en) * 1975-09-12 1977-03-18 Mitsubishi Electric Corp Semiconductor switch device
JPS5625828A (en) * 1979-06-01 1981-03-12 Gould Advance Ltd Semiconductor switching circuit
JPS56123123A (en) * 1980-03-04 1981-09-28 Nec Corp Switching circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5081666A (en) * 1973-11-21 1975-07-02
JPS5228852A (en) * 1975-08-29 1977-03-04 Matsushita Electric Ind Co Ltd Power switching transistor drive circuit
JPS5235569A (en) * 1975-09-12 1977-03-18 Mitsubishi Electric Corp Semiconductor switch device
JPS5625828A (en) * 1979-06-01 1981-03-12 Gould Advance Ltd Semiconductor switching circuit
JPS56123123A (en) * 1980-03-04 1981-09-28 Nec Corp Switching circuit

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6114213A (en) * 1984-06-30 1986-01-22 Yokohama Rubber Co Ltd:The Ultraviolet-curable resin composition
JPH0552328B2 (en) * 1984-06-30 1993-08-05 Yokohama Rubber Co Ltd
JPS6160764A (en) * 1984-09-03 1986-03-28 Dainichi Seika Kogyo Kk Coating composition for thin metallic film
JPH024605B2 (en) * 1984-09-03 1990-01-29 Dainichiseika Color Chem
JPS61187124U (en) * 1985-05-14 1986-11-21
JPS63272222A (en) * 1987-04-30 1988-11-09 Fanuc Ltd Pre-driving circuit
JPH055408B2 (en) * 1987-04-30 1993-01-22 Fanuc Ltd
CN104202036A (en) * 2014-08-15 2014-12-10 广东易事特电源股份有限公司 Lossless thyristor driving circuit
CN104202036B (en) * 2014-08-15 2017-07-18 广东易事特电源股份有限公司 lossless thyristor driving circuit

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