JPS5856323A - Manufacture of semiconductor substrate - Google Patents

Manufacture of semiconductor substrate

Info

Publication number
JPS5856323A
JPS5856323A JP15437881A JP15437881A JPS5856323A JP S5856323 A JPS5856323 A JP S5856323A JP 15437881 A JP15437881 A JP 15437881A JP 15437881 A JP15437881 A JP 15437881A JP S5856323 A JPS5856323 A JP S5856323A
Authority
JP
Japan
Prior art keywords
substrate
growth
epitaxial
sio2 film
single crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15437881A
Other languages
Japanese (ja)
Inventor
Yukinobu Tanno
丹野　幸悦
Nobuhiro Endo
遠藤　伸裕
Yukinori Kuroki
黒木　幸令
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15437881A priority Critical patent/JPS5856323A/en
Priority to US06/395,110 priority patent/US4637127A/en
Priority to DE19823225398 priority patent/DE3225398A1/en
Publication of JPS5856323A publication Critical patent/JPS5856323A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)

Abstract

PURPOSE:To form Si epitaxial layers having smooth surfaces and having favorable crystallinity selectively on a semiconductor substrate by a method wherein Si3N4 films are formed on the sides of an SiO2 film having an opening on the Si substrate, and depressurized epitaxial growth is performed using SiH2Cl2-H2. CONSTITUTION:After the SiO2 film 2 is accumulated on the Si single crystal substrate 1, fine processing is performed on the SiO2 film 2 thereof using the lithography technique and the dry etching technique. Then the Si3N4 films 6, 6' are accumulated on the side walls of the SiO2 film 2 formed with the opening according to processing mentioned above. Then depressurized epitaxial growth is performed using SiH2Cl2-H2 on the single crystal substrate 1 using the Si3N4 films 6, 6' thereof as the mask. Accordingly epitaxial layers 3 having the smooth surfaces and having favorable crystallinity can be formed selectively.

Description

【発明の詳細な説明】 本発明は絶縁＠餉域をもり単ｉｔｉ墨基碩上Ｋｌｔな高
品質のＳムエビタキシャル層をＪｌＳｌ沢的に成長によ
多形成する゛半導体基板の＃！遣方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to forming a high-quality S-layer with an insulating layer by growing it in large quantities on a semiconductor substrate. It is related to the method of sending.

通常、ＭＯＳデバイスにお＾て社Ｓムエビタ中シャル層
は用いられておらず、ｔｔ、＆板そのものにイオンイン
クラテーシ曹ン法や不純拡散法を用いて所望の伝導１１
（Ｐ型又はＮ１１）の層が形成され、それぞれ能動領域
１分離領域などが形成されている０分離領域形成の一方
法として部分酸化法（Ｌｏｃａｌ　０ｘｉｄａｔ　ｉｏ
ｎ　ｏｆ　８ｉ１ｉｃｏｎ　−・−Ｌ　Ｏ００８法）が
良く由いられてｂる。Normally, a MOS layer is not used in MOS devices, and the desired conduction 11 is achieved by using the ion increment method or impurity diffusion method on the tt, & board itself.
A partial oxidation method (Local Oxidatio
n of 8i1icon -・-LO008 method) is often used.

最近では、ｍＬｓｌデバイス指向の微細加工技術の研究
開発か進み、サブミクロンの加工がＵＶ篇元、越子ビー
ム、Ｘ＠等を用めたリング２フイ技術とドライエツチン
グ技術の進歩によ）容易にできるようになってｂる。し
かしながら部分酸化法を用いたＭＯＳデバイスでは、種
々の不都合が生じてきて＾る。すなわち微細加工技術が
先行し部分酸化法の制鉤技術が問題となりつつある。そ
れは基板を酸化する場合にはｂ”ｊＡ換をマスクとして
単結晶領域が熱酸化される。しかしその酸化されたＭ［
ｆｆｉは半楕円形となル所要の能動領域にはみ出し、又
隣接する能動領域との間隔も大きくなることとな）、デ
バイスの高密度化、高速化及び設計上も問題となる。Recently, research and development of microfabrication technology for mLsl devices has progressed, and submicron machining has become easier due to advancements in ring-2-fi technology and dry etching technology using UV beams, Etsuko beams, X@, etc. I am now able to do this. However, MOS devices using the partial oxidation method have various disadvantages. In other words, microfabrication technology has taken the lead, and partial oxidation technology is becoming a problem. When oxidizing the substrate, the single crystal region is thermally oxidized using the b''jA conversion as a mask.However, the oxidized M[
The ffi has a semi-elliptical shape and protrudes into the required active area, and the distance between adjacent active areas also increases), which poses problems in terms of higher density, higher speed, and design of the device.

他の問題としては、鍔えばＣ−ＭＯ８デバイスにおいて
１通常の基板を部分鍾化し分ｍ領域を形成し、それぞれ
ＰチャンネルとＮチャンネルトランジスタを形成した場
合に、デバイスの動作中に大きな外米雑音感圧が、入力
又は出力端子から内部回路に入ると％電源端子から接地
端子へ赦（ＨＡから数十ｍムもの１４常電流が流れる現
象（ラフ、チアラグ）が起る、等の問題がある。Another problem is that in a C-MO8 device, when a normal substrate is partially plated to form m regions and P-channel and N-channel transistors are formed respectively, a large amount of external noise occurs during device operation. If pressure sensing enters the internal circuit from the input or output terminal, there are problems such as a phenomenon (rough, cheer lag) in which a normal current of several tens of mm flows from the HA to the ground terminal. .

以上のように従来技術でのＭＬ）８デバイス構造では高
ｖｌｉ寂化への障害があＩＩ、このことＬ寄生容量を増
大させ、デバイスＯａ速化の障害と１なる。As described above, in the conventional ML)8 device structure, there is an obstacle to high vli, which increases the L parasitic capacitance and becomes an obstacle to increasing the device Oa speed.

さらに先に述べたように構造上＾當電流が處れる等の欠
点を有して−る。Furthermore, as mentioned earlier, it has structural disadvantages such as the electric current being damaged.

本発面の目的は半導体基板その鳴のＫｌ！ａｌｌｉｉ＠
域を形成することなく、絶縁Ｊｉｇ（ｆ８ｊ鳩又は８ム
洩）をマスクとして％旧エビメキシャル成長層を選択的
に半導体基板上に形成し、従来接輪０欠点をおぎないデ
バイスＩ？＃性の向上をねらおうとすゐものである。The purpose of this discovery is the sound of semiconductor substrates! allii@
By selectively forming an old evimexial growth layer on a semiconductor substrate using an insulating Jig (F8J dove or 8M leak) as a mask without forming an area, a device I? ＃It is something that aims to improve sexuality.

その構成要件としては８１単結晶基１１に杷鑞纒を形成
し、リングラフィ技術とドライエツチング技ｍｔ−用い
サブミクロンの微細加工を施す。この基板を減圧エピタ
キシャル成長炉にセットし、１９ｊ鳩Ｃｌ　、−１〜系
を用ｉ減圧下で成長し、半導体基板上又は絶縁基板上に
もわた９選択的に単結晶膜を形成しようとするものであ
る。Its constituent elements include forming a loquat on the 81 single crystal base 11, and subjecting it to submicron microfabrication using phosphorography technology and dry etching technology mt-. This substrate is set in a reduced pressure epitaxial growth furnace, and 19j Cl, -1~ system is grown under reduced pressure to selectively form a single crystal film over a semiconductor substrate or an insulating substrate. It is.

ｂｔｕ晶の選択成長技術の公知列としては１）ジャーナ
ル・オブ・エレクトロケミカル　ンサイテ４　（Ｊ−ｈ
ｌｅｃｔｒｏｃｈｅｍ−８ｏｃ−、ＶｏＬ、１２０．Ｍ
Ｌ５　、Ｐ−６６４゜１９７３）及び２）ジャーナル・
オプ・エレクトロケミカル　ソサイテ４　（Ｊ伊ｋｌｅ
ｃｔｒｏｃｈａｎ−８ａｃ−。Publicly known columns on selective growth techniques for btu crystals include 1) Journal of Electrochemical Research 4 (J-h
lectrochem-8oc-, VoL, 120. M
L5, P-664゜1973) and 2) Journal
Op Electrochemical Society 4 (JIkle
ctrochan-8ac-.

ＶＯＬ、１２２．醜１２．ｌ’−１６６６，１９７５）
があ）、杓σ者では５ｉｌ１４−）ＩＣＩ−）１．系に
！　Ｄ　Ｉ　１５０℃テＢｔｕｓ　＠４ｆ　マスクとし
て、別基板の（１１１）、（１１０）、（１１５）と（
１００）面ｔ−選び成長したとζろ、エピタキシャル表
面の平滑性は（−１１０）面が最も艮＜ｓ　　（１１ｔ
）血と（１１５）面を用いた場合Ｋｌま良くなり０さら
に（１１５）面ｔ−用いた場合のエピタキシャル層では
下地パターンとエピタキシャル層のパターンがずれるパ
ターン変形が大きく、問題でおることが記載されている
。後者では基板に巾１０〜２０＾ｍで深さが〜１１００
ａの溝を形成し、基板上に何ら絶縁膜を形成することな
しに％溝部だけに選択的に８１単結晶を棚込み成長しよ
うとするもので、Ｓｉソー　ス（！：　Ｌ　テ８ｉ　Ｋ
　、８ｉＨＣ１ｓ　、５ｉＨ１ｃｌ、　ト８　ｉ　Ｃ１
４Ｋ加えて１（Ｃｌガスを導入して行うものである。選
択成長のポイントはＣ３／８ｉの滴縦比が重曹であるこ
とが記載されてｂる。又８ｉにｃｌ、　−）１Ｑ　１−
Ｈ，系では基板方位ｔ”　（１１０）面に選び１０８０
℃で試みたが、平滑な表面が得られなりことが述べであ
る。VOL, 122. Ugly 12. l'-1666, 1975)
Yes), 5il14-)ICI-)1. To the system! D I 150℃Te Btus @4f As a mask, (111), (110), (115) and (
When grown selectively on the 100) plane t-plane, the smoothness of the epitaxial surface is the highest on the (-110) plane.
) It is stated that when the (115) plane is used, the Kl is better. Furthermore, when the (115) plane is used, the epitaxial layer has a large pattern deformation in which the underlying pattern and the pattern of the epitaxial layer are misaligned, which is a problem. has been done. In the latter case, the substrate has a width of 10 to 20 m and a depth of ~1100 m.
This method aims to form a groove of 81 and selectively grow the 81 single crystal only in the groove without forming any insulating film on the substrate.
, 8iHC1s, 5iH1cl, 8 i C1
4K plus 1 (This is done by introducing Cl gas. It is stated that the point of selective growth is that the droplet aspect ratio of C3/8i is baking soda.Also, 8i has Cl, -) 1Q 1-
In the H, system, the substrate orientation is t” (110), and 1080
Although I tried it at ℃, I was unable to obtain a smooth surface.

又ＢｉａＮ、Ｉ！をマスクとした選択的な８１エビタキ
クヤル成長技術の公知ガとして３）ザ・エレクトロケミ
カル・ノサイティ・ホールミーティング。BiaN, I! 3) The Electrochemical Nocy Hall Meeting as a known method of selective 81 Ettakikuyaru growth technology using a mask.

１０月、１９６９．アブストラクト８１１８１．４７６
頁（Ｔ、ｈｅ　Ｅｌ　ｅｃｔｒｏｃｈｅｍ＠８ｏｃ−に
’ａ１　トＭｅｅｔ　ｉｎｇ、Ｏｃｔ　。October, 1969. Abstract 81181.476
Page (T, he El electrochem @ 8oc-Meeting, Oct.

１９６９、ムｂｓ、ＭＬ１８１．Ｐ−４７６）ｂ　４）
ジャバフ−ジャーナル・アプライド・フイズイクス・ポ
リ、ラム１０，１９フ１年、　１６７５頁（Ｊａｐａｎ
−Ｊ、Ａｐｐｌ。1969, MUBS, ML181. P-476) b 4)
Javaf-Journal Applied Physics Poly, Ram 10, 19f 1, p. 1675 (Japan
-J, Appl.

Ｐｈｙ　ｓ　−１０（１９７１）　ｅ　ＰＩ３７５　）
とあるが、　Ｓｊ単結晶基板上に加工された８ｉｓべ展
は熱的、化学的に強いが、ｌ：ｌｉ、Ｎ、自体が真性応
力をもつために熱グｎセスを経れば８！基板又は選択８
ｉエピタキシヤル領域に、Ｈえば転位等の結晶欠陥を導
入し易いことはよく知られて−るところである。Phys-10 (1971) e PI375)
However, the 8is base fabricated on the Sj single crystal substrate is thermally and chemically strong, but since l:li and N themselves have intrinsic stress, if they undergo thermal stress, they will become 8! Substrate or selection 8
It is well known that crystal defects such as dislocations are easily introduced into the i-epitaxial region.

又Ｓ＆基板上には通常Ｓ１嶋−と８ｉ、Ｎ、験の二層構
造が用いられておプ、歪補償を行う厚さが１）９欠陥が
発生しな一工夫もされてｂる。In addition, a two-layer structure of S1, N, and N is usually used on the S& substrate, and the thickness for strain compensation has been devised to prevent the occurrence of defects.

以上のように８ｉ結晶の選択区長の公知例では（１１１
）面を用いても結晶表面の千′Ｐ＃直が悪く。As mentioned above, in the known example of the selection section length of 8i crystal (111
) plane, the crystal surface has poor alignment.

８１鳩Ｃｌ、−）ＩＣＩ−鶴系を用ｉても結晶性が良く
ない等の問題かある。又絶縁膜として＊　Ｓｉｎ′Ｎ４
−のみを用いると、熱プロセスで結晶欠陥を導入し易い
等の不利な点がある。Even if 81 HatoCl, -) ICI-Tsuru series is used, there are problems such as poor crystallinity. Also, as an insulating film *Sin'N4
If only - is used, there are disadvantages such as easy introduction of crystal defects during thermal process.

本発明で社従来の選択成長技術の不備な点を改良できる
もので、そのキーポイントはｂｉ基板上の開口したＳ　
ｉ　（Ｊ＊　１１Ｍ面に８４．Ｎ、を形成し、　８ｉ）
４ＣＩ冨−に系で、減圧下で選択成長を行うことである
。The present invention can improve the deficiencies of the conventional selective growth technology, and the key point is that the open S
i (84.N is formed on the J* 11M plane, 8i)
Selective growth is carried out under reduced pressure in a 4CI-rich system.

減圧下で８１エビ！キシヤル成長を行うとその表面が平
滑になる理由社、減圧エビタキ７ヤル法の特徴である／
’メタン形が起らない仁とと関連し成長のメカニズムが
異なるものと考えられる。しかし明確な理由は今のとこ
ろ分ってｈない。81 shrimp under reduced pressure! The reason why the surface becomes smooth when the surface is grown
'It is thought that the growth mechanism is different from that of kernels in which methane formation does not occur. However, the exact reason is not known at this time.

次に本発明を説明するための実ｍガについて述べる。Next, a real model will be described for explaining the present invention.

実施同一１ ３＃φの８ｉ基板の面方位がガえは（１１１）面を迦び
％８ｉ０．ｌ［を〜５０００Ａ堆積し、リングラフィ技
術とドライエツチング技術を用いて、その線巾をα５〜
３．０μｍとなる微細加工を施す、これらの基板をシリ
ンダ薯エピタキシャル成長炉にセットする。Same implementation 1 The plane orientation of the 8i substrate with 3#φ is (111) plane and %8i0. Deposit ~5000A of l[, and use phosphorography and dry etching techniques to increase the line width to α5~
These substrates, which are microfabricated to 3.0 μm, are set in a cylinder epitaxial growth furnace.

基板温度を〜１２０Ｇ℃としプレベーキングを１５分行
う、さらに基板温度を１０８０℃として、ｌも〜１、０
０１７分、　８ｉ）４１０１　＠　：　５００　ｃ　ｃ
／分、成長圧カニ８０’ｉ”ｏ　ｒ　ｒの条件で２．０
分成長すると〜１．０μｍの８１結晶−が成長する。The substrate temperature was set to ~120G°C, pre-baking was performed for 15 minutes, and the substrate temperature was set to 1080°C, and l was also ~1,0.
017 minutes, 8i) 4101 @: 500 cc
/min, growth pressure crab 2.0 under the condition of 80'i"o r r
81 crystals of ~1.0 μm grow.

Ｒｒｆｉ状態は金属干渉顕微鏡（ノマルスキー）でその
断面は走査ｍａｔ子顕微＠（８ＥＭ）で観証できる。こ
の場合のＪエピタキシャル成長ｌＴｈ０ｌ膚面の模式図
をａＫ１因に示す。The Rrfi state can be observed using a metal interference microscope (Nomarski), and its cross section can be observed using a scanning matron microscope @ (8EM). A schematic diagram of the J epitaxial growth lTh0l skin surface in this case is shown in aK1.

８ｉ＊結晶基板１、ｋ絶縁ｉ１２を形成し、この上に３
の８ｉ映が形成される。高温成長のため、溝底部の３ｉ
ｑ−側面がＳｉ結晶に食われていることが分った。これ
は８ｉ０，１１１１が＃細なため、熱プロセスを経るに
つれ、映が剥離する等のデバイス作製上間亀となる。こ
れｔ−縞１図の４，４′に示す。8i*crystal substrate 1, k insulation i12 are formed, and 3
An 8i image is formed. 3i at the bottom of the groove due to high temperature growth.
It was found that the q-side was eaten by the Si crystal. This is because 8i0 and 1111 are thin, so as the film undergoes a thermal process, the film peels off, resulting in problems during device fabrication. This is shown at 4 and 4' in Figure 1 of the t-stripe.

実施ガー２ ３″−のδｉ暴板の面方位が囲えば（１１１）面を選び
ｈ　　”！ＬＪｔｌｌ１４ｔ〜５０００Ａ堆積し、リン
グラフィ技術とドライエツチング技術を用いてその線巾
をα５〜３．０μｍとなる微細加工を施す、さらに開口
された！ｉｉＣＪｍ　ＩｉｌｌｉＯｌｉｌｌｍＫ　８ｉ
ｓＮａ　’ＩＩＩｋｔｊ４１ｉｄｋｆｂ１ｍ下ｔｄ実施
内−１と同じ条件１０８０℃、ＢＱＴｏｒｒ、２．０分
成長で１．０ｔｔｒｎ　ｃＤ　８ｉ結晶映が成長する。If the plane orientation of the δi plate of Implementation Gar 2 3″- is enclosed, select the (111) plane and h ”! LJtll14t ~ 5000A was deposited, and microfabricated using phosphorography technology and dry etching technology to make the line width α5 ~ 3.0 μm, and further opened! iiCJm IilliOlillmK 8i
A 1.0ttrn cD 8i crystal was grown under the same conditions as sNa 'IIIktj41idkfb1m lower td implementation-1 at 1080°C, BQTorr, and 2.0 minutes of growth.

８１工ピタキシヤル成長層の表面状態は金属干渉顕微−
で、その断面は走査型−子顕微鏡で観察できる。この場
合のＳｉエピタキシャル成長層の断面の模式図ｔＭ２図
に示す。The surface condition of the 81st pitaxial growth layer was observed using a metal interference microscope.
Its cross section can be observed using a scanning microscope. A schematic cross-sectional view of the Si epitaxial growth layer in this case is shown in Figure tM2.

８轟θ黛ｗ面に熱的に強い８ｉｓＮａｌｌ１４があるた
めに１１１図に見られるような８ｉ結晶にＳｉ（％眼が
食われる現象は見られず、溝部の形状はエピタキシャル
成長前と変らず、シャープであった。Because there is a thermally strong 8isNall14 on the 8i crystal on the 8i crystal, as seen in Figure 111, the phenomenon of Si(%) being eaten away is not observed, and the shape of the groove remains unchanged and sharp as before epitaxial growth. Met.

絽２図の１は８ｉ単結晶基板、　２Ｆｉ別Ｏ雪瞑、３は
エピタキシャル膜で、５．５’は８４０＊ｌＫ上の岨エ
ピタキシャル層で、６はｓｉ、Ｎ、験である。In Fig. 2, 1 is an 8i single crystal substrate, 2 is an epitaxial film, 3 is an epitaxial film, 5.5' is an epitaxial layer on 840*1K, and 6 is a Si, N, and E.

以上のように８１基板の面方位を岡えば（１１１）に・
選び、４碁板上の開口した８ｉへｍ側面を８１゜Ｎａ　
ｍで保藤しｂ１鵬Ｃ５，−鳩系を用い減圧下で成長を行
えば、その表面が平滑で良好な結晶性を有する選択８１
工ピタキシヤル層が形成てきるものである。As mentioned above, if the plane orientation of the 81 substrate is changed, it becomes (111).
Select and move the m side to the open 8i on the 4 Go board at 81°Na.
If growth is performed under reduced pressure using Yato and B1PengC5, - Hato systems, the surface will be smooth and have good crystallinity.81
This is due to the formation of a pitaxial layer.

本発明の夾總−による第２図の５．５′のようＫｌｌ！
！縁基板上にも成長することは、この領域にソース、ド
レインを形成することができ％異常＊ａの発生（ラッチ
アップをも防止できる。又部分に化法による一密夏化の
不利な点をカバーし、シャープなジャンクシ璽ン形成が
できるため、高田度で、４速なＭ（ＪＳ又はＣ−ＭＵ８
デバイスを形成できるものである。さらにこの選択成長
技術の利点としては、多層配線のためのコンタクトネー
ルの埋込み成長技術としても応用でき、配線の平滑化を
可能ならしめデバイスの信頼性を向上させることもでき
る０本発明ではＭＯ８デノ（イスにつ匹テ述べたが、パ
イボーラデノ（イスにも応用できることは−うまでもな
い。According to the combination of the present invention, as shown in 5.5' in FIG. 2, Kll!
! By growing on the edge substrate, the source and drain can be formed in this region, and the occurrence of % abnormality *a (latch-up) can also be prevented.Also, there is a disadvantage of dense summerization due to the partial chemical method. , and can form a sharp junction.
A device can be formed. Furthermore, the advantage of this selective growth technique is that it can be applied as a buried growth technique for contact nails for multilayer wiring, and it can also smooth the wiring and improve device reliability. I mentioned this about chairs, but it goes without saying that it can also be applied to chairs.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は減圧エピタキシャル法で８ＬＯ＠＠をマスクと
して成長した場合の成長層断層の模式図。 謳２図は本発明によるｆｉＩ＆面方位ｔ−（１１１）面
とじ８１ヘ−の開口部−面を５ｉａｊ’％　ｋで保験し
減圧下でエピタキシャル成長した場合の成長階断面の模
式図。 １・・・８１本結晶基板 ２・・、８ｉ（Ｊ、瞑 ３・・・Ｓｉエピタキシャル成長層 ４．４′・・・８ｉＯ１−の侵蝕部 ５．５′−・絶縁膜上の８１工ピタキシヤル層６．６′
・−５ｉｓべ暎FIG. 1 is a schematic diagram of the tomography of a grown layer when grown by the reduced pressure epitaxial method using 8LO@@ as a mask. Figure 2 is a schematic diagram of a growth step cross section when epitaxial growth is performed under reduced pressure while maintaining the fiI & plane orientation t-(111) plane binding 81 plane at 5iaj'% k according to the present invention. 1...81 crystal substrate 2..., 8i (J, medi 3...Si epitaxial growth layer 4.4'...8iO1- erosion part 5.5'--81 crystal epitaxial layer on insulating film 6.6′
・-5isbeyo

Claims (1)

【特許請求の範囲】[Claims] ｆ９ｉ単結晶基板上に微細構造をもつＳｉへ瞑を形成し
、且つ開口された８ｉ０．＠の側壁に組−４［を堆積し
この膜をマスクとして単結晶基板上に別）ｉＩＣｌ、ン
ースを用い、減圧下でその成長圧力が２０〜２００Ｔｏ
ｒｒの範囲で成長することを特徴とする８ム単結晶−の
選択成長によシ形成することを特徴とする半導体基板の
製造方法。An 8i0. Deposit Group-4 on the sidewalls of @, and use this film as a mask on a single crystal substrate.
1. A method for manufacturing a semiconductor substrate, characterized in that the semiconductor substrate is formed by selective growth of an 8-μm single crystal, which is characterized by growth in the range of rr.
JP15437881A 1981-07-07 1981-09-29 Manufacture of semiconductor substrate Pending JPS5856323A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP15437881A JPS5856323A (en) 1981-09-29 1981-09-29 Manufacture of semiconductor substrate
US06/395,110 US4637127A (en) 1981-07-07 1982-07-06 Method for manufacturing a semiconductor device
DE19823225398 DE3225398A1 (en) 1981-07-07 1982-07-07 SEMICONDUCTOR DEVICE AND METHOD FOR THEIR PRODUCTION

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15437881A JPS5856323A (en) 1981-09-29 1981-09-29 Manufacture of semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS5856323A true JPS5856323A (en) 1983-04-04

Family

ID=15582837

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15437881A Pending JPS5856323A (en) 1981-07-07 1981-09-29 Manufacture of semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS5856323A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6318668A (en) * 1986-07-11 1988-01-26 Canon Inc Photoelectric transducer device
JPS6376367A (en) * 1986-09-18 1988-04-06 Canon Inc Photoelectric conversion device
JPS63133615A (en) * 1986-11-26 1988-06-06 Fujitsu Ltd Vapor growth method
JPH01189914A (en) * 1988-01-25 1989-07-31 Sony Corp Manufacture of semiconductor device
US6503799B2 (en) * 2001-03-08 2003-01-07 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6318668A (en) * 1986-07-11 1988-01-26 Canon Inc Photoelectric transducer device
JPS6376367A (en) * 1986-09-18 1988-04-06 Canon Inc Photoelectric conversion device
JPS63133615A (en) * 1986-11-26 1988-06-06 Fujitsu Ltd Vapor growth method
JPH01189914A (en) * 1988-01-25 1989-07-31 Sony Corp Manufacture of semiconductor device
US6503799B2 (en) * 2001-03-08 2003-01-07 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device

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