JPS5856037A - Central processing unit for microprogram control - Google Patents

Abstract

PURPOSE:To access a microprogram memory smoothly by performing two-cycle operation successively through hardware without generating a deliberate microprogram. CONSTITUTION:Registers RG-A and RG-B are connected to an arithmetic logical circuit and also connected to a main storage MS. Further, a memory address register MSAD, a register LG stored with the length of an operand, and a register ACD for indicating a direction of access are connected to the access control circuit MAC of the main storage. Then, the registers MSAD, LG, and ACD are set by a micro-instruction, so it is evident that the main storage MS crosses a boundary BD. Consequently, a CPU is controlled by signals EX1T and EX2T, obtained by a decoder DEC, through the circuit MAC, so even if a microprogram attains access crossing the boundary, a programmer writes the program smoothly without being aware of that.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention extends K fllJ so that central processing oil can be accessed without spanning the boundaries of main memory.
In the case of centrally processed oil controlled by the micro program of the dull rice, the micro program should be checked once and the two-cycle operation "Ik: 41L" is set, then the micro program branches and operates. It was necessary to return to V11.Therefore, it was necessary to erase the original program by two cycles, and the number of steps increased.The number of memory records in control memory increased from K. Key - The performance of mackerel loading has decreased.

One advantage of the present invention is that when it is necessary to perform two-cycle operation, microblocks can be used with a dosed 5vVT.
The purpose of this invention is to provide a central system that enables two-cycle m-order operations using hardware.Example 1 of the X3# shown in the drawings will be described below. In the diagram shown in Figure 1, RG-mu, R()-B are each register, LU)i is arithmetic logic circuit, MS is main memory,
08 is a control memory, M8D is a memory address register, LG is a register that stores the length of the operand, and MOD is a register that stores the length of the operand.
Is there 10,000 access? 84 is the T register, M0 is the main memory access III control path, DKO is the decoder L,
As shown in Figure 2, it is obvious that the master's yearning for the T-boundary BDKI is B! 2.Address register M8
Since AD, register LG, and MUCD are set, it becomes clear at that time. In addition, the decoder DWOjf is decoded and created by the samurai through the decoder DWOjf (decoded and created by the samurai). becomes.

In the case of Yo 11 King memory gauze, from Micro Order IK (M8) →
Data transfer [Micro order 2] This combination [Micro order 2] This is an order that is executed in the lth cycle (hereinafter abbreviated as lτ).

'IIFJ3 Aku ni Ho T Yoni 1τth [From Micro Order IK] M8 Totame and S-byte Cheetham Oe A 1 em 2 are register RG-M [
-Press e.

1rl (by micro order 2) The contents of register /RG-A are moved to register RG-B.

2τiJ (from Micro Order IK) Micro Memory M
From 8, 6-byte datums 3 to A7 are registers! ? It is set to GM.

(21 Memo V writing) As shown in Figure 1, (4) → M8 (Contents of register RG-M
K convolution) Memory write [micro order 1) (B) → M (inner boundary of register RG-B)
Data Transfer [Micro Order 2] In this case, [Micro Order 2] is the order that is fired at 2rl.

1τth 3 bytes of data from register RG-m are stored in memory 8 [according to 71st order IK] 2nd τ 6 bytes from register PG-m) (/J f
- data is stored in memory MBK [according to micro-order IK]. The contents of register RG-B are moved to register RG-me [according to micro-order IIK]. Thus, according to the present invention, the microprogram straddles the boundary. Even if you do not want to access 8ゎ,
The program creator can create and maintain the program without any intention, and the IJIU hardware allows smooth access to the microprogram memory.

41 Blood in the stirrup No. 1 indicates the perseverance of the embodiment of the present invention, the second cause is the main 1
Explanation of - 1 Accessed by Zhu 3-in and 4-th drawing book - Shows 1 share in T.

RG-M, RQ-B...Resistum LU...Sensitive thoracic circuit M8...Main memory C8
...Control memory "DEC-decoder material delivery person Fuji trace a: Nisosha agent attorney person Patent attorney Eisuke Suzuki 2nd time 71 KI! Ko Prisoner's mouth == situation Figure 3 MS RG- A RG-8 4th
figure

Claims (1)

[Claims] In a microprogram-controlled central processing unit, when an access is made across the boundary of main memory, the microprocessor's manually operated decoder performs the first cycle in the first cycle. T
The micro-orders are divided into the micro-orders that will be fired in the second cycle and the micro-orders that will be fired in the second cycle, and one π control 4fi number will be lost, and the central processing unit will be set as a % sign to access the main 100 million by the control signal. Microprogram Ilj+H@l
(7J central processing unit.