JPS5854418B2 - data processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device, and more particularly to a reset circuit in a data processing device.

In a data processing device using a microprocessor,
While a certain processing program is being executed, it may be necessary to interrupt it and execute another routine, and in order to execute this, the NMi signal is input to the microprocessor.

This NMi is a non-masked
k-interrupt), and is used to interrupt the processing unit even if data processing is in progress, for example, when a parity error occurs, when the power is turned on, when a reset button is operated, etc.

In this case, the data related to the interrupted program is temporarily put on standby, and after the other routines are finished executing, the RTi
The (return included) instruction performs an operation to return to the original program.

For this reason, the microprocessor has a built-in stack pointer (sp), which stores the address information of the stack (consisting of RAM) that stores the data during the period at the same time as NMi occurs.

Note that the program from NMi generation to RTi generation is written in a ROM in a memory containing a memorization stack, and is executed by an LDS (load S) instruction.

On the other hand, when a reset start is applied to the microprocessor, the NMi generating circuit and other external circuits are usually released from reset at about the same time.

In other words, if the microprocessor is the processing unit, NM
The processed section including the i generation circuit and other external circuits is reset and released at approximately the same timing as the processing section is reset (program started).

However, when the reset was canceled, the processing unit started up and the LD
When executing the S instruction, if the NMi signal is generated from the processed part that has already been reset, the program based on the NMi instruction cannot be executed, and even if you try to return using the RTi instruction, the stack pointer will not return normally. The address is not stored and the processing section ends up going out of control.

In order to prevent this kind of runaway, conventionally, if the return address is not properly stored in the stack pointer, the RT
The method used was to cancel the i command and leave it in that state.

However, such a method cannot be said to be a preferable method for achieving highly efficient use of a microprocessor system.

Therefore, an object of the present invention is to propose a data processing device that can prevent the above-mentioned runaway with an extremely simple configuration.

In accordance with the above-mentioned object, the present invention provides a time difference between the reset release of the processing unit and the processed unit, and after the reset release of the processing unit and the completion of the reset start execution of the processing unit and the execution of the LDS instruction have elapsed, the above-mentioned The present invention is characterized in that the reset of the processing target section is canceled.

The present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a data processing device to which the present invention is applied.

In this figure, 11 is a processing unit (microprocessor);
2 is a memory section, and 13 is a processed section to be controlled by the processing section 11.

These components are activated by release of the reset signal.

Now, suppose that an NMi request is generated in the processed section 13 due to power-on, reset button operation, occurrence of a parity error, etc., then the NMi generation circuit 14 in the processed section 13 responds to this request. and connect the NMi signal to signal line 15.
The data is transferred to the processing unit 11 via.

Upon receiving this NMi signal, the processing unit 11 executes the LDS command.

This LDS instruction is an instruction to secure the address information of the stack for timing the data related to the program interrupted by NMi, so that after the execution of the routine based on NMi is finished, the execution of the original program is restarted by the RTi instruction. can be started.

Therefore, only when this LDS instruction is executed normally will NMi
can be effectively executed and prevent the data processing device from running out of control.

That is, receiving the NMi signal and executing the LDS command,
The storage location of data related to the interrupted program is specified in the stack area 16 in the memory unit 12.

The stack area 16 is comprised of a RAM and stacks data related to the interrupted program from a designated address.

After the routine N M i is executed, the process returns to the specified address, so this specified address is stored in the stack pointer 17 (SP) by this LDS instruction.

The program that should execute this LDS instruction is the memory section 1.
The program area is written in a program area 18 in the internal memory 2, and the program area consists of a ROM.

Further, in the program area 18, execution programs based on NMi are written.

Note that 19 in the processing unit 11 is a program counter (PC) for executing a program of LDS instructions.

In the data processing device described above, the NM of the processed section 14 is
Even though the NMi signal is normally sent out from the i generating circuit 14, the RTi command generated after the program is executed by the NMi may not be executed normally and a runaway may occur.

This problem is particularly noticeable at the time of reset.

At the time of reset, the reset start operation of the post-reset release processing unit 11 is executed, the contents of the program counter are determined, and the LDS instruction is subsequently executed. However, if the NMi signal has already been sent during this period, the If an NMi is received at the time, and the program is subsequently executed using the NMi and the program attempts to return to the original program, the stack pointer 1γ will not have a return address set and the program will run out of control.

Therefore, in the present invention, the reset is canceled using the time chart shown in FIG.

L2, 3, 4, 5 and 6 in FIG. 2 indicate the clock pulse (φ2) and the first reset signal (φ2) of the data processing device, respectively.
R8T 1), reset start (R8T'), LDS
command, the second reset signal (R8T2) and the NMi signal, particularly the first and second reset signals (R8T1.
R8T2) is a characteristic part according to the present invention.

The first reset signal (R8TI) originally means reset release, and in the present invention is applied only to the processing section (11 in FIG. 1).

In addition, the second reset signal (R8T2)
It is applied only to 13) in the figure.

To explain with reference to FIG. 1, first, when the reset is released in synchronization with the clock pulse (φ2), the processing section 11 is released from the reset by the first reset signal (R8T1), and the reset starts (R8T'). is executed.

Subsequently, the LDS instruction is also executed. When these executions are sufficiently completed, a second reset signal (R8T2) is outputted to release the reset of the processed section 13.

After that, the NMi generation circuit 14 sends the NMi signal to the processing section 11 for the first time.

As is clear from the time charts of FIGS.
Since this is done after the execution of the instruction is completed, when the program by NMi is executed and the RTi instruction returns to the original program, the return address is definitely set in the stack pointer, and runaway is unlikely.

In order to implement the time chart shown in FIG. 2, an extremely simple configuration change is required on the hardware.

For example, the configuration shown in FIG. 3 is used. However, FIG. 3 is a block diagram showing only the parts related to the present invention. In this diagram, numeral 31 is a shift register, and a clock terminal 32 (CL) is connected to the clock pulse (φ2) of FIG.
is applied, and the first reset signal (R8T1) shown in FIG. 2 is applied to the set terminal 33.

QA, QB, Qc, QD, QE, QF, QG and QH
is an output terminal, from which signals whose phases are sequentially shifted are obtained.

Among these, a signal having a desired amount of phase shift is obtained from the output terminal 34 (QH) and is used as the second reset signal (R8T2).

This shift register 31 will be placed at a position indicated by a dotted line 31 in FIG.

As explained above, according to the present invention, it is possible to prevent runaway caused by NMi processing at the time of reset, which has been a problem in the past, and moreover, without reducing the usage efficiency of the data processing device, and with a simple design. With this configuration, the runaway can be reliably prevented.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of a data processing device to which the present invention is applied, and FIG. A time chart showing the state, FIG. 3 is a diagram showing an example of elements to be newly added to implement the present invention. In this figure, 11 is a processing section, 12 is a memory section, 13 is a processed section, 14 is an NMi generation circuit, 16 is a stack area,
1T is a stack pointer, 18 is a stack area, 19 is a program counter, 31 is a shift register, R8T1
and R8T2 are first and second reset signals, respectively.

Claims (1)

[Claims] 1. A processing section, a processed section controlled by the processing section,
It has a memory section that stores programs and data necessary for data processing between the processing section and the processed section, and the memory section includes at least a stack area for waiting data related to the interrupted data processing, and a stack area for waiting data related to the interrupted data processing. The processing unit has a program area for storing a program for executing an operation for the processing, and the processing unit is related to a stack pointer for storing an address in the stack area of the timed data and an operation for waiting for the stack pointer. A data processing device having a program counter for executing a program, characterized in that the data processing device is provided with a delay means for stopping activation of the processing target section at least until the address is stored in the stack pointer. 2. The delay means is a shift register, a first reset signal for activating the processing section is applied to the set input of the shift register, and a second reset signal given a predetermined phase shift is sent from the output thereof, 2. The data processing apparatus according to claim 1, wherein the second reset signal is used to start the processing section.