JPS5853347B2 - Denshigatsukinokenshingosentaxouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention distributes a plurality of key press signals sent as encoded digital signals to at least one prepared sound source circuit, and calculates the frequency corresponding to the pressed key. The present invention relates to a key signal selection device for an electronic musical instrument for obtaining musical tone signals.

In conventional electronic musical instruments, sound sources corresponding to the number of keys are prepared for each key, and the sound source corresponding to the pressed key is extracted by opening and closing a key switch linked to the playing operation of the keyboard, or It is common to prepare sound sources that generate the highest pitches for one octave, and divide the frequency of these by seven to obtain a sound source corresponding to each key.

Therefore, there is a drawback that the number of sound sources and the number of frequency dividers becomes very large, making the device itself very complicated.

The present invention has been made in order to eliminate the drawbacks of the conventional methods described above.The present invention prepares at least as many sound sources as required, and distributes key signals corresponding to the pressed keys to the sound sources. It is an object of the present invention to provide a key signal selection circuit for an electronic musical instrument, which obtains a musical tone signal of a frequency corresponding to a selected key.

The present invention will be described in detail above with reference to the accompanying drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

The key signal generator 1 encodes a key press signal corresponding to a pressed key (hereinafter referred to as key-on data) and a key release signal corresponding to a released key (hereinafter referred to as key-off data). A specific example circuit is shown in FIG. 2, which will be described later, and will be described in detail.

The key-on data sent out from the key signal generator 1 is sent to N sound source circuits 6, which are prepared in advance. ．． 6.・・・・・・
・Channel 1 and 2 corresponding to 6
... is guided to the first channel 1 of N.

This channel 1 has a memory circuit 3I that temporarily stores key-on data, and when this memory circuit 3I has already stored key-on data (that is, when it has content), it stores the key-on data. and a gate circuit 2° that stores the key-on data in its memory circuit 3I when the key-on data is not stored yet (that is, when there is no content). , a logic gate circuit 5 that sends key-on data to the next channel 2 only when the storage circuit 31 has content. , the memory contents of the memory circuit 3, and the key-off signal sent from the key signal generator 1.
A match signal is generated only when the data matches, and this match signal is used to generate the match signal from the memory circuit 3. It is composed of a matching circuit 41 that clears the memory contents of.

Channels 2...N have a similar configuration.

Therefore, when a key-on data is sent from the key signal generator 1 by pressing the duplicate key, the key-on data will be sent to channel 1, channel 2, etc. sequentially, and will automatically be sent to the channel 2 without any content. If there is a memory circuit 3 of a channel with no content, it will be stored in the empty memory circuit 3 via the gate circuit 2 of that channel, and the search will be stopped after that. .

If all channels 1, 2...N storage circuits 3. ．． 32...When 3N has content, the key-on data is given to the key signal generator 1 as overflow data from the logic gate circuit 5N of channel N, and one of the memory circuits 3 has the content. Key on until nothing
Continue sending data.

When you release the key you were pressing next, the key-off data sent from key signal generator 1 will be sent to all channels 1,
2...N matching circuits 4. ．． 42...4
N, the contents of the memory circuit 3 that match this key-off data are cleared, and the memory circuit 3 becomes empty again.

Each channel 2...N memory circuit 3.・
The key-on data stored in 32...3N is transmitted to the corresponding sound source circuit 6.32. , 62...
Sent to 6N.

These sound source circuits 6□62...6N send out musical tone signals of frequencies corresponding to the input key-on data to the output terminals 1, 2...N.

FIGS. 2 and 3 are circuit diagrams of a more specific embodiment of the above-mentioned FIG.
This is an example circuit assuming that 7.

FIG. 2 shows a specific example of the key signal generator 1, in which a 62-decimal counter 12 driven by the clock signal of the clock generator momentarily converts the count signal into key-on data.
Gate circuit 15 and key-off data gate circuit 1
Send on 6.

On the other hand, key switches S, S2 that are linked to the playing operation of each key
. . . 861 are commonly connected to the voltage supply terminal EV, and the other ends are connected to the key switches S1. S2...Connected to the first shift register in which SaS opening/closing information is written in parallel.

That is, in the embodiment of FIG. 2, the first shift register 13 has 62 shift stages, the first shift stage is an empty shift stage, and the second shift stage is an empty shift stage. The opening/closing information of the key switch S1, the opening/closing information of the key switch B2 for the third shift stage, and the opening/closing information of the key switch 861 in the same way.
The opening/closing information is written in the 62nd shift stage.

Further, this first shift register 13 uses the output pulse of the NOR circuit NOR which sends out the output when all the output count values of the counter 12 are O'' as a write pulse, and uses the clock signal of the clock generator as the write pulse. The information is pushed out sequentially starting with the information of the second shift stage.

The output information of the first shift register 13 is sequentially outputted to the second shift register 14 via an AND circuit AND.

This second shift register 14 transfers the information written in the first shift register 13 to the counter 12.
The information is extracted as one cycle delayed information, and therefore has 62 shift stages.

The AND circuit AND also handles overflow from the logic gate circuit 5N of channel N in FIG. 3, which will be described later.
Key-on data is led to one input side via an OR circuit OR and an inverter circuit 1.

Therefore, when no overflow key-on data occurs, one input side of the AND circuit AND
1” is given.

Next, the output information of the first shift register 13 is guided to one input side of the AND circuit AND2 via the inverter circuit I2, and also to one Oki side of the AND circuit AND3. The output information of the shift register 14 is led to the other input side of the AND circuit AND2, and also to the other input side of the AND circuit AND3 via the inverter circuit I3.

These AND circuits AND2 and AND3 are applied to the key-off data gate circuit 16 and the key-on data gate circuit described above, respectively, and the key-on data gate circuit 1. and controls opening/closing of the key-off data gate circuit 16.

In the above configuration, if only the key switch SI is closed now, while the key switch SI is closed (as shown in Figure 4a)
, 00...0 in the first shift register 13
10'' is written every time the count value of the counter 12 becomes 0 (as shown in Figure 4b).

Therefore, an output jt 1jj is generated on the output side of the first shift register 13 every time the count value of the counter 12 reaches '000001'' (as shown in Figure 4c), and a second shift register 1
Outputs tt and pp are obtained on the output side of 4.

(Illustrated in Figure 4d) Therefore, the AND circuit AND2 outputs the output "'1" as shown in Figure 40, and the output side of the key-on data gate circuit 15 outputs "OO0001". Ru.

Further, the AND circuit AND3 outputs an output "1" as shown in FIG. 4f, and as a result, the key-off data gate circuit 16 outputs an output "OO0001".

Similarly, if you close the key switch S2, the key will turn on.
The data gate circuit 15 displays 'ooooio', and when the key switch S2 is opened, the key-off data
°"000010" will be sent from the gate circuit 16.

The key-on data and key-off data sent from the key signal generator 1 are applied to channel 1 shown in the third diagram.

The key-on data applied to channel 1 is input to one input side of AND circuits 211 to 216, and is also input to one input side of AND circuits 5I□ to 5. is input to one input side of I2.

The output side of the AND circuits 2.1 to 216 is the memory circuit 3. while the inverter circuit 5m is connected to the write input terminal of the
, ~5.6 to the other input sides of the AND circuits 517-5112.

The output terminal of the memory circuit 31 is connected to the sound source circuit 6. and the matching circuit 4, and is also connected to the other input side of the AND circuits 2□-2, 6 via the OR circuit OR2 and the inverter circuit 4.

In the above circuit configuration, key-on data t0000 is generated from the master key signal generator 1 upon closing of the key switch S1.
The case where 01'' is sent will be explained.

In this case, if the memory circuit 31 has no content, the output of the inverter circuit I4 is ゛1'', so l'' is given to all input sides of one of the AND circuits 2□ to 216, and the key -On data ``000001'' is stored in the storage circuit 3I.

Therefore, the logical conditions of AND circuits 5.7 to 522 are not satisfied, and the key-on data "00000"
1'' is not sent out to channel 2.

Next, if the memory circuit 31 has contents, the inverter circuit is installed.

Since the output of ``0'' is O'', the AND circuits 21.-2.6 are not opened, and the key-on data ``000001'' is not output.

Therefore, the logical conditions of AND circuits 517 to 5.12 are satisfied and output to channel 2.
” is sent.

Since the other channels 2 to N have exactly the same circuit configuration as channel 1, the key-on data sent from channel 1 is transmitted from channels 2, 3, etc.
. . . memory circuits with no content are sequentially searched, and if a memory circuit with no content is found, it is stored in that memory circuit and the search for the next channel is stopped.

If the memory circuits of all channels have content,
Key-on data “000001” is AND circuit 5N7 of channel N
. . . 5N12 overflows, and therefore, the output It 1jj is generated in the OR circuit OR shown in the first diagram, and the AND circuit AND is closed, so that the output information of the first shift register 13 is It is not sent to the second shift register 14.

Therefore, the key-on data gate circuit 15 continues to send out the key-on data 'ooooooi' until the memory circuit of any channel becomes empty.

Next, when the key switch S1 is opened, key-off data "'oooooi" is generated and applied to the matching circuit 4.

Therefore, the key-on data '0' is stored in the memory circuit 3□.
If ``00001'' is stored, a coincidence output is generated, and the result ``000001'' applied to the recent terminal I of the memory circuit 3I is cleared and returns to the state with no content.

The sound source circuit 6 provided corresponding to the channel 1 includes a waveform storage circuit 612 that stores a required one-cycle musical waveform in memory, and a waveform storage circuit 612 that stores the memory contents of the waveform storage circuit 612, as shown in the third diagram, for example. Channel 1 memory circuit 3. a waveform readout circuit 60 configured to read out key-on data at a frequency corresponding to the key-on data sent out by the waveform readout circuit 60. It is composed of.

This waveform readout circuit 6.1 can be easily constructed using, for example, a rate multiplier.

Therefore, the scale note corresponding to the key switch Sl now is C2,
cl the scale note corresponding to key switch S2...
・from the scale clock generator group 1 which generates a clock signal proportional to each scale note frequency °" 000001
If a clock signal corresponding to, for example, proportional to the C2 tone is selected in the waveform readout circuit 6□, and the waveform storage circuit 612 is read out using this clock signal, the output terminal out.
A musical sound waveform corresponding to C2 can be obtained at 1.

Although not shown in the embodiment, the sound source circuit 6 converts the clock signal corresponding to the input key-on data into a triangular wave or a triangular wave as appropriate.
Alternatively, it can be applied to various sound source circuits such as a waveform forming circuit that forms a sawtooth wave or the like.

Ten sound source circuits 6 are sufficient.

This is because, in general, in the case of a single-level keyboard, the maximum number of keys that can be played at one time is 10 notes.

As described above, according to the present invention, the number of sound sources can be significantly reduced, the sound source device of an electronic musical instrument can be simplified, and since all processing can be performed using digital signals of '1"tt O", it is possible to integrate circuits. It has excellent effects such as being suitable for

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
FIG. 3 is a circuit diagram of a more specific embodiment of FIG. 1, and FIG. 4 is a waveform diagram for explaining FIG. 2. 1... Key signal generator, 2... Gate circuit, 3... Memory circuit, 4... Coincidence circuit, 5... Logic Gate circuit, 6... Sound source circuit.

Claims (1)

[Claims] 1. A key signal generator that sends out a key press signal corresponding to a pressed key and a key release signal corresponding to a released key as encoded digital signals, and a plurality of key signal generators that temporarily store the key press signals. a memory circuit; a first gate circuit provided corresponding to each of the memory circuits for writing the key press signal to the corresponding memory circuit when the content of the memory circuit is empty; and a first gate circuit corresponding to each of the memory circuits; A second gate circuit is provided corresponding to each of the memory circuits and transmits the key press signal to the next stage memory circuit when the content of the memory circuit is present; A key signal selection device for an electronic musical instrument, comprising a matching circuit that sends a reset signal to a corresponding storage circuit when a key release signal matches the key release signal.