JPS5852854A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5852854A
JPS5852854A JP15096381A JP15096381A JPS5852854A JP S5852854 A JPS5852854 A JP S5852854A JP 15096381 A JP15096381 A JP 15096381A JP 15096381 A JP15096381 A JP 15096381A JP S5852854 A JPS5852854 A JP S5852854A
Authority
JP
Japan
Prior art keywords
pad
layer
semiconductor device
layers
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15096381A
Other languages
Japanese (ja)
Inventor
Takashi Tokura
戸倉　隆
Daiki Ogawa
大樹 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15096381A priority Critical patent/JPS5852854A/en
Publication of JPS5852854A publication Critical patent/JPS5852854A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enable the PAD in semiconductor device freely connectable from any wied layer by a method wheren the PAD in semiconductor device with multi wiried layers is piled over the contact hole connecting said wired layers to come in contact with external elements. CONSTITUTION:The lowermost layer 1 and the uppermost layer 3 may be connected to a part of opening from the first, second and third wired layers 1, 2 and 3 to PAD by means of simply drawing the wired layer needless of any spare space since the contact holes 4 and 5 are arranged at the opening A of PAD. Through the procedures of forming said PAD into multilayer construction, the layer conversion space except PAD may be eiliminated avoiding the troubles in layout and reducing the layout errors.

Description

【発明の詳細な説明】 本発明は半導体装置に関し、特に外部との接触を目的と
するパッド（Ｐ　Ａ　Ｄ）の構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to the structure of a pad (PAD) intended for contact with the outside.

従来、多層配線層をもつ半導体装置におけるパッド（Ｐ
　Ａ　Ｄ）は、最上層の配線層だけで構成されていた。Conventionally, pads (P
AD) was composed of only the uppermost wiring layer.

このため、レイアウト設計に際し、チップ内の各層配！
Ｉｔ１個以上のコンタクトを介して最上層の配線でＰＡ
Ｄに接続する必要があり、ＰＡＤ以外の層変換スペース
を使用し、又、レイアラ）（スを犯す危険をはらんでい
た。For this reason, when designing the layout, it is important to carefully consider the layout of each layer within the chip.
PA on the top layer wiring via one or more contacts.
It needed to be connected to D, used a layer conversion space other than PAD, and risked a layer error.

本発明の目的は、ＰＡＤｔ多層化するととＫより上記欠
点管除去し、どの配一層からでも自由に鋏ＰＡＤへの接
続を可能圧する半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device which eliminates the above-mentioned drawbacks when PADs are multi-layered and allows connection to scissors PADs freely from any wiring layer.

本発明の特徴は、多層配線層を有すゐ半導体装置におけ
るＰＡＤｔ、諌配線層間を接続するためのコンタクトホ
ールと重ね合わせた構造にある。A feature of the present invention is a structure in which PADt in a semiconductor device having multi-layer wiring layers is overlapped with a contact hole for connecting between the wiring layers.

本発明について、図面を参照して説明する。The present invention will be explained with reference to the drawings.

第１図は従来の構造を示す断面図である。FIG. 1 is a sectional view showing a conventional structure.

半導体基板９に部分的に第１拡散配線層１が設けられる
。第２拡散配線層１と第２配線層２とは、絶縁膜６にあ
けられたコンタクトホール４を介して接続される６さら
に、第２配線層２と第３配線層３とは、絶縁膜７に設け
られたコンタクトホール５を介して接続される。パッド
の開孔部人以外は、保鏝カバ８で覆われている。A first diffusion wiring layer 1 is partially provided on a semiconductor substrate 9 . The second diffusion wiring layer 1 and the second wiring layer 2 are connected to each other via a contact hole 4 made in an insulating film 66.Furthermore, the second wiring layer 2 and the third wiring layer 3 are connected to each other through an insulating film 6. The connection is made through a contact hole 5 provided in 7. The opening of the pad except for the person is covered with a protective cover 8.

この構造の場合、最下層のＩ１１拡散配線１を最上縁起
［３１で接続するために、ＰＡＤ開孔郁ムのスペース以
外の所に：２ンタクトホール４及びｓｔ−設けるように
レイアウト設計することが必要である。In the case of this structure, in order to connect the bottom layer I11 diffusion wiring 1 at the top edge [31], the layout can be designed to provide two contact holes 4 and st- in a place other than the PAD opening space. is necessary.

１１２図は本発明の一実施例を示す断面図である。FIG. 112 is a sectional view showing an embodiment of the present invention.

この構造の場合、最下層１と最上層３との接続は、ＰＡ
Ｄ開孔部人の部分圧コンタクトホール４及び５が配しで
あるため、第１図のように余分のスペースを必要とする
ことなく、実施することが可能である。すなわち第１．
第λ第３配線層１．＆３のどの配線層からでも、開孔部
Ａの部分に接続したり、配線層を引き込むだけでＰＡＤ
への配線が可能になる。本実施例では、３層配線構造に
ついて記したが、さらに多層の場合も同様である。In this structure, the connection between the bottom layer 1 and the top layer 3 is PA
Since the partial pressure contact holes 4 and 5 are arranged in the D opening, it can be implemented without requiring extra space as shown in FIG. That is, the first.
λth third wiring layer 1. & 3 from any wiring layer, just connect to the opening A part or pull the wiring layer to PAD.
wiring becomes possible. In this embodiment, a three-layer wiring structure has been described, but the same applies to a multi-layer wiring structure.

本発明の他の実施例として全層を重ねることなく必要の
ある層だけｔＰＡＤ部分Ｋ１１ｌ（＜ことも可能である
。但し、この場合不要層に関係するコンタクトホールは
同様に配置する必要がある。As another embodiment of the present invention, it is also possible to overlap only the necessary layers in the tPAD portion K11l (<) without overlapping all the layers. However, in this case, the contact holes related to the unnecessary layers must be arranged in the same way.

算３図は２層構造の場合の本発明によるさらに他の実施
例を示す断面図である。Figure 3 is a sectional view showing still another embodiment of the present invention in the case of a two-layer structure.

この場合は、第２配線層２及び第３配線層３から本ＰＡ
ＤＫ自由に配線できる構造となっている。In this case, from the second wiring layer 2 and third wiring layer 3 to the main PA
DK has a structure that allows for free wiring.

本発明は、以上説明したように、ＰＡＤｔ多層構造にす
ることＫより、ＰＡＤ以外の層変換スペースをなくシ、
且つレイアウト時の煩られし１５ｔ−なくすともにレイ
アウト建スを低減できるという効果がある。又ＰＡＤ部
分に大きいコンタクトを設けるため、信頼度の向上が図
れる。As explained above, the present invention eliminates layer conversion space other than PAD by creating a PADt multilayer structure.
In addition, it is possible to eliminate 15 tons of trouble during layout and reduce layout space. Furthermore, since a large contact is provided in the PAD portion, reliability can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

槙１図は従来のパッド（ＰＡＤ）周辺の構造断面図、第
２８！ｉ！、第３図はそれぞれ本発明の実施例を示す断
面図である。 同図において、Maki Figure 1 is a cross-sectional view of the structure around the conventional pad (PAD), No. 28! i! and FIG. 3 are cross-sectional views showing embodiments of the present invention. In the same figure,

Claims (1)

【特許請求の範囲】[Claims] 多層配線層と、外部との接続用パッドとを有する半導体
装置において、前記パッドの開孔部下Ｋ、前記多層配線
層間を接続するためのコンタクトホールを配したことｔ
特徴とすゐ半導体装置。In a semiconductor device having a multilayer wiring layer and a pad for connection with the outside, a contact hole for connecting between the multilayer wiring layers is arranged below the opening K of the pad.
Features: Semiconductor devices.
JP15096381A 1981-09-24 1981-09-24 Semiconductor device Pending JPS5852854A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15096381A JPS5852854A (en) 1981-09-24 1981-09-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15096381A JPS5852854A (en) 1981-09-24 1981-09-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5852854A true JPS5852854A (en) 1983-03-29

Family

ID=15508258

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15096381A Pending JPS5852854A (en) 1981-09-24 1981-09-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5852854A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6378555A (en) * 1986-09-20 1988-04-08 Fujitsu Ltd Asemiconductor device
US4926236A (en) * 1986-02-12 1990-05-15 General Electric Company Multilayer interconnect and method of forming same
US5151770A (en) * 1989-11-24 1992-09-29 Mitsubishi Denki Kabushiki Kaisha Shielded semiconductor device
US5256590A (en) * 1989-11-24 1993-10-26 Mitsubishi Denki Kabushiki Kaisha Method of making a shielded semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS494622U (en) * 1972-04-13 1974-01-15
JPS5227389A (en) * 1975-08-27 1977-03-01 Hitachi Ltd Semiconductor device containing multi-layer wiring
JPS5553441A (en) * 1978-10-14 1980-04-18 Sony Corp Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS494622U (en) * 1972-04-13 1974-01-15
JPS5227389A (en) * 1975-08-27 1977-03-01 Hitachi Ltd Semiconductor device containing multi-layer wiring
JPS5553441A (en) * 1978-10-14 1980-04-18 Sony Corp Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4926236A (en) * 1986-02-12 1990-05-15 General Electric Company Multilayer interconnect and method of forming same
JPS6378555A (en) * 1986-09-20 1988-04-08 Fujitsu Ltd Asemiconductor device
US5151770A (en) * 1989-11-24 1992-09-29 Mitsubishi Denki Kabushiki Kaisha Shielded semiconductor device
US5256590A (en) * 1989-11-24 1993-10-26 Mitsubishi Denki Kabushiki Kaisha Method of making a shielded semiconductor device

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