JPS5852748A - Memory control system - Google Patents

Abstract

PURPOSE:To control a part to be operated at a high speed without increasing memory capacity greatly, by providing an area for storing operation information for operating another part to be operated corresponding to respective areas of a memory stored with commands. CONSTITUTION:Areas for storing operation information for operating parts to be operated are provided corresponding to respective areas of a memory stored with commands. For example, a central processing unit CPU2 reads programs from the program starting addresses of control memories 1a and 1b through an address bus 5 and a data bus 7 to perform processing. Then, a parity check circuit 8 checks the parity bit output of the control memory 1b to detect an error in data stored in the memory 1b, and when the processing of the CPU2 is passed to the program in an address A1, a counter 10 sends a count permit signal. Then, a latch 11 latches the count output of the counter 10 to output a time-over detection signal to the CPU2, thereby performing processing for time- over occurrence.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory control system, and particularly to a processing device (hereinafter referred to as C
This paper relates to a memory control method in which actuated parts are operated 11111i41 by program commands on the memory via the PU (abbreviated as PU). Conventionally, when operating the workpiece Jwls' on the hardware, it was performed using the 0PUillllllll program. . That is, a command for controlling the actuated parts is stored in the OPU control memory, and after reading out this command, each actuated part is controlled according to the successively issued commands.

However, in the above-described method, each of the waO actuated part control commands is provided in the control program V'3, which results in an increase in the number of steps in the control program, and as a result, a memory with a large capacity is required.

Furthermore, a delay occurs from the time the OPU inserts a command until the actuated part is actually activated due to the processing time of the OPU. For example, if the actuated part measures the processing time of a command such as a timer, the delay time of the timer activation time on the actual hardware with respect to the timer activation time threshold on the program is the tt hardware. It also has the drawback of slow operation time.

The purpose of the present invention is to eliminate the drawbacks of the prior art, without significantly increasing the memory capacity (step Hf1 of the CPU control program).
The object of the present invention is to provide a memory control method that can immediately activate a created aS upon access.

In order to achieve the above object, the memory control method of the present invention is! 6
It has a JI device, a memory for storing commands, and a plurality of actuated parts, and after the processing W&P indulges the program command in the memory, it activates the predetermined actuated parts according to the #continuous command. In the memory SI control method 2,
An area for storing operation information for activating the actuated st of the memory ff14c and others is provided corresponding to the next area where each of the commands is stored, and at the same time when the processing device indulges the command, the operation information is stored from the area where the operation information is stored. The goal is to cause the other actuated at to actuate based on the actuation information that is successively output.

Section 1 below: The present invention will be explained in detail using @S diagram・Essay 1#
! J is a diagram showing an example of an OPU control memory circle ssg in the memory control method of the present invention.

This is the OPU control memory for 1m lb#i8 pit data in the same figure. Here, the data to the OPU is 8 bits, and one parity pit is added. However, if a reprinted memory with an 8-bit output is used, surplus pits will occur as shown in the figure. In this embodiment, one of the surplus bits is used as an operation pit for starting the timer. For example, this operating pit is 1! @
Assuming that the timer is activated only during the period when the output is 1", as shown in the figure, the operation bits at addresses A, i from address Al are set to 1111, and the operation bits at other addresses are set to Igll, so that the OPU can A1 to A
It is possible to start a timer for a period of time to execute the steps up to . By setting the counter time of the timer in advance, it is possible to detect a time-out on the hardware during the step t-execution period in which the timer activation is set.
FIG. 3 is a diagram showing an example of a memory ffriIIi41 method using lb. In the figure, 3 is the CPU, 8 is the clock generator, number is the latch, 5 is the address bus, 6 is the decoder, 7 is the data bus, 8 is the parity check circuit, 9 is the data memory, 10 is the counter %, and 11 is the There are two steps. 0PU
The lower 11 bits (All to Ao) of address bus 5 (person 0. to A0) of il are l! PIJ memory la, l
b, connected to the data memory 9; The decoder 6 is connected to the Kamijo bits (M1h to AtS) of the address bus 5, and decodes the memory selection information from the CPU 5 and sends a selection signal to each memory.On the other hand, the data bus 7 is connected to the !II official memory. The 8-bit output of 11 is connected.The data memory 9 is used to store calculation results, data, etc. for processing various programs according to the 0PUI or control program. The timer operation pit output of allIO4 memory 1/lb which performs data collection with 0PUI via 0PUI is connected to the count permission CTE and reset terminal of counter 10.
The counter clock to the counter 10 is supplied with the output of a clock generator s'm that supplies the OPU drive clock.

The operation will be explained below.

The 0PUI sequentially reads programs from the program start address of the control memory la*lb via the address bus 5 and the data bus.

The parity pit output of control memo 1Jlb is always checked by parity check 1gl about 8,
biUsed to detect errors in stored data.

When the processing of oPum moves to the program step of the address Al shown in the diagram wc1, the operation pit output of the control memory lb becomes 118, and the count permission of the counter 1G becomes mq. Since the address output of 0PUI is held in level by the latch number, from the time OP[J21 continues to program the address A0, the program A is executed and the next address A is output to the address bus A@=AII. However, the operating pit output remains at m1ll until the next program starts execution, and the counter lO
will perform time measurement during this period. When the processing up to 0P (l is the address person) is completed and the program step of the next address is executed, the operation pit output becomes OI again, which acts as a reset force for the counter IO, and the counter IO is reset.However, when the address Al OP in 1 from 1 When executing J, the process becomes an eternal loop due to a runtime error etc. - If the address does not move on to the next program execution, the pre-given count output of counter O is output. Time over detection is performed by

Latch 11 latches the count output from counter O and OPU! He time over detection bias detection mountain number, OP
Um uses this time over detection peak number as an interrupt peak number and proceeds to the process when the timeout occurs.As described in 7 above, according to this embodiment, the timer can be easily set by simply setting the timer 1 operation pit in the control memory. Operation control can be performed. Furthermore, any number of timer set/reset locations using the tie 1 operation pit can be provided at any location in the control program, and moreover, the timer set/reset is a carefully planned program that does not affect the number of city control program steps at all. Time O-5-
This is effective when there is no room for detection. Also, since the output from the memory is used as a direct timer operation signal, 0PLI
According to the present invention, the actuated part on the hardware can be controlled with a simple hardware configuration. , 0PUWIJ@ program can be greatly simplified and reduced. Furthermore, since the operation of the Jill 11 to be operated can be controlled simultaneously with the OPU's command input, even high-speed actuated units can be accurately controlled.

In this embodiment, a memory control method using a timer has been described, but the present invention is not limited to this, but is also applicable to a method in which the operation of an actuated part is controlled using the next operation bit output provided in the memory. Of course, the present invention can be applied if

[Brief explanation of drawings]

Claims (1)

[Claims] A memory play that has all devices, a memory for storing commands, and a number of actuated parts, and after the Ishigaki device successively issues commands in the memory, a predetermined actuated part is activated in accordance with the successive commands. 2) In the method, an area for storing operation information for activating another workpiece 11hflA is provided in the memory P3 corresponding to an area in which each of the m commands is stored, and at the same time when the IIJI embedded device outputs the command, A memory control method characterized by operating the nine other work units based on the operation information that is stored and successively output from the next area.