JPS5852578A - Device for testing integrated circuit - Google Patents

Abstract

PURPOSE:To shorten the time required for checking the cause of failure, by generating a test pattern signal and an expected pattern signal from an address signal, and providing a storage register of a pattern address on a circuit for comparing the test data signal with the expected pattern signal. CONSTITUTION:A storage part 1 of a test pattern applied to an IC6 to be tested receives a signal 10 of an address control part 3, and outputs a test pattern signal 9 and an expected pattern signal 8. Test data information 16 of the IC6, and the signal 8 are applied to a deciding circuit 7. In this case, a pattern address which has executed an instruction of the control part 3 is stored in a storage register 13, and when the circuit 7 has decided its failure, a control signal 15 of a write control part 5, and an address of the register 13 are stored in a storage device 14 together with the signal 10 and good/failure information 12 of every pin of the circuit 7. Accordingly, it is possible to know an address of a call instruction of a subroutine by reading the contents of the device 14, and it is possible to shorten the time required for checking the cause of failure of the IC to be tested.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit testing device, and more particularly to a failure analysis device provided within the testing device.

In general, integrated circuit test equipment! (hereinafter referred to as IC test equipment)
When testing integrated circuits (hereinafter referred to as IC), prepare a test pattern for each type of IC to be measured in advance, input this test pattern = 6 IC test equipment, and temporarily store it in the built-in pattern generation section. .

This't1. All 1. The IC under test is tested by applying voltage to the IC under test from address 0 to the final address at the start and comparing the output from the IC under test with the output expected from the test pattern. When the test pattern is stamped on the IC under test, if for some reason the output from the IC under test does not match the output expected from the test pattern, that is, the expected value, at any position in the test pattern, this IC under test It is said to be defective. In this case, it is necessary to investigate the cause of this failure. Therefore, in order to know the address of the test pattern where this defect occurred and the output pin of the IC under test that became defective, it is necessary to memorize the pass/fail result for each pin of the IC under test at that address. An analysis device is provided within the IT test equipment.

In recent years, the integration level5 functions of ICs have improved dramatically, and the number of test patterns required for testing has become enormous.The pattern generation section of the test equipment also requires a huge amount of memory to store the test patterns. Part f is becoming more and more demanding. Moreover, since the test pattern generator is required to operate at high speed, the test equipment becomes extremely expensive. In order to prevent the price of equipment from rising, we have devised various ways to generate test patterns to shorten the length of test patterns. The most commonly used method for this is to allow subroutines to be set within the test pattern.

Conventionally, in an IC test device having a pattern generation section as described above, a defect analysis device stores the address of the test pattern where a defect occurred and the pass/fail information for each bin at that time while generating the test pattern. By reading this content at the end of the test, it is possible to obtain information on the address and bin number of the defective test pattern.

FIG. 1 is a schematic diagram of an example of a conventional failure analysis device for an IC testing device.

In Figure 1, ■ is a pattern memory "J" that stores the test pattern to be applied to the test object 1C, and 2 is a microinstruction for controlling the address order of pattern memory operations that occur at the start of the test. 3 is an address control unit that decodes the microinstructions stored in the microinstruction storage unit 2 and controls the order of generation addresses in the pattern storage unit 1. 4 is a test pattern generation unit. A storage device 5 stores the address of the pattern storage unit 1 and the pass/fail information for each pin at that time when a defect occurs in the pin; A storage control unit that stores the defective address into the storage device 4, 6 is the IC under test, 7
8 is a determination circuit that compares the output from the C6 under test with the expected pattern from the pattern storage unit 1 and determines whether or not they match for each bin; 8 is a determination circuit 7 from the pattern storage unit l;
9 is an expected value signal for applying an expected pattern to the judgment circuit 7 to determine the output from the test target 1c; 9 is a test pattern signal for applying a test pattern from the pattern storage unit l to the test target 115; 10 is an address An address signal 11 is an address signal that controls the address order of the pattern read by the control unit 3, and 11 is output from the judgment circuit 7 when the expected pattern and the output of the IC under test do not match, that is, when a defect occurs. The writing No. 4g and No. 12 are the good/bad information No. 12 for each bin outputted from the determination circuit 7.

At the start of testing the IC under test, the address control section 3 decodes the microinstructions from the microinstruction storage section 2, and applies the address signal 10 to the pattern storage section 1 in accordance with the decoding result. The pattern storage section 1 applies a test pattern signal 9 to the test object 1C6, and outputs an expected pattern signal 8 to the determination circuit 7.

5- At the same time, the microinstruction at this address is read and decoded by the address control unit 3, and the address to be generated next is given to the pattern storage unit 1. In this way, γ is applied to the IC under test 5 at the last address 1 of the test patterns stored in the pattern storage section 1 in order.

At this time, if a defect occurs in the determination circuit 7 while the test pattern is being generated, the determination circuit 7 outputs a correction signal 11 to the write control unit 5. Then, the address signal 10 from the address control section 3 is input to the storage device 4. As described above, good/bad information for each bottle is repeatedly written to the storage device 4 for each bottle where a defect occurs. As a result, defect information can be obtained by reading the contents of the storage device 4 after the test pattern has been generated up to the final address.

When a subroutine is set within a test pattern, the test pattern generation order is as follows.

Test patterns are generated in order from address O in pattern storage section 1, but if a call (CALL) instruction that generates a test pattern in the subroutine section is set in the microinstruction at addresses 01 and C2. +('After the occurrence of address 1, the Kashio address moves to the specified n subroutine. 1 Generates address A2 from A1 of this subroutine, generates a pattern at address 01+1 from that IL, and then from C2 It executes sequentially up to the address, and when it generates the C2 address, it goes back to the subroutine and generates the QA1 to 2 addresses, and then generates the C2+1 address.In this way, each time the call instruction is set as a microinstruction, the subroutine is executed. Address A2 will be generated from 80.At this time, if the defect occurs while the address A2 is occurring from subroutine A1, the defective address written to the storage device 4 will be from A to A2. However, addresses from this person 1 to A2 are changed every time there is a call command, that is, ClIC2.
Since the execution is executed at both addresses, it is difficult to determine whether the fault occurred because the call was made at address C□ or whether the nfc was discharged at address C2.
Even if the contents of the storage device 4 are read after the test pattern generation ends, it is unclear. For this reason, it is necessary to investigate where the defect occurred. In order to check the call address where the defect occurred, first check the pattern storage unit 1 from address O to address 01 and C2.
The test pattern must be generated between addresses to see if a defect occurs, and then the call addresses must be executed in order to see if a defect occurs, checking up to address C2. That is, the test pattern is divided and examined every time n call instructions are set. However, as the functions of ICs under test become extremely complex and the degree of integration increases, subroutines are frequently set in test patterns, and if a defect occurs in a test pattern within a subroutine, it becomes very difficult to investigate. The disadvantages are that it is difficult and requires a lot of time and effort.

The present invention eliminates the above-mentioned drawbacks by adding a memory register that stores the address of the pattern memory where the calling instruction was executed, so that even if a defect occurs in the subroutine, reading the contents of the storage device will allow the address of the calling instruction of the subroutine to be stored. An object of the present invention is to provide an integrated circuit testing apparatus t that can shorten the time required to investigate the cause of a defect in an integrated circuit under test.

The integrated circuit testing device of the present invention includes a microinstruction storage section, an address control section that decodes microinstructions from the microinstruction storage section and outputs an address signal, and receives the address signal and outputs a test pattern signal and an expected pattern signal. a pattern storage unit that generates an output from the integrated circuit under test according to the test pattern signal; a determination circuit that compares and determines the test data information and the expected pattern signal; a storage register that stores the address of the pattern storage section where all the call commands have been executed among the address signals; and a write control section that receives the pledge signal output from the determination circuit when the determination circuit determines that the determination circuit is defective. and the address control section and the address control section store the address of the Bakun storage section to be outputted from the storage register and the good/bad information for each bin outputted from the judgment circuit. It is constructed by incorporating a failure analysis device including a storage device for storing data.

Next, embodiments of the present invention will be described using the drawings.

FIG. 2 is a block diagram of one embodiment of the present invention.

9- The integrated circuit testing apparatus of this embodiment includes a microinstruction storage section 2, an address control section 3 that decodes the microinstructions in the microinstruction storage section 2 and outputs an address signal 1 (l), and an address control section 3 that receives an address signal 1o. A pattern storage unit 1 that generates a test pattern signal 9 and an expected pattern signal 8, and a judgment that compares the test data information 16 outputted from the C6 under test with the test pattern signal 9 and the expected pattern signal 8. A circuit 7, a memory register 13 that stores the address of the pattern storage unit 3 at which the pattern storage instruction has been executed, out of the address signal lO received from the address control unit 3, and a determination circuit 7.
The judgment circuit 7 outputs a pledge signal fL when it is determined to be defective.
The failure analysis device is fully built-in, including a storage device 14 for storing the address of the pattern storage section outputted from the storage register 13 by 0 and the pass/fail information 12 for each pin outputted from the judgment circuit 7. It is configured.

In the integrated circuit testing apparatus of this embodiment, when the address system 10-part 3 decodes the micro-instruction and executes the calling instruction, the address of the pattern storage part 10 where all the calling instructions have been executed is recorded. A memory register 13 is added, and the determination circuit 7 determines that it is defective, and the pledge signal 11 is output.
It is different from the conventional technology in that the memory device 14 is configured such that when one pattern is stored, the defective address in the memory section 1, the pass/fail signal 12 for each pin from the determination circuit 7, and the contents of the memory register 13 can be written all at once. It's different.

Next, the operation of this embodiment will be explained.

When the test pattern 9 is generated, when a call instruction for address C1 of the pattern storage section 3 is executed, C□ is stored in the storage register 13. At this time, if a defect occurs between subroutine 80 and address A2, the contents of the memory register 13 are written to the memory device 14 along with the address of the pattern memory section l at that time and the pass/fail information for each pin from the determination circuit 7. Komaruru.

That is, if a defect occurs in a subroutine, the address of the calling instruction for that subroutine is also stored in the storage device 14, so that the address of the calling instruction for that subroutine is also stored in the storage device 14.
By reading the contents tW, it becomes possible to immediately know the address of the subroutine call/-instruction. For this reason, the time taken to investigate the cause when a defect occurs in a subroutine, as in the conventional method, is reduced, as shown in FIG.

As explained in detail above, according to the present invention, even if a defect occurs in a subroutine, it is possible to know the contents of the storage device and the address of the output instruction of the subroutine. This has a great effect because it provides an integrated circuit testing device that can completely shorten the time it takes to investigate the cause of a problem.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of a conventional failure analysis device for integrated circuit testing equipment, and FIG. 2 is a block diagram of an embodiment of the present invention. 2...Microinstruction storage unit, 3...Address filJA unit, 4...Storage device, 5...Installation control unit, 6... ...IC17 under test...Judgment circuit, 8...Expected pattern signal, 9...
Test pattern signal, 10...Address signal, 1
1...Oath control signal, 12...Good/bad information signal for each pin, 13...Storage register, 14...Storage device, 15・・・・・・Sakomi control signal, 16・Old・・Test pattern No. 1g. 13- No./Part/2 3. 3 もFl/Z'1! Q' 4・Thanks C2 key i A/ 2 Da 2 Record φ turbidity, ) 3 O Remenuta d' Public and private, Ken 1
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Claims (1)

[Claims] a microinstruction storage section, an address control section that decodes the microinstruction from the microinstruction storage section and outputs an address signal, and a pattern storage section that receives the address signal and generates a test pattern signal and an expected pattern signal; output from the integrated circuit under test according to the test pattern signal.
a determination circuit that compares and determines the test data information and the expected pattern signal; and a determination circuit that compares the test data information and the expected pattern signal, and
a memory register that stores an address of the pattern storage unit that executed the call command among the address signals to be executed; and a write control unit that receives a write-in signal output from the determination circuit when the determination circuit determines that the determination circuit is defective. and pattern description 1. output from the storage register according to signals from the storage control section and the address control section. 1. An integrated circuit testing device comprising a built-in failure analysis device including a storage device for storing the part address and pass/fail information for each pin extracted from the determination circuit.