JPS5852168A - Elevator controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an elevator control device, and in particular, facilitates signal transmission between various control terminal devices installed in a car and a control device main body installed in a machine room that controls the elevator. The present invention relates to an elevator control device suitable for.

Some of the control terminal equipment constituting the elevator control device is also provided in the car. Examples include a car destination button, its response light, and a car position indicator light. For this reason, a tail cord is used to connect the control panel, which is the main body of the control device for controlling the elevator, located in the machine room, and the terminal equipment provided in the car. By the way, this tail cord bends as the car goes up and down, so there is a risk of it breaking.
In addition, since the shafts may shake during an earthquake and hit the protrusions in the hoistway and be damaged, there is a desire to reduce the number of shafts as much as possible so that they do not hit the protrusions in the hoistway. Furthermore, from the viewpoint of resource saving, the number of tail codes is reduced by multiplexing signals for transmission and reception.

For this purpose, there is a method of transmitting and receiving signals between the control panel in the machine room and an auxiliary control device provided in the car, and transmitting and receiving signals from the auxiliary control device to each control terminal device.

The prior art will be explained below with reference to FIGS. 1 and 2. 1st
In the figure, there is a micro processing unit (hereinafter abbreviated as MPU) 1, a random access memory (hereinafter abbreviated as RAM) 3, and a read-only memory (hereinafter abbreviated as R (abbreviated as II)). A microcomputer (hereinafter abbreviated as microcomputer) consisting of 5 etc.
(Large 5ca
9 (for example, Hitachi's new HD46850ACIA) and connect this LS
I9 is connected to a microcomputer 13 provided in the car via a tail cord 11 to communicate with an LSI 15 (same as LSI 9). Note that the microcomputer 13 is also provided with a RAM 17 and a ROM 19, and via an adapter 21 for external input/output, for example, a car destination button 23 and a response light 25, which are one of the above-mentioned control terminal devices.
It is designed to exchange signals with. in this case,
This has the advantage that only a few signal lines are required to connect the car and the machine room.

Also, as another example, when connected to a microcontroller and working
A dedicated signal for transmission is created by SI, and a similar L signal is used for the car.
There is a system in which an SI is provided and this dedicated signal is transmitted and received through several signal lines.

Its block diagram is shown in FIG. In Figure 2, the first
Parts having the same functions as those in the figures are indicated by the same reference numerals, and description thereof will be omitted here. In FIG. 2, LSIs 31 and 33 are used to generate the above dedicated signal. LSI
The difference between 31.33 and 819.15 in Figure 1 is that signals can be easily sent and received without an MPU.

Another advantage other than being able to transmit data using just a few signal lines is that a large amount of data can be sent and received in a short period of time because it uses a dedicated LSI for transmission. You must use a tail cord in which the wires are combined (for example, one tail cord consists of 20 wires), so the wires must be combined in one tail cord. It has the disadvantage that it is susceptible to noise from other signal lines, and countermeasures are required to prevent malfunctions caused by this noise. Therefore, in Fig. 1, the microcomputer 13 must be installed in the cage, and in Fig. 2, the expensive LSI 3'l', 33 must be used, which makes it impossible to reduce the number of tail cords 11. However, the cost has increased, making them more expensive than the elevators currently in use, and the current situation is that they are not very practical.

In order to eliminate these drawbacks, a method as shown in FIG. 3 has been proposed. The characteristics of this method are that a microcomputer is used as the elevator control device, and the signal transmission speed is set as low as possible to transmit signals between the control panel in the machine room and the car control terminal equipment. The aim is to reduce malfunctions due to internal noise, and at the same time, the microcomputer itself that controls the elevator can directly control transmission signals, thereby making the elevator control device inexpensive.

In FIG. 3, parts with the same functions as those in FIG. 1 are designated by the same reference numerals, and their explanation will be omitted here. In Figure 3, M
An interface adapter (IP) 41 that temporarily holds signals from the PU 7 and reads signals from the outside.
A tail cord 11 is connected to the IP 41, a signal decoding device 43 is provided to the car, and the tail cord 11 is connected to the car. And in the signal decoding device 43,
The destination button 23 of the car and its response light 25 are connected. The signal decoding device 43 is the same hardware as the adapter 21 shown in FIG. 1, and its cost is almost the same. Further, the IP41 is composed of a simple latch and a tristate gate, and is extremely inexpensive in terms of cost.

However, when using the method shown in FIG. 3, the above approach has the following major drawbacks. That is, the signal transmission speed is low.

The present invention has been made in view of the above, and an object of the present invention is to provide an elevator control device that can prevent the delay time caused by this from becoming a problem in control even if the signal transmission speed is slow. It is in.

A feature of the present invention is that an input signal from a control terminal device installed in a car is decoded into an output signal from a control device main body that controls an elevator installed in an elevator machine room, and the decoding result is used to perform the above-mentioned functions. When the auxiliary control device provided in the above section operates the specified control terminal device provided in the control device, an output signal corresponding to the input signal is generated before receiving an output signal corresponding to the input signal from the main body of the control device. The present invention is characterized in that a signal is output from the auxiliary control device to the specified control terminal equipment to provide an immediate response function with a high pitched voice.

The present invention will be described below with reference to the embodiments shown in FIGS. 3 to 8 and FIG. 9, but since FIG. 3 has been described above, the explanation will be omitted.

FIG. 4 shows I of FIG. 3 related to the elevator control device of the present invention.
It is a detailed block diagram showing one example of P41. The data bus DB of MPU 1 in FIG.
D to 8D and output terminal I of tristate gate 53
It is connected to Y~8Y.

Note that the MPUI used in this example is an 8-pint MPUI.
[It is J. On the other hand, an address decoder 55 is connected to the address bus AB, and this decoder 55Fi, FF
51 and the specific address of tristate gate 53 are MP
When the output is output from Lll (M P U l is FI”
51 or tristate gate 53, the address decoder 55 outputs an output. The output of the decoder 55 is combined with the read/write signals R, /W from MP[Jt by the AND gate 57.

The output of FF51 is a transistor (hereinafter abbreviated as TR -To
) 59 to the TR 59 through a gate 61, and is connected to the power supply P. For DI and D2, the n signal AO~
A2. Outputs DI and D2. These signals @ have a tail code 11. It should be noted that the above signal lines are for only bits .theta..about.2 and bits 6.7 out of 8 bits from the data node DI3.

On the other hand, the tristate gate 53 has a tail code 1.
A signal obtained by voltage-dividing the signals 1 to I4 from 1 to 1 by a resistor 65 is applied via a level conversion gate 67. Note that a capacitor 69 is connected to this input circuit to absorb noise in the time width of the time constant due to CR.

FIG. 5 is a detailed block diagram showing an embodiment of the signal decoding device t43 of FIG. 3 according to the present invention. Tail code 1
1, the signals AO to A2. DI, D2.
The input signals of each n of Tl to T4 are passed through the voltage dividing resistor 73 and the capacitor 75 to the level conversion gate 77, and the respective output signals (It-I4') are transmitted to the TR
79, and is outputted via a pull-up resistor 81.

After passing through the gate 77, the signals DI and D2 are input to data input terminals ID and 2D of eight FFs 83 similar to the FF 51. Further, the signals AO to A2 are inputted to the decoders 85 and 87 after passing through the gate 77. The decoder 85.87 is the new Hitachi ID74 LS.
138 is used. Output terminals YO to Y of decoder 85
The eight outputs from 7 are input to a delay circuit 89, which is connected to signal lines AO to A2. The temporary output output from the delay circuit 89 is absorbed by the delay circuit 89.

The output of the delay circuit 89 is input to the trigger input terminal T of the nT'F 83. Note that the delay circuit 89, when the signals DI and D2 are completely input to the FF 83,
It also functions to apply the output of the decoder 85 to the trigger input terminal T of the FF 83.

In this way, according to the embodiment shown in FIG.
Since there is no need to create and input a special pulse to the input terminal T of the circuit 83, the circuit configuration can be simplified.

Although it depends on the configuration of the FF83, for example, when using Hitachi's new HD74LS175 as the FF83, malfunction may occur unless a Schmitt trigger IC is inserted between the delay circuit 89 and the FF83. Caution must be taken.

Since the input terminal C of the other decoder 87 is grounded,
At the time of output from the output terminals Y4 to Y7 of the decoder 85, outputs C are also output from the output terminals YO to Y3. This output is input to four tristate gates 91 similar to tristate gate 53 in FIG.

On the other hand, the car destination button 23, which is one of the car control terminal devices, is connected to the corresponding response light 25.
Further, it is connected to a thyristor (hereinafter abbreviated as SCR) 93 and an input voltage dividing resistor 95. And 5CR93
is connected to the SCR driving gate 97, and the gate 9
7 is designed to be operated by outputs from output terminals IQ and 2Q of the PF33. Further, the voltage dividing resistor 95 is connected to a level conversion gate 99, and the output of the level conversion gate 99 is an input to the tristate gate 91. 4
Output terminals IY to 4Y of tri-state gates 91
The output from the gate drives TR79 through the gate 101.

Note that the power supply PAC with a response of 25 is a full-wave rectified direct current, and when the gate signal of the 5CR93 disappears, the light goes out when the next waveform becomes OV.

Below, signals 11jAO to A2 are connected to address lines and signal line D1.
．． This is because D2 is referred to as an output data line, and signal lines Tl to 4 are referred to as input data lines. A set of three signals transmitted by this address line (signals indicating the address of the terminal device)
AO to A2 are input to decoders 85 and 87 and decoded, but as for output, two types of data are simultaneously sent via the output data line. □When an address and two types of data are sent, there are two types of control terminal equipment with the same address, so the data lines are used to distinguish between them. Further, four types of input data are output from the decoder 87 to the input data line, but since these also have the same address, they are distinguished by the input data from the input data line. That is, the output control terminal devices are grouped two by two and given one address, and at the same time, the four input control terminal devices are also grouped and given the same address. However, for input, two addresses are attached.

Next, the above-mentioned software will be comprehensively explained while explaining the software of the microcomputer 70 shown in FIG.

The software includes 40 m5 tasks that are executed every 401 nS as shown in Figure 6 and 10 mS tasks that are executed every 10 mS as shown in Figure 7.
There are pack ground tasks and programs that start these tasks at predetermined intervals.

FIG. 6 is a flowchart showing an example of the program for the 40m5 task, in which block 601111 represents that there is a 40mS task, and the next block 603 represents the execution of the elevator control program. The details of this program are not directly related to the present invention and are therefore omitted from illustration.1 In summary, the presence or absence of input signals from the hall call button and the destination button/23 of passengers in the car, which are control terminal devices, is checked. When a call is received, the elevator is operated by calculating the call and the position of the corner, and the speed is controlled according to the position. When the car stops, the elevator controls the opening and closing of the doors at the next destination floor. It is a program. Changes in status are checked once every 40m5, and processing is performed accordingly, and the results are output to each terminal device.

The program shown in FIG. 7 creates part of the input data (input data from the car control terminal equipment) for the program shown in FIG. 6.

'This program is also part of the program that outputs the processed results to each control terminal device (output to the car control terminal device).

In FIG. 7, a block 701 is shown to be a filter. Since this program is repeated for each program ti, tOmS, the order differs from the program order, but the explanation will be given starting from block 713. In block 713, two pieces of output data (for data lines DI and D2) of the control terminal equipment corresponding to the destination address are extracted from addresses AO to A2 in FIGS. 4 and 5, and in block 15, this output data is extracted. The data and the addresses of the control terminal equipment group are edited as shown in FIG. The data edited by the block 717 is then output to the FF 51 in FIG.

That is, when the MPUt stores the data to the address of the FF 51, the output of the decoder 55 and the R/W signal are combined at the AND gate 57 and input to the trigger input terminal T of the FF 51. Therefore, the output data in Figure 8 at that time is %F
Write and send in F51. The results of 7 are immediately outputted to addresses l1lAO-A2 and output data DI, D2, and then passed through the tail code 11 and given to the upper signal decoder 43 (see FIG. 3). Then, the address signals AO to A2 are input to the decoder 85 (see FIG. 5), and only one signal out of the eight outputs is outputted, passes through the delay circuit 89, and becomes the trigger input of the FF 83. . At this time, one of the eight signals corresponding to address signals AO to A2
Only those data are selected and their output data DI and D2 are stored. This output is given to 5CR93 via gate 97.

5CR93 is ignited or extinguished, and as a result, the response light 25
turns on or off.

Similarly, the decoder 87 outputs a signal to select only one of the four tri-state gates 91, and outputs the input from the next button 23 to the gate 10.
It passes through the tail cord 11 via the 1% TR 79, is divided by the voltage dividing resistor 65 in FIG. 4, and is applied to the gate 67.

Then, by driving 1 gate 67, tri-state gate 5
It is input as the input signal of No. 3.

This completes the task in FIG. 7, and returns to the first block in block 719.

When starting this task next time, the manual signal for address data will be input to the tri-state gate 53, so
In block 703, input data can be read simply by reading the address of tristate gate 53. This read data is then RA'd in block 705.
M3 (see Figure 3) at a location associated with the current address data.

In block 707, 1 is added to the address data in order to output the next address, but block 707 checks whether the added result is greater than the number of output blocks of 8.
9, and if it is larger, the address has ended up to the final address, so the process advances to block 711 and the address data is set to 0 to return to the beginning. To explain more specifically, the address data in FIG.
When the order of bO is 111 (7 in decimal system), the signals from the output terminal Y7 of the decoder 85 and the output terminal Y3j of the decoder 87 are output, and one of the addresses of each control terminal equipment group is output. final address data. At this time, when the address signal is +1 in block 707, it becomes 1000 (10
It becomes 8) in base system. When this 1000 is detected in block 709, this data is set to oooo in block 711. With this address data, the output terminal YO error signal of the decoders 85 and 87 is output, so it becomes the first address of the control terminal equipment group. Thereafter, the process proceeds to blocks 713 to 719 described above.

FIG. 9 is a time chart showing the chronological progress of the above tasks. The 10m8 task that is executed with the first priority is executed once every %10m8.

Signals are sent and received between the car control terminal equipment 23, 25 and the microcomputer 7 for each toms. When the lOmB task is finished, the 40m5 task is executed, but even during this execution, the 10m5 task is executed 4 times at intervals of 10m5.
Executed by interrupting the processing of the 0m5 task. This 40m
When the 8 tasks are completed, the punk ground task is executed until the next 40m5 task is executed, and processes such as performing calculations that take time in advance are performed.

In this way, 10m5 tasks are executed once every 10mS, but in order to update all the data of FF83 in FIG. 5, %iomsxs=s.

It takes m3 of time. Also, tristate gate 91
In order to input all the inputs into the microcontroller 7, 10
It takes mSX4=40mS.

To explain how this time affects elevator control, for example, when a passenger in the car presses the destination button
If you press , the information is taken into the microcomputer 7 after a time of 40 m5 in the worst case, as described in 1. Also,
After that, it is processed in a 40 mS task and the result is output, but in the worst case it takes soms time to do so, so the response light 25 will be turned on after a total of 160 m5. During this time, passengers are anxious because the elevator does not respond even though they press the destination button 23. It is generally said that this time is allowed as long as it is within a minimum of 100m5, but
160m5 takes too much time. However, the reason for taking such a long time is to make it possible to manufacture the transmission device at a cost commensurate with the reduction in the number of tail cords 11, as described above. In other words, malfunctions caused by noise can be prevented by using inexpensive resistors, and by performing a 10mS task once every 10mS, the elevator can be controlled without increasing the load factor of Mico/7. This is □ in order to be able to perform transmission control by oneself.

Therefore, in the present invention, the following means are provided in order to ensure that there is no problem even at low speed transmission times. That is, the destination button 23 in the car is provided with an immediate response function. Specifically, in FIG. 5, the destination button 23 and the response light 25 are connected, so that when the passenger presses the destination button 23, the response light 25 lights up at the same time. By doing this, the microcomputer 7 (
(see FIG. 3), a lighting signal is sent to the FF 83 within 160 m3, and thereafter the response lamp 25 is lit by this lighting signal. The time from when the destination button 23 is pressed and the response light 25 turns off until it is turned on again by the above-mentioned lighting signal is very short, less than 160m8, so passengers are not aware that the light has been turned off at this time. It is difficult and does not cause any problems.

In addition, as another embodiment of the instant response function, instead of connecting the destination button 23 and the response light 25 to the fist, the operation of the destination button/23 is converted into a signal by the gate 99, and after 'fc,
This signal is given to 5CR93 via the OR circuit and 80R
93 may be ignited, and the effect will be the same.

Furthermore, once converted into a signal by the gate 99, it is input to the one-shot circuit before entering the OR circuit, and the one-shot circuit's one-shot time is set to the above delay time of 160 m.
5, and even if the destination button 23 is pressed momentarily, the response light 25 may be turned on for that time.

In this way, the response light 25 can be prevented from going out before being turned on by the lighting signal from the F'F83.

In the above explanation, the destination button 23 in the car and its response light 25 have been explained as the control terminal equipment, but it goes without saying that the same can be done for the car position indicator light.

As explained above, according to the present invention, even if the signal transmission speed is slow, the delay time due to this delay can be prevented from becoming a problem in terms of control.

[Brief explanation of drawings]

1 and 2 are block diagrams of a conventional elevator control device, FIG. 3 is a block diagram showing an embodiment of the elevator control device of the present invention, and FIG. 4 is an implementation of the interface adapter shown in FIG. 3. Detailed block diagram showing an example, FIG.
A detailed block diagram showing an embodiment of the signal decoding device shown in the figure, FIGS. 6 and 7 are flowcharts showing an embodiment of the processing program in the microcomputer shown in FIG. 3, and FIG. 8 is a data structure explanatory diagram. FIG. 9 is a time chart showing the temporal progress of tasks. l...MPU, 3...RAM%5...ItOM,
7... Microcomputer, 11... Tail code, 23...
- Destination button, 25... Response light, 41... Interface adapter, 43... Signal decoding device, 51...
・FF, 53... Tri-state gate, 55...
Address decoder, 57...AND gate, 83.
FF, 85.87 Decoder, 89 Delay circuit, 91 Tri-state gate, 93 S
CR, 9s...Voltage dividing resistance, 97°99.101...
Gate. Figure 1 5 Figure 7

Claims (1)

[Scope of Claims] 1. A control device main body that controls the elevator provided in the elevator machine room and an auxiliary control device provided in the car are connected via a tail cord, and an output signal from the control device main body is connected to the elevator control device main body that controls the elevator. The auxiliary control device decodes the data, and the decoded result operates a specified control terminal device installed in the car, and the input signal from the control terminal device is used to control the auxiliary control device. and the control device main body controls the elevator based on the transmission and reception of the respective signals, when the auxiliary control device receives an input signal from the control terminal device. ,
means for outputting an output signal from the auxiliary control device to the specified control terminal device for a predetermined period of time before receiving an output signal corresponding to the input signal from the control device main body, and immediately An elevator control device characterized by having a configuration with enhanced response function. 2. The elevator according to claim 1, wherein the control terminal device that outputs the input signal is a destination button provided on the car, and the specified control terminal device is a response light corresponding to the destination button. Control device.