JPS5851618A - Gate circuit for gate turn-off thyristor - Google Patents

Gate circuit for gate turn-off thyristor

Info

Publication number
JPS5851618A
JPS5851618A JP56149535A JP14953581A JPS5851618A JP S5851618 A JPS5851618 A JP S5851618A JP 56149535 A JP56149535 A JP 56149535A JP 14953581 A JP14953581 A JP 14953581A JP S5851618 A JPS5851618 A JP S5851618A
Authority
JP
Japan
Prior art keywords
gate
current
circuit
thyristor
period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56149535A
Other languages
Japanese (ja)
Inventor
Mitsusachi Motobe
本部 光幸
Takao Kishi
岸 隆雄
Katsunori Suzuki
鈴木 勝徳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56149535A priority Critical patent/JPS5851618A/en
Publication of JPS5851618A publication Critical patent/JPS5851618A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/72Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region
    • H03K17/722Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region with galvanic isolation between the control circuit and the output circuit
    • H03K17/723Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region with galvanic isolation between the control circuit and the output circuit using transformer coupling

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Power Conversion In General (AREA)
  • Thyristor Switches And Gates (AREA)

Abstract

PURPOSE:To reduce gate losses remarkably and to make the circuit constitution small in size, by splitting a switching circuit controlling a gate current of a gate turn-off thyristor into that for off-period and for tail-period. CONSTITUTION:A switching SW circuit controlling a gate current of a gate turn-off thyristor GT01 is constiuted with an SW element 4 for off-period, an SW element 7 for tail period, and a resistor 8 in parallel. The element 4 is turned on with signal (b) from a control circuit 5, a signal (c) turns on the element 7, a collector current (d) of the element 4 flows and an off-gate current (f) is applied to a GT01 via a pulse transformer 3. When the GT01 turns off and the element 4 is turned off, a collector current (e) of the element 7 flows, the gate current (f) is limited at the resistor 8, and since the gate current for the compensation of a tail current Itail only flows, a gate loss (h) is remarkably reduced, the elements 4, 7 can be made small in size and the circuit constitution can be made small in size.

Description

【発明の詳細な説明】 本発明は、ゲートターンオフサイリスタにオフゲート電
流を供給するゲート回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gate circuit that supplies an off-gate current to a gate turn-off thyristor.

第1図に従来用いられているこの種のゲート回路の一例
を示す。同図において、1はゲートターンオフサイリス
タ(以下GTOと略記する)、2はGTOIにオフゲー
ト直流を供給するオフ用電源、3は電源2からの直流を
増刷してGTOIへ伝送するだめのパルストランス、4
はオフゲート直流の供給を制御するためのトランジスタ
からなるスイッチング素子、5はスイッチング素子4の
開閉を制御する。6す御回路、6はスイッチング素子4
をオフしたときにパルストランス3に発生するエネルギ
ーを還流させるだめのダイオードを示す。
FIG. 1 shows an example of this type of gate circuit conventionally used. In the figure, 1 is a gate turn-off thyristor (hereinafter abbreviated as GTO), 2 is an off power supply that supplies off-gate DC to the GTOI, 3 is a pulse transformer that reprints the DC from the power supply 2 and transmits it to the GTOI, 4
5 is a switching element made of a transistor for controlling the supply of off-gate direct current; 5 is a switching element for controlling opening and closing of the switching element 4; 6 control circuit, 6 is switching element 4
This shows a diode that circulates the energy generated in the pulse transformer 3 when the pulse transformer 3 is turned off.

次に、上記4或を有するゲート回路の動作を第2図に示
す波形図を用いて説明する。同図において、(a)はG
TOIのアノード電圧、(b)ハア、、+−トカソード
ilJ’J 電圧、(C)はゲート電流(d)はゲート
カソード間電圧、(e)はゲート損失、(f)は制御素
子5から出力されるスイッチング素子4の制御信号をそ
れぞれ示している。
Next, the operation of the gate circuit having the above-mentioned circuit 4 will be explained using the waveform diagram shown in FIG. In the same figure, (a) is G
TOI anode voltage, (b) Ha,,+-tocathode ilJ'J voltage, (C) gate current, (d) gate-cathode voltage, (e) gate loss, (f) output from control element 5. The control signals of the switching elements 4 are shown respectively.

第2図−において、(f)に示す制御信号によりスイッ
チング素子4をオンさせると、(C)に示すように電源
2からパルストランス3を介してGTOIへオフゲート
電流が流れる。(a)に示すターンオフ期間toffが
過ぎると、GTOIはオフし、(b)に示すようにアノ
ードカソード間電圧が上昇して来る。
In FIG. 2-, when the switching element 4 is turned on by the control signal shown in (f), an off-gate current flows from the power supply 2 to the GTOI via the pulse transformer 3, as shown in (C). When the turn-off period toff shown in (a) has passed, the GTOI is turned off, and the voltage between the anode and cathode increases as shown in (b).

この期間、即ちテイル期間t、出には、GTOIにティ
ルミ流Itanが流れ、再点弧するおそれがある。そこ
で、これを防止するために、このテイル亀流Ita+ 
1をゲート回路で吸収する必要があり、このために、ス
イッチング素子4は、(f)に示すようにテイル期間t
tallを含めてオンさせておかなければならない。他
方、GTOlのオフゲート電流の立上りを急峻にするた
めに、パルストランス302次側(’GTolのゲート
側)の電圧はGTOIのアバランシェ電圧より高くしで
ある。
At the beginning of this period, that is, the tail period t, the Tilmi flow Itan flows through the GTOI, and there is a risk of re-ignition. Therefore, in order to prevent this, this tail turtle style Ita+
1 must be absorbed by the gate circuit, and for this purpose, the switching element 4 has a tail period t as shown in (f).
You must turn it on, including tall. On the other hand, in order to make the rise of the off-gate current of GTol steep, the voltage on the secondary side of the pulse transformer 30 (gate side of GTol) is set higher than the avalanche voltage of GTOI.

このため、(d)に従するようにGTOIがオフしてゲ
ートカソード間の接合が回復して来るに従い、アバラン
シェ電流が流れる。この結果、ゲート損失は(e)に示
すようにテイル期間jtillで非常に大きくなる。ま
た、ゲート損失が大きくなるに従って、オフ電源2およ
びスイッチング素子4も容量の大きいものが必要となる
。このため1回路が全体として大型になるという欠点が
生じている。
Therefore, as shown in (d), as the GTOI is turned off and the junction between the gate and cathode is restored, an avalanche current flows. As a result, the gate loss becomes extremely large during the tail period jtill, as shown in (e). Furthermore, as the gate loss increases, the off-power supply 2 and the switching element 4 also need to have a large capacity. This results in a disadvantage that one circuit becomes large as a whole.

本発明の目的は、ゲート電流を制御するスイッチング回
路をオフ期間用とテイル期間用とに分割することによシ
、ゲート損失を大きくすることなしにティルミ流を吸収
することが可能なGTOのゲート回路を提供することに
ある。   ′本発明は、スイッチング回路をオフ期間
のゲート電流制御用とテイル期間のゲート電流制御用の
2種類のスイッチング素子により構成し、かつ後者に抵
抗を直列に接続したものである。
An object of the present invention is to provide a gate of a GTO that can absorb Tilmi current without increasing gate loss by dividing a switching circuit that controls the gate current into an off period and a tail period. The purpose is to provide circuits. 'In the present invention, a switching circuit is constituted by two types of switching elements, one for gate current control in the off period and the other for gate current control in the tail period, and a resistor is connected in series with the latter.

以下、実施例を用いて本発明の詳細な説明する。Hereinafter, the present invention will be explained in detail using Examples.

第3図は1本発明の一実施例を示す回路図であり、第1
図と同一部分は同一記号を用いてその詳細説明を省略す
る。第3図において、スイッチング素子4に並列にスイ
ッチング素子7と抵抗器8との直列回路が接続しである
。このスイッチング素子7の開閉は、スイッチング素子
4と同様、制御回路5によって制御される。
FIG. 3 is a circuit diagram showing one embodiment of the present invention.
The same parts as in the figures are given the same symbols, and detailed explanation thereof will be omitted. In FIG. 3, a series circuit of a switching element 7 and a resistor 8 is connected in parallel to the switching element 4. The opening and closing of this switching element 7 is controlled by a control circuit 5, similarly to the switching element 4.

、  次に、上記構成を有するゲート回路の動作を。, Next, the operation of the gate circuit having the above configuration will be explained.

第4図に示す波形図を用いて説明する。第4図において
、(a)はGTOIのアノード電流、(b)はスイッチ
ング素子4の°制御信号、(C)はスイッチング素子7
の制御信号、(d)はスイッチング素子′4のコレクタ
電流、(e)はスイッチング素子7のコレクタ電流、(
f)はゲートを流、(g)はゲートカソード間電圧、(
h)はゲート損失をそれぞれ示している。
This will be explained using the waveform diagram shown in FIG. In FIG. 4, (a) is the anode current of the GTOI, (b) is the degree control signal of the switching element 4, and (C) is the switching element 7.
control signal, (d) is the collector current of switching element '4, (e) is the collector current of switching element 7, (
f) is the current flowing through the gate, (g) is the gate-cathode voltage, (
h) shows the gate loss, respectively.

第4図において、 L)、 (C)に示す制御信号によ
りスイッチング素子4,7をオンさせると、(d)に示
すように、スイッチング素子のコレクタ電流が流れ、パ
ルストランス3を介して(f)に示すようなオフゲート
電流がGTOIに供給される。GTOIがオフした時点
で、スイッチング素子4をオフすると、その時から(e
)に示すようにスイッチング素子7のコレクタ電流が流
れ、ゲート電流はスイッチング素子7を通して流れる。
In FIG. 4, when the switching elements 4 and 7 are turned on by the control signals shown in L) and (C), the collector current of the switching elements flows as shown in (d), and the voltage (f ) is supplied to the GTOI. When the switching element 4 is turned off at the moment when the GTOI is turned off, (e
), the collector current of the switching element 7 flows, and the gate current flows through the switching element 7.

この時、スイッチング素子7には抵抗器8が接続されて
いるため。
At this time, the resistor 8 is connected to the switching element 7.

流れるゲートia流の直は(f)に示すように制限され
る。この場合、抵抗器8の抵抗器は、スイッチング素子
7を通して流れるゲート電流がティルミ流:lauを補
償できる匝となるように設定しておく。
The directivity of the flowing gate ia flow is limited as shown in (f). In this case, the resistor 8 is set so that the gate current flowing through the switching element 7 can compensate for the Tilmi current: lau.

スイッチング素子70オン期間t2はスイッチング素子
4のオン期間1.の終了時からGTOIのテイル期間’
tallが終了するまでとする。
The on period t2 of the switching element 70 is the on period 1.2 of the switching element 4. The tail period of GTOI from the end of '
This is assumed to be until the "tall" is completed.

このように、GTOIがオフするまでは、スイッチング
素子4を通して当該GTOI′f:ターンオフさせるに
十分なオフゲート電流が供給されるが。
In this way, until the GTOI is turned off, an off-gate current sufficient to turn off the GTOI'f is supplied through the switching element 4.

GTOIがオフした後は、抵抗器8に制限Aれてテイル
醒流、Iaa++を補償、するだけのゲート電流しか流
れないため、Φ)に示すようにティル期間ttallに
おけるゲート損失を大福に低減することができる。
After the GTOI turns off, only enough gate current flows to compensate for the tail current Iaa++ due to the limit A in the resistor 8, so as shown in Φ), the gate loss during the till period ttall is greatly reduced. be able to.

第5図は1本発明の他の実施例を示す回路図であり、第
3図と同一部分は同一記号を用い、てそのIOA説明を
省略する。即ち1本実施例はGTOIのゲート電流を、
第3図のパルストランス3を経由することなく、ゲート
at、源2から直接に供給するようにした例であシ、ス
イッチング素子4,7および抵抗器8.ならびに制御回
路5の各作用は前述した第3図の回路の場合と同・庫で
ある。
FIG. 5 is a circuit diagram showing another embodiment of the present invention, and the same parts as in FIG. 3 are denoted by the same symbols, and the explanation of the IOA is omitted. That is, in this embodiment, the gate current of GTOI is
This is an example in which the gate at and the source 2 are directly supplied without passing through the pulse transformer 3 shown in FIG. The functions of the control circuit 5 are the same as those of the circuit shown in FIG. 3 described above.

以上説明したように、本発明によれば、GTOのテイル
期間にゲートに流れる電流を必要最小限に抑制すること
ができるため、GTOのゲート損失を大幅に低減するこ
とができ、回路構成を小型化し得るという憂れた効果を
有する。
As explained above, according to the present invention, the current flowing through the gate of the GTO during the tail period can be suppressed to the necessary minimum, so the gate loss of the GTO can be significantly reduced, and the circuit configuration can be made smaller. It has the worrying effect of being able to become

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のGTOのゲート回路の一例を示す回路図
、第2図はその動作を説明す石波形図。 第3図は本発明の一実施例を示す回路図、第4図(a)
ないしくh)はその動作を説明する波形図、第5図は本
発明の他の実施例を示す回路図である。 1・・・ゲートターンオフサイリスタ、2・・・オフゲ
ー燦1図 劣2図
FIG. 1 is a circuit diagram showing an example of a conventional GTO gate circuit, and FIG. 2 is a waveform diagram illustrating its operation. FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. 4(a)
to h) are waveform diagrams illustrating the operation thereof, and FIG. 5 is a circuit diagram showing another embodiment of the present invention. 1...Gate turn-off thyristor, 2...Off game 1 figure inferior 2 figure

Claims (1)

【特許請求の範囲】 1、ゲートターンオフサイリスタにゲート電流を供給す
るオフ用ゲートd源と、このゲート電流の供給を制御す
るスイッチング回路とからなるゲートターンオフサイリ
スタのゲート回路において。 前記スイッチソゲ回路は、オフゲート電流の供給を制限
するだめの第1のスイッチング素子と、これに並列に接
続し、ゲートターンオフサイリスタがオフした後のテイ
ル期間にティルミ流を供給するための第2のスイッチン
グ素子およびこれに直列に接続した抵抗とを具備するこ
とを特徴とするゲートターンオフサイリスタのゲート回
路。
[Scope of Claims] 1. In a gate circuit for a gate turn-off thyristor, which comprises a gate d source for off, which supplies a gate current to the gate turn-off thyristor, and a switching circuit, which controls the supply of this gate current. The switch-over circuit includes a first switching element for limiting the supply of off-gate current, and a second switching element connected in parallel with the first switching element for limiting the supply of off-gate current, and for supplying a Tilmi current during the tail period after the gate turn-off thyristor is turned off. 1. A gate circuit for a gate turn-off thyristor, comprising an element and a resistor connected in series with the element.
JP56149535A 1981-09-24 1981-09-24 Gate circuit for gate turn-off thyristor Pending JPS5851618A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56149535A JPS5851618A (en) 1981-09-24 1981-09-24 Gate circuit for gate turn-off thyristor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56149535A JPS5851618A (en) 1981-09-24 1981-09-24 Gate circuit for gate turn-off thyristor

Publications (1)

Publication Number Publication Date
JPS5851618A true JPS5851618A (en) 1983-03-26

Family

ID=15477257

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56149535A Pending JPS5851618A (en) 1981-09-24 1981-09-24 Gate circuit for gate turn-off thyristor

Country Status (1)

Country Link
JP (1) JPS5851618A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4752705A (en) * 1985-12-16 1988-06-21 Kabushiki Kaisha Toshiba Off-gate circuit for a GTO thyristor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5530238A (en) * 1978-08-24 1980-03-04 Toshiba Corp Gate driver for gate turn-off thyristor
JPS5674083A (en) * 1979-11-20 1981-06-19 Fuji Electric Co Ltd Driving circuit for gate of gate turn-off thyristor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5530238A (en) * 1978-08-24 1980-03-04 Toshiba Corp Gate driver for gate turn-off thyristor
JPS5674083A (en) * 1979-11-20 1981-06-19 Fuji Electric Co Ltd Driving circuit for gate of gate turn-off thyristor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4752705A (en) * 1985-12-16 1988-06-21 Kabushiki Kaisha Toshiba Off-gate circuit for a GTO thyristor

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