JPS5851563A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5851563A JPS5851563A JP14943581A JP14943581A JPS5851563A JP S5851563 A JPS5851563 A JP S5851563A JP 14943581 A JP14943581 A JP 14943581A JP 14943581 A JP14943581 A JP 14943581A JP S5851563 A JPS5851563 A JP S5851563A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- film
- base
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims 4
- 230000000694 effects Effects 0.000 abstract description 3
- 230000003321 amplification Effects 0.000 abstract description 2
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 2
- 230000001590 oxidative effect Effects 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 3
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 238000000034 method Methods 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造法に関し、主としてアイソプ
レーナ方式によるバイポーラＩＣを対象とする。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and is primarily directed to isoplanar bipolar ICs.
バイポーラトランジスタにおいて、電流増幅率ｈＦＫを
高くするためにはぺ〜スーを小さくかつ不純物濃度を低
くする必要があり、一方、ベース抵抗効果の影響を少な
くするためにはベースコンタクト部の濃度を高くしなけ
ればならないため、第１図に示すようなＮ″″エピタキ
シャルＳｉ基体１ノ表面の一部に高濃度のＰ＋ベース（
コンタクト）領域２と、この領域２にＩすれた低濃度の
Ｐ−真性ベース領域３と、領域３の表面にＮ＋エミッタ
領域４を有するＮＰＮ）ランジスタが提案されている。In a bipolar transistor, in order to increase the current amplification factor hFK, it is necessary to reduce P~S and lower the impurity concentration.On the other hand, in order to reduce the influence of the base resistance effect, it is necessary to increase the concentration in the base contact part. Therefore, a high concentration of P+ base (
An NPN transistor is proposed having a contact region 2, a lightly doped P- intrinsic base region 3 in contact with this region 2, and an N+ emitter region 4 on the surface of the region 3.
このようなトランジスタを通常のプロセスにより実施す
る場合、Ｎ−基体１表面にＰ−ベース領域３を形成した
後、Ｐ＋ベース領域２とＮ＋エミッタ領域４とを個別の
マスク工程を経て形成するため、マスクずれでＰ＋ベー
ス２とＮ＋エミッタ３が一部で重なり合い、実効的にｈ
ＦＥが低下するのみならず、集積度が上がらないという
欠点がある。When such a transistor is implemented using a normal process, after forming the P- base region 3 on the surface of the N- substrate 1, the P+ base region 2 and the N+ emitter region 4 are formed through separate mask steps. Due to mask shift, P+ base 2 and N+ emitter 3 partially overlap, effectively causing h
This has the disadvantage that not only the FE decreases, but also the degree of integration does not increase.
本発明は上記の問題を解決すべくなされたものであり、
その目的とするところは、高ｈ 化、高Ｆ！
ｉ１１化かつ小脂化したトフンジスタの実現にある。The present invention has been made to solve the above problems,
The purpose is to increase H and F! The aim is to realize a Tofunjista that is i11 and has a small fat content.
第２図（副〜（ｅｌは本発明をバイポーラＮＰＮ）ラン
ジスタのベース・エミッタプロセスに適用した実施例を
示し、以下各図に対応する工程に従って詳細に説明する
。FIG. 2 shows an embodiment in which the present invention is applied to a base-emitter process of a bipolar NPN transistor, and will be described in detail below according to the steps corresponding to each figure.
＋ａ＋ ａｔ濃度Ｐ−１１１８ｉ基板５表面に選択拡
散した高濃度Ｎ＋＋込層６を形成した上に低濃度Ｎ−型
エビタキシャルＳｉ層１を形成した基体を用意し、表面
の一部に生成した酸化膜（Ｓｉｎ、）７をマスクとして
低濃度のベース拡散（Ｂイオン打込み）を行ないＰ一層
３を形成する。このＰ一層３は不純物濃度Ｎ ： １
Ｇ”〜” ａｔｏｍｓ／ｓ” 程度とし、拡散深さｄ：
ｏ、５〜１．０μｍ程度とする。Ｐ一層の表面には薄い
８ｉＱ、膜８が生成される。A substrate is prepared in which a low concentration N- type epitaxial Si layer 1 is formed on a selectively diffused high concentration N++-containing layer 6 on the surface of a +a+ at concentration P-1118i substrate 5, and the oxidation generated on a part of the surface is A low concentration base diffusion (B ion implantation) is performed using the film (Sin, ) 7 as a mask to form a P layer 3. This P layer 3 has an impurity concentration N: 1
G"~"atoms/s", diffusion depth d:
o, about 5 to 1.0 μm. A thin 8iQ film 8 is formed on the surface of the single P layer.
ｔｂ＋ 全面に８ｉの窒化物（８ｉ、Ｎ、）膜９を形
成しり後ホトレジスト処理によりエミッタにあたる部分
の８ｉ、Ｎ４ｇ％のみを残してそれ以外のＳｉ、Ｎ４を
エッチ除去する。tb+ After forming an 8i nitride (8i, N,) film 9 on the entire surface, a photoresist process is performed to leave only 8i and 4g% of N4 in the portion corresponding to the emitter, and remove the remaining Si and N4.
（ｃｌ ８ｉ、Ｎ、膜９と周囲の厚いＳｌへ膜７をマ
スクとして高濃度のＢ（ボロン）デボジシ曹ンを行ない
酸化雰囲気中で拡散を行なうことにより、ベースコンタ
クト部となるＰ＋層２を約０．５μｍの深さに形成する
とともにＰ＋層層表表面８ｉ０．膜１０を厚く生成する
。(Cl 8i, N, B (boron) is deposited at a high concentration onto the film 9 and the surrounding thick Sl using the film 7 as a mask and diffused in an oxidizing atmosphere to form the P+ layer 2 which will become the base contact part. The P+ layer is formed to a depth of about 0.5 μm and a thick P+ layer surface 8i0. film 10 is formed.
（ｄｉ ８１ｓ ｈ＋膜マスク９を熱リン酸エッチ液
等により除去し、そのあとＰ（リン）又はＡｓ（ヒ、３
Ｉ）を高濃度にデボジシ画ン又はイオン打込みにより導
入し、エミッタとなるＮ＋層４を約０．２〜０゜５μｍ
の探さに形成する。この工程で８ｉ、Ｎ、膜下の薄い８
ｉＱ、膜８とＰ＋層表面の厚い８ｉ０．膜１０の膜厚差
を利用することにより自己整合的にＮ＋層４を形成する
ことができる。(di 81s h+ film mask 9 is removed using hot phosphoric acid etchant, etc., and then P (phosphorus) or As (hi, 3
I) is introduced at a high concentration by deposition or ion implantation, and the N+ layer 4, which will become an emitter, has a thickness of about 0.2 to 0.5 μm.
Form in search of. In this process, 8i, N, thin 8 under the film
iQ, thick 8i0. of film 8 and P+ layer surface. By utilizing the difference in film thickness of the film 10, the N+ layer 4 can be formed in a self-aligned manner.
ｌｅｌ Ｐ＋ベース、Ｎ＋エミッタ表面の８ｉ０．膜
８゜１０の一部をコンタクトホトエッチにより室間し、
λ１（アルミニウム）を蒸着し、ホトエッチすることに
よりベース人！電極Ｂ及びエミッタ人！電極ＥｒｔＷｅ
或する。なお、コレクタ拡散はベース・エミッタと別工
程により行ない捺い高濃度Ｎ＋層（図示されない）を形
成する。 −
以上実施例で述べた本発明によれば下記の理由で前記発
明の目的を達成できる。el P+ base, N+ emitter surface 8i0. A part of the film 8゜10 is removed by contact photoetching,
Base by depositing λ1 (aluminum) and photoetching! Electrode B and emitter! Electrode ErtWe
There is. Note that the collector diffusion is performed in a separate process from the base/emitter process, and a high concentration N+ layer (not shown) is formed. - According to the present invention described in the embodiments above, the object of the invention can be achieved for the following reasons.
（１） Ｎ＋エミッタ層の直下には低濃度のＰ−ベー
ス層が形成されており、ｈ□を高くすることができる。(1) A low concentration P− base layer is formed directly under the N+ emitter layer, so that h□ can be increased.
（２）ベース層はコンタクトとなるＰ＋層により抵抗効
果を低減し高速化できる。(2) The base layer can reduce the resistance effect and increase the speed by using the P+ layer which serves as a contact.
（３１Ｎ＋工ミツタ層はＰ＋層に対し自己整合的に形成
されるため両者のオーバーラツプは最小限におさえられ
高集積化が可能となる。(Since the 31N+ semiconductor layer is formed in self-alignment with the P+ layer, the overlap between the two is kept to a minimum and high integration is possible.
（４）精度を唸要とするホトレジスト工程はエミッタ上
の８ｉ、Ｎ、膜マスク形成時のみであってプロセスが簡
Ｊｌ、化されコスト的に有利である。(4) The photoresist process, which requires precision, is only performed when forming the 8i, N, film mask on the emitter, which simplifies the process and is advantageous in terms of cost.
本発明はアイソプレーナ方式によるバイポーラＩＣの全
ての場合に適用できる。The present invention is applicable to all cases of isoplanar bipolar ICs.
第１図は高ｈ□用ＮＰＮ ）ランジスタのベース・エミ
ッタ構造を示す断面図、第２図ｉ１１〜（・ｌは本発明
によるＮＰＮ ）ランジスタプロセスのベース・エミッ
タ部分の工程断面図である。
１・・・Ｎ″″エピタキシャル８ｉ層Ｃ基Ｋ）、２・・
・Ｐ＋ベースコンタクト領域、３・・・Ｐ−ぺ−Ｘ領域
、４・・・Ｎ＋エミッタ領域、５・・・ｐ−８ｉ、基板
、６・・・Ｎ＋鳳込層、７・・・８ｉＱ、膜、８・・・
薄いＳｔＯ，膜、９・・・８６Ｎ４膜、１０・・・８ｉ
０＊膜。
ｊ
第２図
第２図FIG. 1 is a cross-sectional view showing the base-emitter structure of a high h□ NPN transistor, and FIG. 2 is a process cross-sectional view of the base-emitter portion of the NPN transistor process i11 to (.l is according to the present invention). 1...N''''Epitaxial 8i layer C base K), 2...
・P+ base contact region, 3...P-P-X region, 4...N+ emitter region, 5...p-8i, substrate, 6...N+ embedding layer, 7...8iQ, Membrane, 8...
Thin StO, film, 9...86N4 film, 10...8i
0*membrane. j Figure 2Figure 2
Claims (1)
電型領域と、この第１導電型領域に接し、かつこの領域
に１まれた高不純物濃度第２導電型領域を形成するにあ
たって、上記基板表面の一部に形成した第１の半導体酸
化膜をマスクとして低不純物濃度第１導電型領域を形成
し、この第１導電型領域の表面の一部に薄い第２の酸化
膜を介して耐酸化性物質膜を形成し、第１の酸化膜と耐
酸化性物質膜を用いて低不純物濃度第１導電型領域の表
面に高不純物濃度第１導電型領域を選択的に形成すると
ともにこの高不純物濃度第１導電型領域表面に第３の酸
化膜を形成した後、耐酸化性物質膜を取り除き、第２の
酸化膜と第３の酸化膜との膜厚の差を利用して第２の酸
化膜下の半導体領域に高不純物濃度第２導電型領域な形
成することを特徴とする半導体装置の製造法。1. Forming a highly impurity-concentrated first conductivity type region in a part of one main surface of a semiconductor substrate and a highly impurity-concentrated second conductivity type region in contact with and in contact with this first conductivity type region A first conductivity type region with a low impurity concentration is formed using the first semiconductor oxide film formed on a part of the surface of the substrate as a mask, and a thin second oxide film is formed on a part of the surface of the first conductivity type region. forming an oxidation-resistant material film through the oxidation-resistant material film, and selectively forming a high impurity concentration first conductivity type region on the surface of the low impurity concentration first conductivity type region using the first oxide film and the oxidation resistance material film. At the same time, after forming a third oxide film on the surface of this highly impurity-concentrated first conductivity type region, the oxidation-resistant material film is removed and the difference in film thickness between the second oxide film and the third oxide film is utilized. A method of manufacturing a semiconductor device, comprising: forming a highly impurity-concentrated second conductivity type region in a semiconductor region under a second oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14943581A JPS5851563A (en) | 1981-09-24 | 1981-09-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14943581A JPS5851563A (en) | 1981-09-24 | 1981-09-24 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5851563A true JPS5851563A (en) | 1983-03-26 |
Family
ID=15475045
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14943581A Pending JPS5851563A (en) | 1981-09-24 | 1981-09-24 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5851563A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6076165A (en) * | 1983-09-30 | 1985-04-30 | Nec Kansai Ltd | Transistor |
| JPS62245709A (en) * | 1986-04-17 | 1987-10-27 | Sanyo Electric Co Ltd | Differential amplifier circuit |
| JPS63233102A (en) * | 1987-03-19 | 1988-09-28 | 株式会社 中山製鋼所 | Water permeable paving block, its production and water permeable paving method using said block |
| JPH06207401A (en) * | 1993-01-08 | 1994-07-26 | Yabuhara Sangyo Kk | Surface pavement material of anti-fading property and water permearbility |
| JP2012023041A (en) * | 2011-07-29 | 2012-02-02 | Fujitsu Ltd | Mesh and element analysis method |
-
1981
- 1981-09-24 JP JP14943581A patent/JPS5851563A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6076165A (en) * | 1983-09-30 | 1985-04-30 | Nec Kansai Ltd | Transistor |
| JPS62245709A (en) * | 1986-04-17 | 1987-10-27 | Sanyo Electric Co Ltd | Differential amplifier circuit |
| JPS63233102A (en) * | 1987-03-19 | 1988-09-28 | 株式会社 中山製鋼所 | Water permeable paving block, its production and water permeable paving method using said block |
| JP2530645B2 (en) * | 1987-03-19 | 1996-09-04 | 株式会社 中山製鋼所 | Block for permeable pavement, method for producing the same and permeable pavement method using the same |
| JPH06207401A (en) * | 1993-01-08 | 1994-07-26 | Yabuhara Sangyo Kk | Surface pavement material of anti-fading property and water permearbility |
| JP2012023041A (en) * | 2011-07-29 | 2012-02-02 | Fujitsu Ltd | Mesh and element analysis method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6279666A (en) | Manufacture of bipolar semiconductor integrated circuit | |
| JPS62290173A (en) | Manufacture of semiconductor integrated circuit device | |
| JPS5851563A (en) | Manufacture of semiconductor device | |
| JPH02271566A (en) | Semiconductor device and its manufacture | |
| JP2511993B2 (en) | Method for manufacturing semiconductor device | |
| JP2626300B2 (en) | Method for manufacturing semiconductor device | |
| JPH0579186B2 (en) | ||
| JP3104335B2 (en) | Method for manufacturing semiconductor device | |
| JPS58212171A (en) | Semiconductor device | |
| JPS5678139A (en) | Manufacture of semiconductor integrated circuit | |
| JPS59961A (en) | Manufacture of semiconductor device | |
| JPS63199462A (en) | Manufacture of semiconductor device | |
| JPS6060759A (en) | Semiconductor device | |
| JPH0132669B2 (en) | ||
| JPH01225357A (en) | Semiconductor device | |
| JPH0785475B2 (en) | Method for manufacturing bipolar semiconductor integrated circuit device | |
| JPH02119258A (en) | Manufacture of semiconductor device | |
| JPS639150A (en) | Manufacture of semiconductor device | |
| JPH0239861B2 (en) | ||
| JPS60223160A (en) | Manufacture of bipolar transistor | |
| JPS6068646A (en) | Manufacture of semiconductor device | |
| JPH05152233A (en) | Manufacture of semiconductor device | |
| JPS60140759A (en) | Manufacture of semiconductor device | |
| JPS62144358A (en) | Manufacture of semiconductor device | |
| JPS60165757A (en) | Manufacture of semiconductor device |