JPS585081U - Character display control device - Google Patents
Character display control deviceInfo
- Publication number
- JPS585081U JPS585081U JP9685681U JP9685681U JPS585081U JP S585081 U JPS585081 U JP S585081U JP 9685681 U JP9685681 U JP 9685681U JP 9685681 U JP9685681 U JP 9685681U JP S585081 U JPS585081 U JP S585081U
- Authority
- JP
- Japan
- Prior art keywords
- character
- character display
- random access
- access memory
- control device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Dot-Matrix Printers And Others (AREA)
- Record Information Processing For Printing (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来例の処理方式の概念図、第２図は本考案の
実施例の構成を示すブロック図、第３図は第２図のＲＡ
Ｍ又はＲＯＭ３−１〜３−８の内容を示す図、第４図は
スキュード・アレイ方式を採用しない場合の文字ビット
情報がＲＡＭ４−Ｑ〜４−７に格納されている状況を示
す図、第５図はスキュードφアレイ方式で文字ビット情
報がＲＡＭ４−Ｑ〜４−７に格納されている状況を示す
図である。
図中１． ２． ９． １０はシック、３−１〜３−８
はＲＡＭ又はＲＯＭ、４−０〜４−７はＲＡＭ、ｆ３−
θ〜８−３はメモリ（ＲＡＭ）、ＡＤＲ８はアドレス情
報、ＲＡＭ、ＡＤＲ８はＲＡＭ３−１〜３−８のアドレ
ス情報θ〜７、Ｂ、ＡＤＲ３はＲＡＭ４−０〜４−７の
文字のブロックのアドレス、ＷＤはライト拳データ、Ｒ
Ｄはリード・データ、′臨〜ｂ７７は文字のビット情報
、０． １． ２． ３はモード情報を区別する番号、
ＭＯＤＥは読出しモード情報、１１−１〜１１−３は加
算回路である。
尺 尺 ＥＦ。Fig. 1 is a conceptual diagram of a conventional processing method, Fig. 2 is a block diagram showing the configuration of an embodiment of the present invention, and Fig. 3 is an RA of Fig. 2.
FIG. 4 is a diagram showing the contents of M or ROMs 3-1 to 3-8, and FIG. FIG. 5 is a diagram showing a situation in which character bit information is stored in RAMs 4-Q to 4-7 in the skewed φ array system. 1 in the figure. 2. 9. 10 is chic, 3-1 to 3-8
is RAM or ROM, 4-0 to 4-7 are RAM, f3-
θ~8-3 is memory (RAM), ADR8 is address information, RAM, ADR8 is address information of RAM3-1~3-8 θ~7, B, ADR3 is character block of RAM4-0~4-7. Address, WD is light fist data, R
D is read data, `--b77 is character bit information, 0. 1. 2. 3 is a number that distinguishes mode information,
MODE is read mode information, and 11-1 to 11-3 are adder circuits. Shaku shaku EF.
Claims (1)
示された文字コードに対応した文字表示情報を格納する
キャラクタ・ジェネレータから、上記指示された文字コ
ードに対応した文字表示情報を生成して文字表示を行な
う文字制御装置において、該キャラクタ・ジェネレータ
からの出力を第１のランダム拳アクセス・メモリ上にス
キューした状態で格納するよう再配列する第１のシフタ
、該第１のランダム拳アクセス・メモリ上にスキューし
た状態で格納された文字表示情報を文字表示モードに対
応して読出すアドレスを与へる第２のランダム・アクセ
ス・メモリ又は１ノード・オンリ・メモリ、上記のアド
レスで読出された文字情報を文字表示モードに対応して
再配列する第２のシフタ及び該第１のランダム・アクセ
ス・メモリより構成されることを特徴とする文字表示制
御装置。A character generator is equipped with a terminal device including a data processing device and a display device, and stores character display information corresponding to the specified character code, and generates character display information corresponding to the specified character code and displays the character. a first shifter for reordering output from the character generator to be stored in a skewed manner on a first random access memory; a second random access memory or one node only memory that provides an address for reading character display information stored in a skewed state according to the character display mode; a character read at the above address; A character display control device comprising: a second shifter that rearranges information in accordance with a character display mode; and the first random access memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9685681U JPS585081U (en) | 1981-06-30 | 1981-06-30 | Character display control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9685681U JPS585081U (en) | 1981-06-30 | 1981-06-30 | Character display control device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS585081U true JPS585081U (en) | 1983-01-13 |
Family
ID=29891683
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9685681U Pending JPS585081U (en) | 1981-06-30 | 1981-06-30 | Character display control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS585081U (en) |
-
1981
- 1981-06-30 JP JP9685681U patent/JPS585081U/en active Pending
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