JPS5850686A - Editing device of digital signal - Google Patents

Abstract

PURPOSE:To detect an accurate editing point and to realize the easy and accurate editing, by giving a fading process to the signal obtained by storing a reproduced signal and reading it out through a fading time setting means and detecting a specific address with the set value of said setting means. CONSTITUTION:The 1st and 2nd tapes are connected to terminals P and R respectively. The parts A and B of the tapes are reproduced and then dubbed in the digital form to the recording side through a terminal W to obtain the 2nd tape. Then parts C and D are reproduced, and D is recorded at the boundary between A and B. Here an editing point is detected. Then 2 of the 1st tape is fed to the terminal P to decide the boundary between C and D. The data is recorded cyclically to a memory 9. Then the memory 9 is read out, and an editing point retrieving mode is obtained at an operation input part 7. In the same way, the boundary between A and B of the 2nd tape is decided by the memory 12. Then the memories 12 and 9 are consecutively read out to perform a cross fading process.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal editing device that edits digital signals recorded and played back by a digital recording and playback device, and in particular, when fade processing is performed, editing points during fade time can be easily and accurately edited. The purpose of the present invention is to provide a digital signal editing device that can easily perform precise and high-quality editing.

Traditionally, when editing analog recorded tapes, the useful parts of the recorded tapes were manually cut and spliced.
They have been hand-cut and edited into book tapes. This situation is shown in FIG. In Fig. 1, 11 and 2/ are parts of the recorded tape, part A of 1' is a necessary part, part B is an unnecessary part, part 0 of 2' is an unnecessary part,
Part D is a necessary part. A desired tape 3' can be obtained by cutting these tapes and mechanically joining them together. At this time, tapes 1', 2
It is necessary to find the cutting position of ', that is, the boundaries between A and B and C and D (hereinafter referred to as editing points), but due to the snow, the following work was necessary.

That is, the tape recorder is put into a playback state, and while listening to the playback sound, the tape recorder is stopped at a position that appears to be an editing point.

In order to find a more accurate editing point, the take-up reel and the supply reel of the tape recorder are manually rotated forward and reverse in the same direction, and the editing point is determined by listening to the reproduced sound. In other words, by making such fine adjustments,
When it was determined that the tape was in the editing violet, the position of the tape that was in contact with the gap of the playback head was regarded as the main editing point, and the cutting was performed as shown in Figure 1. The reason why the tape is cut diagonally is to prevent the playback sound from becoming discontinuous at the editing point when the edited tape is played back. This is because the sound in the D section gradually becomes louder (fade-in), and the sound in the D section gradually becomes louder (fade-in).This connection process is called cross-fade.

Such editing work is indispensable when creating music tapes, etc., but difficult problems arise when applying ivC to digital i-sound playback devices that have been put into practical use in recent years. In other words, in a digital recording and reproducing apparatus, since the recorded signal is a digital signal, it is cut diagonally like an analog signal, and this has a negative effect on the reproduced sound. On the other hand, in order to reduce the amount of information lost as much as possible, even when cutting perpendicularly to the direction of failure, digital recording and playback devices usually use several dozen or so bits of information to store error/correction codes. Errors in the information in the 1PcjM frame cannot be avoided unless the 1PcjM frame is attached and recorded as 1PGM frame. Therefore, (a)
It is necessary to perform operations such as applying muting to that part, or (b) skipping that part and connecting the information before and after it, but in any case, the sound quality of the original information at that part will not deteriorate. This is essentially a problem.゛The present invention solves the above-mentioned conventional drawbacks, and when performing fade processing during editing, the digital signal is first stored in memory and then played back.1'''C% =
fi , , , , , 'L edit point etc. 0 desired 0 position 1 to.

To provide a digital signal editing device that allows editing work to be performed accurately and easily by notifying the user when an error occurs.

Hereinafter, one embodiment of the present invention will be described based on the drawings. First, an outline of the editing method of the digital signal editing device according to the present invention will be explained. In this method, the recorded tape is not cut mechanically, but two digital recording and playback devices are used. The first digital recording and playback device plays the first tape before editing, and the second digital A recording/playback device records only the necessary portions of the first tape onto a second tape to create one edited tape. This will be explained with reference to FIG. That is, in FIG. 2 (&), 1 and 2Fi
Part 1 of the first tape loaded in the first digital recording/playback device is played back, and the second digital recording/playback device plays part 1 of the first tape that passes the boundary between 1 and B and slightly enters the area of B. Record on the second tape installed. This situation is shown in FIG. 2(b).

Next, the first tape is played back from a distance Ll before the boundary between C and D in 2. At the same time, the second tape is played back from L2 before the boundary between M and B. Here, it is assumed that L1yL2, and this value is the value of the first field of A and B of the second tape at the moment when the playback head of the first digital recording and playback device comes into contact with the boundary between C and D of the first tape. It is sufficient that the length is sufficient to run the first tape and the second tape synchronously so that the recording heads of the two digital recording and reproducing apparatuses come into contact with each other. By running the first tape and the second tape synchronously in this manner, it is possible to record D on the first tape from the boundary between M and B on the second tape. This situation is shown in FIG. 2G. At this time, at the boundary between M and D, M is faded out and D is faded in depending on the digital voice quality.

These operations are performed using time codes recorded on separate tracks on the tape.

The present invention realizes a digital signal editing device based on the above-mentioned idea, and a detailed description of the embodiments will be given below. In FIG. 3, 4 is a CPU (microcomputer) that controls this device, sFi,
(ROM where the program of 3PU4 is stored, 6 is a data bus (the address bus is omitted in the diagram)
, 7 is an operation input section for giving control commands to this device; 7' is a control output section for outputting operation instructions or control signals for controlling other parts of this device; 8 is the above-mentioned 7; .7'lcP, an interface element for interfacing with U4. On the other hand, P and R are the first
and a digital signal input terminal from a second digital recording/reproducing device (hereinafter referred to as a PCM tape recorder). 9 is a memory for writing and storing digital data from the input terminal P, 1° is an address counter of the memory 9, 1
1 is an interface element that interfaces the address counter 10 and the CPU 4; 12 is a memory that similarly writes and stores digital data from the input terminal R; 13 is an address counter for the memory 12; and 14 is an interface between the address counter 13 and the CjUA usable interface. It is element. 15 and 15' are switches controlled by the output of the control output unit 7' from the CPU 4 via the interface element 8; 16 is the digital data from the first PCM tape recorder input from the input terminal P and the input terminal R; This is a cross-fade processing circuit for digitally calculating the digital data inputted from the 20th POM tape recorder or the output data of the memory 9 and the output data of the memory 12 to generate a cross-fade. 171'i interpolation circuit, which prevents the clock frequency from being mixed into the reproduced audio as noise when the memories 9 and 12 are reproduced at variable speeds and the memories are read at a clock frequency lower than the original sampling frequency. This is to prevent this. 18 is a D/MU converter, 19
is a low-pass filter, 2o is an amplifier, and 21Fi monitor speaker. W is an output terminal to the second PCM tape recorder (recording tape recorder).

22 is a clock pulse generation circuit, 23 is a manual clock pulse generator, and 24 is for selecting and outputting either the output of the clock pulse generation circuit 22 or the manual clock pulse generator 23 according to the output of the control output section 7'. It is a changeover switch. The Tp terminal is played back by the first PCM tape recorder connected to the P terminal.
The PU4 interface, the TR terminal, is played back by the second PCM tape recorder connected to the R terminal, fcsMpTx
The time record input terminal 26 is an interface between the time code input and the CPU 4. 27 is a means for detecting a specific address from the initial value of the address counter 13, the output address, and the set cross-fade time. It is.

Next, the operation of this embodiment will be explained based on FIG. 3 as well.

As a premise, the tape attached to the first PCM tape recorder connected to the P terminal is the first tape explained in Fig. 2, and the n-th "2nd P" (3M tape recorder is also The second tape is called a playback tape recorder and a recording tape recorder, respectively.

First, use the playback tape recorder to play back part 1 (parts M and B) of Figure 2e), pass through the cross-fade processing circuit 16, and dub the digital signal from the W terminal to the recording tape recorder. Then, make a second tape as shown in Figure 2. Next, play the 20 - part (c, n part) of Figure 2 (IL), and
D is recorded after performing cross-fade processing from the boundary of , but here the editing point, that is, M.

It is necessary to find the exact position of the boundary of B and the boundaries of C and D.

Next, the operation for determining the editing point will be explained.

First, in order to determine the boundary between C and D, part 2 of the first tape is played back by a tape recorder on the playback side and inputted to the P terminal. When PGM data is input to the P terminal, this data is cyclically recorded in the memory 9. In other words, once the writing to the last address in the memory 9 is completed, writing starts again from the first address.As a result, if we take a certain moment, the PGM data stored in the memory 9 will always last for a certain period of time from that moment. The previous data will be stored continuously. The address of this memory 9 is controlled by an address counter 1o. , the clock pulse of this counter 10 is the 11 of the switch 24.
By turning on -f, the clock pulse generation circuit 22
A clock 11 pulse generated from the clock is supplied. Furthermore, switch 1
6, b-c are ON, the input PCjM data passes through the cross-fade processing circuit 16 and the interpolation circuit 17, is converted to the original analog signal by the I)/mu converter 18, and is converted into a low-frequency signal. High-frequency components are cut by a filter 19, amplified by an amplifier 20, and supplied to a speaker 21, where the audio from the tape recorder on the playback side n1 is monitored.

Control of each of the above parts, for example, the polarity of switches 15 and 24,
All operations such as disabling the cross-fade processing circuit 16 and the interpolation circuit 17 are performed by signals from the control output section 7'. That is, signals from the operation input unit 7, which is composed of keyboard push buttons, etc., are transmitted to the interface element 8,
It is transmitted to the CPU 4 via the pass line 6, and a corresponding control signal is output from the CPU 4 via the pass line 6 and the interface element 8 from the control output section D, and the control is performed using this signal. In FIG. 3, control lines from the control output section 7' to other parts than the switches are omitted.

The editor inputs the output audio from the speaker 21 and the monitor number from the operation input section 7. This signal is passed through QPT via the above path.
J4, and the following control is performed via the control output section 7'. First, the editor continues the previous operation for a certain period of time from the editing point desired, and after a certain period of time, the memory 9
Stop writing to. Thereafter, tape running in the playback tape recorder is stopped. Tape recorder control 1-I
Although this is carried out in response to an instruction from the CPU 4, it is omitted from the diagram. Now, the contents of the memory 9 at this time are as shown in FIG. Here, the specifications are assumed as follows. Audio data Fi 1.6 bits/sample, sampling frequency 50, memory 256 kW (1W 216-bit)
In this way, the audio data stored in the memory 9 is approximately 6 seconds, which is 266/60 (5 seconds). Of course, in order to save memory, it is also possible to store every other sample in the memory (this means that the sampling frequency becomes a bar). Alternatively, we will not perform any processing that involves reducing the number of pits per sample using a bit compression method. In FIG. 4, a 256 kW memory is simulated, and audio data is sequentially written from left to right, and if it is written as 2FFFF1, it will be written again from 0oooO, and this process is repeated. The memory address corresponding to the timing desired by the editor is represented by p in the figure.

Then, writing is completed at a timing corresponding to the memory address Yp with a delay of, for example, 4 seconds within the repetition period as a fixed period of time. As a result, memory 9 stores (Yp+-
The audio is recorded in the order of 1)→2FFFF-00000-)YP.

Next, in order to search for one accurate edit point, the contents of the memory 9 are read out, and the editor can control each section by setting the device to edit point search mode from the operation input section 7. The signal will look like this: The switches a-C of the switch 16 are turned on, and the switches d-6 of the switch 24 are turned on.

Reference numeral 23 denotes a manual clock pulse generator composed of a rotary encoder or the like, which generates no pulses at all depending on the speed of movement. If a rotary dial, for example, is employed as the manual control means, the greater the rotation speed, the more pulses will be generated. This pulse and rotation direction information is sent to the address counter 1o.
If the counter is operated as an up/down counter, for example, when the counter is rotated clockwise, addresses are set in the forward direction, that is, in the order of (Yp+1)→2FFFF→0oOoO→Yp, and the contents of the memory are read out. This read PCM data passes through the cross-fade processing circuit 16, and is interpolated by the interpolation circuit 17.
It is converted into the original analog signal by the analog signal converter 18, and the high-frequency components are cut by the low-pass filter 19, and the signal is sent to the amplifier 2Q.
The sound is amplified and supplied to speaker 2, and the editor monitors the sound. The faster the rotary dial is rotated, the higher the frequency of the audio to be reproduced becomes.

When rotated counterclockwise, YP -0000-2
It is natural that the frequency of the reproduced sound changes depending on the rotational speed even when it is reproduced in the order of FFFF-(Yp + 1) and recorded as if it were a tape recorder. In the case of variable speed reproduction of the audio sampled and stored in 60 songs in this way, the following problems arise. That is, if playback is performed at a clock frequency of 50 songs or more, there is no particular problem, but if playback is performed at a frequency lower than 50 songs, for example, by 10 animals, 10 song components will occur at this clock frequency. However, low-pass filter 2
For example, the cutoff frequency of ° is 201&, which is the optimum value when the sampling frequency is 60 songs. Therefore, the above 101 & component is not removed by the low-pass filter 19 and is heard as noise. In order to solve this problem, the interpolation circuit 17 is operated.

Next, the function of the interpolation circuit 170 will be explained with reference to FIG. FIG. 6(a) shows the audio signal stored in the memo 1y being reproduced at normal speed, that is, 601t)h, and subjected to D/MU conversion. When the same signal is played back for 10 songs and subjected to b/mu conversion, the result is as shown in FIG. 6(b). Here, Fig. 6(a)
, S point in (b) indicates the same sample. The purpose of this circuit is to smoothly interpolate the discontinuous portions of these signals by 50k) as shown in FIG. 6(0).

First, the concept of interpolation will be explained. Figure 5(b)
, (C) is shown in FIG. 6. In FIG. 6, 31 is an input to the interpolation circuit. A and b are outputs read from the memory, and are sample values of numbers adjacent to each other in time. Too 'j'2o is the timing of the hand a clock pulse, and T2O is the timing one clock period after Too. 'l'1o, Ti
1°Ti2, Ts, Ti4. T2'(l li
This is the timing of the sampling clock pulse. 32
is the output of the interpolation circuit 17. t Too(n=o, 1
, 2+3'+4), the output L+n of the interpolation circuit 17 is determined as follows.

L+n=a+(b-t)-n'*k---
--- Yamauchi --- (1) K is a virtue number that is inversely proportional to the frequency of the output of the manual clock pulse generator 23. For example, in the case of Fig. 6, if n is simply determined, the manual clock pulse is generated. Since the output Fi10k)h of the device 23 and the sampling frequency are curved by 6 degrees, it is expressed as %. In equation (1), k=%
.

It can be seen that if n=o, 1, 2, 3.4, 32 interpolations shown in FIG. 6 can be performed. A block diagram for realizing the above functions is shown in FIG.

FIG. 7 shows a block diagram of the interpolation circuit 17. 52 is a 16-bit parallel signal input to the interpolation circuit; 53il'' is a terminal to which the output of the manual clock pulse generator 23 is input;
4 is the Sambli jig clock (50'kPa in this case)
) is an input terminal. 41 and 42 are launch circuits, 43 is a subtraction circuit that subtracts the output of the latch circuit 42 from the output of the latch circuit 41, 44 is an adder circuit, and 46 is a latch circuit that latches the output of the adder circuit 44 with a sampling clock. 46 is a reference clock pulse generation circuit (for example, 50k, which generates clock pulses of 5 kites). 47 is a counter that is reset by the output of the manual clock pulse generator Masuda and counts the output of the reference clock pulse generator 46, and 48 is a ROM, which takes the value of the output of the color/returner 47 as an address and corresponds to that address. A circuit that outputs the contents of the ROM to generate a slope coefficient k; 49 a circuit that multiplies the slope of the output of the latch circuit 46 and the output of the slope coefficient generation circuit 48; 50 a circuit that multiplies the output of the multiplier circuit 49 and the output of the latch circuit 42; An adder circuit 61 is a polarity determining circuit that latches the polarity bit of the output of the latch circuit 43 and determines the polarity of the multiplier circuit 49. 55 is the output of the interpolation circuit.

The outputs of the latch circuits 41 and 42 correspond to a and a in FIG. 6, respectively. The output Fi of the subtraction circuit 43 is ba in equation (1). Furthermore, an adder circuit 44 and a latch 46
The output (b − a) x n is obtained by the combination of . Since the frequency of the output of the reference clock pulse generation circuit 46 is 514h and the frequency of the output of the manual clock generator 23 is 10 songs, the output of the counter 47 is 500. At this time, k of the slope coefficient generating circuit 48 constituted by, for example, a ROM is assumed. As a result, the output of the multiplication circuit 49 is (b-a).n-k. Furthermore, the output of the adder circuit 60 is combined with the output 56 of the interpolation circuit as indicated by the dotted line 3 in FIG.
2 is obtained. Here, depending on the magnitude relationship between a and b, the polarity bit passes through the polarity determining circuit 61 and changes the sign bit of the multiplication circuit 49. In addition, in Fig. 7, (1
) The second term of equation (b-a) is configured to calculate xn first, but depending on the hardware, it may overflow at this stage, so if kXn is calculated first, That fear will disappear.

As described above, the output of the interpolation circuit 17 shown in FIG. 3 is obtained, and the sound reproduced at a variable speed through the speaker 21 via the D/MU converter 18, the low-pass filter 19, and the amplifier 20 can be monitored. At this time, if you turn the rotary dial in the forward or reverse direction, you will hear exactly the same playback sound as when you manually rotate the reel of a conventional analog tape recorder in the forward and reverse directions.

In this way, the rotary dial is stopped at the point to be edited, and a signal indicating that the point is the editing point is given to the CPU 4. This means that the position of the boundary between C and D in FIG. 2 has been determined. The following process is performed for the 1cPU4 to recognize this position. First, at the timing of the editing point given by the editor, the CPU 4 reads the time code input signal from the Tp terminal, which is input simultaneously with the PGM data, via the time code and hash line 6. In SMPTE time code, the minimum signal unit is a frame (1/30th of a second), so in order to increase the editing accuracy beyond this, it is necessary to count the audio sampling pulses within a frame, and However, in FIG. 3, this counter is omitted and is included in the time code interface 26, although the CPU 4 also needs to read the information. Therefore, at this point (jPU4 has hours, minutes, seconds, frames,
You will read sample information. Next, in the edit point search mode, manually: - The counter in the time code interface 26 operates together with the address counter 1o by the output of the clock pulse generator 23, and the time code information of the correct edit point corrected manually and in finer frame units are operated. The CPU 4 reads the sample point information within, that is, the hour, minute, second, frame, and sample information. In this way, icP'tT4 has information on the exact position of the sample point in the memory e and on the tape. The address in memory 9 of the edit point determined at this point is
MP.

Next, the boundaries of the second tape M and B in FIG. 2(b) are determined. Play back the recording side tape recorder and connect PGM to the R terminal.
Data is entered. This data is recorded cyclically in memory 12. At this time, the memory address counter 13,
Switch 5, switch 24, switch 16, crossfade processing circuit 16, interpolation circuit 17, D/M converter 18, low frequency filter, filter 9, amplifier 20. The operation of the speaker 21 is similar to that of the playback tape recorder, so a description thereof will be omitted. The editor monitors the output audio from the speaker 21 at the timing when he wants to edit, that is, when the second tape is
In the vicinity of the boundary, a signal to that effect is inputted from the operation input section 7 in the same manner as described above. After that, writing continues in the memory 12 for a certain period of time and then stops, which is the same for the case. However, in this case, if the capacity of the memory 12 is approximately 6 seconds as in the case of the memory 9, writing to the memory 12 is stopped when, for example, 1 second has elapsed from the specified point. The state inside the memory 12 at this time is shown in FIG. )IJI,
YR corresponds to Xp and Yp in FIG. 4, respectively. Furthermore, the operation of searching for the correct editing point in the memory 12 is performed by switching the switch 16' to a/- as in the case of the playback tape recorder.
When C' is turned on and the dial is rotated in the forward direction, the contents of memory 12 are YR+ 1→2FFFF→000
It will be played in the order of oO → Shift, and if it is rotated in the opposite direction, it will be played in the order of xR-+0OoOO-2FFFF-YR+1 (D).In this way, the audio will be played both when the dial is turned and stopped. You can stop the dial at the correct position and specify this point as the editing point.The position information of this point can be obtained from the CPU using the same operation as above.
Loaded into 4. Let this space be XR+NR.

As described above, the boundaries of c and D in Fig. 2 and the PCM
Position information based on sample points and information based on addresses on memory are stored in registers within the CPU.

Next, by continuously reading out the contents of the memory 12 and the memory 9δ using the editing point determined above as a boundary point, the audio similar to that actually edited in the memory is monitored. At this time, cross-fade processing is performed at the editing point to obtain a natural sound connection. -This series of actions is called rehearsal here. At the time of rehearsal, the editor gives a rehearsal instruction to the CPU 4 from the operation input section 7.

The CPU 4 has an address counter interface element 14.
The initial value of the address counter 13 is controlled through the address counter interface element 1, and the address counter 10 is controlled through the address counter interface element 1. For example, this is 1111! i, 10m! ! , 10 (JIg
.

300ml, 500m! , 18, 38, etc., by selecting one of the operation buttons. The operation when the cross-fade time is F seconds is shown in FIG. 9(a). Memory reproduction in the case of rehearsal is performed in the following order based on instructions from the CPU 4. IJ , - Monkey starting point is 2FFFF → ooooo- at YR+1 of memory 12
'X*cD is played in order, but In+Nil-172
Start the crossfade. Here, 2 is the number of memory addresses to advance in F seconds, ts6 x 105B x,
This corresponds to ir seconds. Memory 12 is XR+NR
-When reaching V2Z, memory 10FiXp + Np-
Playback begins from Wz and the crossfade period begins.

Thereafter, for one second, memories 9 and 12 are simultaneously reproduced by 2 memory addresses, and a cross-fade process is performed. The cross-fade period ends when memory 12 reaches In+NR+172 Z and memory 9 reaches Xp+Np+%Z, and only memory 9 is played back to Yp, ending the rehearsal.

Here, the above-mentioned cross-fade processing will be specifically described. FIG. 10 is a detailed block diagram of the fade processing circuit 16 in FIG. 3. Fil is an input from switch 16' in FIG. 3, and F-2 is an input from switch 16 as well. GK is a sampling clock pulse input. Reference numeral 61 is a fade curve generation circuit that generates coefficients of a fade curve, and can be a counter or a combination of an address counter and a ROM. An example of the output of this circuit is shown at 66 in FIG. Here, the vertical axis is the magnitude when the above coefficient is subjected to D/mu conversion. 62 is a multiplier circuit, which receives input from the output of the fade curve generating circuit 61 and Fi1 power).
A multiplication circuit 62 digitally multiplies this result with the CM audio signal.
The output of Fil d>-doard becomes the original. 63 is a fade curve generating circuit similar to 61, and an example of its output is shown at 67 in FIG. 64 is the input of Fi2 and 6
The multiplication circuit 64 multiplies the output of IFi2, and the output of the multiplication circuit 64 fades in the input from IFi2. Reference numeral 66 denotes an adder circuit that adds the outputs of the multiplier circuits 64 and 62, and from this output 10Irl, a four-digitally cross-faded signal 75 can be obtained. In this way, a cross-faded tll'c signal is obtained at the output of the fade processing circuit 16 at the editing point.

Reference numeral 68 denotes a fade time setting circuit which receives the selection output from the operation input section 7 and determines the rate on the horizontal axis in FIG. 11 in the fade curve generating circuits 61 and 63. Through the above process, if the reno-sal is completed and there is a problem with the connection of sounds near the edit point, the process after the process of determining the edit point in the memory is repeated.

However, setting the address xR0NII on the memory mentioned above,
When t;i,
As shown in Figure (b), at the end of the fade-out, the address on the memory exceeds Yi, so the discontinuous PCM audio signal will be faded out. In this case, an accurate loss-faded signal cannot be obtained at the editing point.

Therefore, in this embodiment, in the edit point search mode, the address on the memory is determined by the specific address detection means (xR+NR+-)
When Yn is calculated and detected, (2) the lamp 28 provided in the control output section 7' is turned on.

27 (2) By notifying the editor by cutting off all analog signals supplied to the speaker 21, it is possible to prevent discontinuous PCjM audio signals from fading out.

Further, although the above description has been made regarding the fade-out in the cross-fade processing portion, the same applies to the case where the fade-out is simply performed instead of the cross-fade processing portion.

If a suitable editing point is obtained here, proceed to the next editing operation.

In the editing process, the same signal that has been rehearsed in memory is recorded onto the actual tape, but the signal played back by the playback head that is directed to the recording head of the recording tape recorder and the signal played back by the playback tape recorder are combined. The timing of each signal reproduced by the reproduction head is adjusted by an appropriate delay circuit, and the recording head of the recording tape recorder just contacts the first position of the cross-fade period shown in Fig. 1<b). At an instant, the signal played from the first position of the cross fade of the second tape in Figure 2, (b) on the recording tape recorder and the first signal in Figure 2 (&) on the playback tape recorder. The signal reproduced from the first position of the cross-fade period in the D portion of the tape passes through the cross-fade processing circuit 16 shown in FIG. 3, passes through the interpolation circuit 17, is output to the W terminal, and is supplied to the recording head. This allows the signals that have been previously recorded in the vicinity of the editing point to be correctly connected to the signals that are newly recorded by the editing operation. At this time, the switches 15 and 15' are of course b-c and "b'-c" are ON.

Since the exact editing point on the tape is held in the register within the CPU 4 as described above, the synchronized running of the tape, the delay amount of the delay circuit, the cross-fade timing, etc. are all performed by commands from the CPU 4. The operation of the cross-fade processing circuit 16 is exactly the same as in the case of rehearsal. When the above process is completed, the second tape shown in Figure 1 (C) is completed, and the editing work is completed. □ According to the above embodiment, because the editing is done at the stage of the audio PGM signal itself, regardless of the recording format of the tape deck, the errors that occurred during manual editing when newly reconfigured and recorded on the recording side tape recorder. There is no lack of information at all.

Furthermore, in the above configuration, when reading a signal from the memory 12 and performing cross-fade processing for monitor playback, a specific address is calculated from the initial value of the address counter and the cross-fade setting time. Since the notification is made by lighting the lamp 28 or cutting off the monitor audio output, it is possible to accurately detect the position of the editing point. At this time, if the editing point is inappropriate, it is only necessary to rewrite it in the memory, so it is very easy to change it.

Furthermore, since the positional information of the editing point is given by using both the time code and the sampling pulse, the position accuracy can be improved to the level of the sampling pulse.

Further, signals can be read out from the memory at variable speeds, and editing points can be easily selected by manually reproducing the signals at a slow speed. That is, when performing fade processing, editing points can be easily and accurately determined, and signal loss and discontinuous editing can be prevented.

As described above, according to the present invention, the reproduced signal is stored in the memory, the digital signal read from the memory is fade-processed via the fade time setting means, and the fade processing is performed based on the setting value of the fade time setting means. By monitoring the addresses in the memory and being able to notify when a specific address is detected, it is possible to accurately know the edit point during the fade period. Therefore, it is possible to provide an excellent digital signal editing device that can easily and accurately perform editing with a cross-fade effect without causing signal dropouts or discontinuities.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing the concept of analog editing, FIG. 2 is an explanatory diagram showing the concept of the editing method adopted in the digital signal editing device of the present invention, and FIG. 3 is an implementation of the digital signal editing device of the present invention. A block diagram showing an example, FIG. 4 is an explanatory diagram showing the writing state of the memory 9, FIG. 6 is a waveform diagram explaining the concept of interpolation, FIG. 6 is a waveform diagram explaining the interpolation function of this embodiment, Figure 7 is a block diagram showing the configuration of the interpolation circuit.
9 is an explanatory diagram showing the write state of the memory 12, FIG. 9 is a diagram showing the temporal correspondence of the memories in FIGS. 4 and 8, FIG. 10 is a block diagram showing the configuration of the cross-fade processing circuit, and FIG. The figure is a characteristic diagram showing the output of the fade curve generating circuit converted to 'kD/m. 4... cpnls... ROM, 7... operation input section, 7'... control output section, 9...
...First memory, 1o stomach...First memory address counter, 12...Second memory, 13.
...Second memory address counter, 15, 1
5'...First and second switch means, 16
...Cross fade processing circuit, 17...
・Interpolation circuit, 18...D/MU converter, 21...
... Speaker, 22 ... Clock generation circuit, 23 ... Manual clock generator, 27 ...
...Specific address detection means, 28...Lamp,
41, 42.45... Latch circuit, 46...
...Reference clock pulse generation circuit, 47...
... Counter, 48 ... Slope coefficient generation circuit, 49 ... Multiplication circuit, 5o ... Addition circuit, 61 ... Fade curve generation circuit ( 63...Fade curve generation circuit (fade-in means), 68...Fade time setting means. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 4
Figure 4 seconds ←u1 Figure 5

Claims (1)

[Claims] A memory for storing a reproduced digital signal, a manual clock pulse generating means for manually varying the frequency of a clock pulse for reading this memory, and a means for converting the digital signal read from the memory into an analog signal. a fade time setting means for fading in or out a digital signal read from the memory from a specified address, and monitoring the address of the memory based on the setting value of the fade time setting means to detect a specific address. What is claimed is: 1. A digital signal editing device comprising: means for detecting, and means for notifying based on the output of the detecting means.