JPS5850032A - Channel controlling system - Google Patents

Abstract

PURPOSE:To reduce the number of input pins of a channel package or an LSI to the half and share a line test circuit to reduce the gate quantity, by operating OR between two-channel components of input signal lines of an I/O interface and scanning them in time division. CONSTITUTION:Plural channels 103 are connected between a channel controlling part 101 and receivers 220 and 221 which receive I/O interface X and Y signal lines XREQER and YREQER, and their outputs are selected and outputted to drivers 222 and 223. Inputs are scanned in time division and selected by an input register 201 of the channel 103, and the output is held in input registers 202 and 203 of channels X and Y. Outputs of registers 202 and 203 are selected successively in a selecting circuit 204 by the output of a decoder 205 and are applied to an establishing circuit 205. Outputs of registers 202 and 203 are compared with the output of the circuit 204 in the circuit 205; and when a change is detected, the switching of time division is stopped temporarily, and the processing is performed in output registers 207 and 208 of channels X and Y.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a channel control method, and more specifically, a channel control method for controlling an input/output device (hereinafter abbreviated as 10) via an input/output interface (hereinafter abbreviated as I10 interface). -Regarding reduction of gate amount of interface signal of hardware.

As an interface method for connecting a channel and Ilo, there is an interlock method in which responses of each signal line are confirmed. Figure 1 shows the I10 of this interlock system.
It shows the status reporting sequence from I210 at the interface. In Figure 1, R
, BQIN is the request signal from I,10, 8ELOUT is the selection signal from the channel, ADRIN is the I10 address report signal, and at this time, the input bus BUSIN is I1.
0 address is confirmed. CMDOUT is ADRIN
The response signal 5TAIN is the status report signal of I710, and 8RVOUT is the response signal to 5TAIN. At this time, the I and 10 statuses have been determined for BUSIN.

According to this sequence, when EQIN from Ilo is detected, 5ELOUT is output and accepted.

Ilo issuing REQIN has 0 PLI for it.
N-1ADFtIN exit L, BUSIN is l107
) 'Response has been confirmed. The channel is BUSIN I
When receiving 10 addresses, it responds with CMDOUT.

Furthermore, Ilo issued 5TATN and BUSIN received I10.
The status is confirmed. When the channel receives the BUSIN ■10 status, it responds with 8 RVOUT.

FIG. 2 shows an example of a prior art configuration of channel control hardware that uses the above-mentioned interlock method.

In FIG. 2, 101 is a channel control unit CHC, and 102 is channels CH0, 1, . . . i which control the I10 interface. Channel CT(0,1
, . . . i are the receiver Cv denoted by 105
Drivers DB and 106 are connected to the ■10 intermace line via V.

That is, in the conventional configuration, each channel independently connects the 710 interface line to the
There is a problem in that packages and LSIs require a large number of pins and gates.

Therefore, it is an object of the present invention to solve the above-mentioned conventional problems and to improve the channel I10 interface.
The object of the present invention is to provide a channel control method that reduces the number of pins and gates in a package or LSI.

In order to achieve the above object, the present invention focuses on the fact that the sequence of the I10 interface is an interlock system.In other words, in the interlock system, the request signal does not disappear unless a response signal is returned. By collectively ORing the input signal lines of the l710 interface for multiple channels and using the OR signal lines in a time-sharing manner, the input signal lines corresponding to each channel are sequentially selected. .

Hereinafter, the contents of the present invention will be explained in detail based on examples.

FIG. 3 is a block diagram of an embodiment of the present invention. In FIG. 3, a channel control unit (CHC) 101, an L/'/- bar (RCV) 105, a driver (DRv) 10
6 is the same as the conventional example shown in FIG. 103 is 2 channels
For example, for CH (X, Y) in which channel X and channel Y are built-in, input signal line X of channel
REQIN, ... and channel Y input signal line YREQ
The outputs obtained by ORing the outputs of the corresponding RCV 105 are input to IN, . . . . Reference numeral 107 denotes selection signals TKX8EL and TKY8BL which determine which input signal line of the two channels is selected, and are output so that only one of them is selected.

A specific example of the configuration of the channel 103 is shown in FIG.

In FIG. 4, X is added to the beginning of the part name (abbreviation) for channel X, and Y is added to the part name for channel Y. 220 and 221 are the ■10 interface signal lines XREQIN of each channel
, ..., YR, BQIN, ... with receiver circuits RCvX and RCvY, as shown in Fig. 3 (7) 105 E
Equivalent to. It is something. RCVX220. RCVY22
The outputs of 1 are ORed, and the OR signal line is CH(X,
Y) 103 register (input to INJZ heart. I
NR201 is an update type register having bits corresponding to each input signal line of the I10 interface. 209 is a one-pit counter (CYCL) for determining which channel's I10 interface input line is selected, and 210 is its decoder (DEC). 216 and 217 are D E C2
10 output signal lines, respectively FLCvX220, R,
CVY221 Select all TKXSEL, TKYSEL
is output. These 216 and 217 are 1 in Figure 3.
Corresponds to 07. 202 and 203 are update type registers XINLl'L and YINLR, [) E C21
0 output signal line, the contents of INR201 are currently selected as X1NR202 and YIN R20.
3. 204 is a selection circuit that switches the outputs of XlNR202 and YINR203 by the output of D E C210, and 205 is a selection circuit 20
A circuit INLT that compares the output of 4 and the output of INR201 and determines which signal line has changed in value.
EST.

Depending on the change in the value of the signal line in INLTEST 205, the signal line (CHINT) 212 is set to "1" and the CHC
Interrupt to l01 and control flip-flop (LOC
K) When setting 206 @1" to suppress the counting operation of CY CL 209, and - register 207 or 2
There are two cases: resetting the value of the corresponding bit of 08. Register (X0UTR) 207, Register (YO
UTR) 208 is a register having bits corresponding to the output signal line of the I10 interface of each channel. These X0UTR207, YOUTR'2
The input of 08 is the /( line (INB) from CHC101.
US) 213 is connected, and 1) it is selected by the output of EC 210 so that any value can be set. The outputs of X0UTR207 and YOUTR20B are passed through drivers DRvX222 and DRVY223t.
Output signal line X5EL of each I10 interface
OUT, ..., YSEI, OUT, ... are connected to the tail. D-VX 222, DRVY 223 corresponds to 106 in Figure 2.

A timing chart for explaining the operation of FIG. 4 is shown in FIG. CY CL 209 usually repeats inversion at a certain period. This value of CHCl01 is D E
Decoded by C210, CY CL 209 is "0"
TKXSBL 216 between 1" and T'KYS between 1"
E L 217 is output alternately, thereby scanning the input signal line on the channel X side and scanning the input signal line A on the channel Y side alternately. In this scan operation, RCVX220 or RCVY2
210) The output line (r) value is set to INL'TES, and depending on which I10 interface is currently selected, the value of XlNR202 or YINR203 is compared with the value of INR201.
T 205 and if they match, applicable ■71
Since there is no change in the value of the 0 interface signal line, a scan operation is performed for the input signal line of the other 10 interface.

Next, for example, the RBQIN signal line (XRE
QIN) becomes "1", at the time of the next channel X side scan, the corresponding REQIN
The bit corresponding to
When performed by NLTEST 205, it is determined that there is a difference in the bit corresponding to the above REQIN. As a result, I,+OCK 206 is set and CHINT
212 is output and interrupts CHC101. Also, L O
By setting CK 206, CY CL
Since the count operation of 209 is suppressed, the scan operation is also suppressed, so that the TKXSEL 216 is left open and the RCvX 220, CH (X, Y), and the internal 4X side register remain selected. On the other hand, CHCl01
to CHINT 212 (as a response to two IN
Via BUS 213, the value to be set to XOUTR 207 is sent. In this example, 5ELOU on the X side
A value is set so that the T(X8ELOU'l') signal line becomes 11".Thereby, LOCK 206,
CHINT 212 is reset and CYCL 209
counting and scanning operations are restarted.

As described above, according to this embodiment, by ORing the input signal lines of the I10 interface for two channels and scanning in time division, the number of input pins of the channel package or LSI can be reduced by approximately half. Also, I N R
201 and INLTEST 205 can be shared for two channels, and the amount of gates can be reduced accordingly.

Generally, the number of pins of an LSI or PK can be reduced by ORing the interface input signal lines for a plurality of interface control devices and using them in a time-sharing manner. Further, by sharing the circuits inside the interface control device with a plurality of interface control devices, it is possible to reduce the amount of gates in the node hardware.

[Brief explanation of drawings]

FIG. 1 is a timing diagram showing an example of an l710 interface sequence, FIG. 2 is a diagram showing an example of the configuration of channel control software according to the prior art, and FIG. 3 is a diagram showing an implementation fJ of the present invention. FIG. 4 is a diagram showing a specific example of the structure of the channel in FIG. 3, and FIG. 5 is a timing diagram for explaining the operation of FIG. 4. 10f...Channel control unit, 103...Channel (interface control unit), 105...Receiver-1106...Driver, 107...
Selection signal, 201...input register, 202, 203
. . . Channels X and Y input circuits 89, 204 and 5 selection circuits, 2050. . Judgment circuit, 206... Control flip-flop, 20
7, 208...channel X, Y output register, 2
09...Counter, 201...Decoder.゛First
Figure 3

Claims (1)

[Claims] 1. In a plurality of channels connected to an input/output device via an input/output interface, the plurality of channels are divided into one or several groups, and each group has input/output for the plurality of channels. The interface lines are ORed all at once, and the ORed input/output interface lines are time-divisionally switched to sequentially select and hold the input/output interface signal corresponding to each channel, and the input/output interface signal of the currently selected channel and the input/output interface signal of the currently selected channel are selected and held. A channel control method characterized in that the input/output interface signals of the corresponding channel are compared, and when a change is detected, the time division switching is temporarily stopped and the interface signal of the corresponding channel is processed.