KR20030025610A - Redundancy processors system and method for preventing data error thereof - Google Patents

Abstract

PURPOSE: A system for supporting a dual processor and a method for preventing a data error in the system are provided to control a processor in a specific address area according to an operation of other process when the processor executes an operation by adding a semaphore circuit. CONSTITUTION: An address area of a message whose width is bigger than a width of a memory is set in the memory out of messages being transmitted/received through the memory. A semaphore circuit with respect to the set memory area is embodied(S200-S210). In an operation at the set area, a processor applies a low pulse signal to an input terminal of the semaphore circuit(S220). The semaphore circuit selectively outputs a high pulse signal or a low pulse signal in accordance with an operation of other process(S230-S250). In the case that a low pulse signal is output from the semaphore circuit, the processor executes an operation in the set area and applies a high pulse signal to the input terminal of the semaphore circuit according as the operation is completed(S250-S270).

Description

REDUNDANCY PROCESSORS SYSTEM AND METHOD FOR PREVENTING DATA ERROR THEREOF}

The present invention relates to a dual processor support system and a control method thereof, and more particularly to a system and method for preventing a data error that may occur when a message larger than the data width of a dual port RAM is transmitted during communication between two processors by adding a semaphore circuit. It is about.

1 is a block diagram of a dual processor support system according to the prior art.

Referring to FIG. 1, a conventional dual processor supporting system includes two processors 1 and 2, a memory 3 for communication between the two processors 1, 2, and two processors 1 and 2. It consists of a memory system bus comprising a data bus, an address bus 4, 5 and a control signal bus 6, 7 connecting the memory 3.

The memory 3 may be a dual port RAM having a 16-bit data width (hereinafter, referred to collectively as a dual port RAM), and the dual may be provided when the two processors 1 and 2 are located in different units. The port RAM 3 may be located in either of two units.

The description of the operation in the state configured as described above is as follows.

The first processor 1 and the second processor 2 are connected to the dual port RAM 3 through their data buses 4 and 5 to write and read data.

However, since the dual port RAM 3 has two ports but only one internal RAM array, two processors 1 and 2 simultaneously request the operation of the same area through the two ports. The BUSY signal is transmitted to the processor that attempted to operate later, and when the bus operation of another port is completed, the BUSY signal is inactivated so that the processor can write and read.

However, assuming that the data widths of the two buses 4 and 5 are 16 bits, a read / write operation of word data is performed for each bus cycle, and a message transmitted and received between the processors 1 and 2 is one. If the data width is longer than the word of, the write or read operation cannot operate on all the messages, and the message must be sent through one or more cycles.

For example, if the data to be written is 64-bit data, four write operations must be performed.

If the first processor 1 using the left port attempts to write 16 bits among the 64-bits, the second processor 2 using the right port attempts to read 16 bits of the same address. The second processor 2 waits with the BUSY signal activated, and the first processor 1 performs a write operation.

Then, the second processor 2 reads at the same address, and then the first processor 1 writes data to be written to the next address, while the first processor 1 tries to write the remaining data. If an operation of a process with a higher priority is required, a write operation for the next data is delayed, and the second processor 2 does not recognize that the write operation is delayed in the first processor 1 and does not recognize the remaining data of 64 bits. Will read.

Therefore, there may be a problem that only 16 bits of 64 bits are transferred to the first processor 2 and other data that is not desired is transferred to the remaining bits.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems. When the processor attempts to perform an operation on a specific address region by adding a semaphore circuit, it is necessary to determine whether another processor is operating in the specific address region. It is an object of the present invention to provide a dual processor supporting system for controlling a processor to allow or prohibit an operation in the specific address region according to whether or not a data error is prevented in the system.

An embodiment of the present invention for achieving the above object, in a system that supports two processors for transmitting and receiving messages by performing a read or write operation through a single memory, the memory is a message width that is transmitted and received An address area larger than the data width of the memory is set, and includes two input terminals each connected to the two processors through a control signal line, and two output terminals outputting a result value to each of the two processors. When a low pulse signal is input from the first processor for operating in the area, it is determined whether the second processor is operating in the address area, and when the low pulse signal according to the operation is input from the second processor, 1 output a high pulse signal to the processor to The data error protection unit includes a plurality of semaphore circuits that support the operation of the control circuit and to output the low pulse signal to the first processor when the high pulse signal is input from the second processor. Characterized in that further comprises.

Another embodiment of the present invention for achieving the above object is to set the address area when the message width of the message transmitted and received through the one memory between the two processors than the data width of the memory in the memory, and the set memory Implementing a semaphore circuit that outputs a processor operation control signal for the region; A second step of applying, by the processor, a low pulse signal to an input terminal of the semaphore circuit during operation in the set region; A third step in which the semaphore circuit receiving the low pulse signal selectively outputs a high pulse signal or a low pulse signal according to whether another process operates; When the high pulse signal is output from the semaphore circuit, the processor returns to the second step, and when the low pulse signal is output from the semaphore circuit, the processor performs an operation in the set area and then, upon completion of the operation, And a fourth step of applying a high pulse signal to an input terminal of the semaphore circuit.

1 is a block diagram of a dual processor support system according to the prior art.

2 is a block diagram of a dual processor support system according to the present invention.

3 is a semaphore circuit diagram in accordance with the present invention.

4 is a flowchart for explaining a data error prevention method in a dual processor support system according to the present invention.

** Description of symbols for the main parts of the drawing **

1: first processor 2: memory (dual port RAM)

3: second processor 10: data error protection unit

100: semaphore circuit 110, 130: first, second D flip-flop

120, 140: first and second negative AND gate

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a dual processor support system according to the present invention.

Referring to FIG. 2, in the dual processor supporting system of the present invention, two processors 1 and 2 and a memory 3 (dual port RAM) for communication between the two processors 1 and 2 are conventionally used as data buses. (4, 5) and the control signal bus (6, 7) in a state connected to the control signal received from the two processors (1, 2), the operation whether the control signal to the two processors (1, 2) It further includes a data error prevention unit 10 for outputting.

The data error protection unit 10 is used in many types to ensure mutually exclusive access to the common dual port RAM 3 in order to prevent data from being changed at the same time by both processors (1, 2) A plurality of binary semaphore circuits 100 are widely used among the hardware techniques.

The semaphore circuit 100 is introduced by Dijkstra as a tool for synchronizing tasks. In addition to the binary semaphores, counting semaphores, case-wait semaphores, and the like. There are semaphores with various types of functions.

The binary semaphore functions to synchronize specific domains because only one task uses a specific region and waits for the rest if multiple tasks are to be used simultaneously.

3 is a semaphore circuit of the present invention.

Referring to FIG. 3, the semaphore circuit 100 includes two D-type flip-flops 110 and 130 connected to input terminals 111 and 131 to which control signals are input from the two processors 1 and 2, respectively. Two negative AND gates 120 and 140 are connected to the output terminals 123 and 143 for outputting an operation control signal to the processors 1 and 2, respectively.

The D flip-flops 110 and 130 include D inputs 111 and 131 and Q outputs 113 and 133, and inverters 114 and 144 are added to the Q output terminal 113 to invert the output signal. The inverted Q output is connected to the first inputs 121 and 141 of the negative AND gates 120 and 140 by signal lines.

The outputs of the negative AND gates 120 and 140 are connected to the second inputs 142 and 122 of the other negative AND gates 140 and 120, respectively, and to the output terminals 123 and 143, respectively.

4 is a flowchart illustrating a data error prevention method in a dual processor supporting system according to the present invention.

Referring to FIG. 4, the data error prevention method of the dual processor supporting system according to the present invention stores an address area when a message width of a message transmitted and received through the memory 3 is larger than the data width of the memory 3. (S) and implementing the semaphore circuit 100 for the set memory area (S200 to S210), and the processors 1 and 2 are operated when the semaphore circuit 100 operates in the set area. Applying a low pulse signal to the input terminal (S220) and the semaphore circuit 100 receiving the low pulse signal selectively outputs a high pulse signal or a low pulse signal depending on whether other processes (2, 1) operate. And a high pulse signal is output from the semaphore circuit 100, and is fed back to the step S220, and a low pulse signal is output from the semaphore circuit 100. After performing the operation in the set area, the parser may be configured to apply a high pulse signal to the input terminal of the semaphore circuit (S250 to S270) as the operation is completed.

First, when both processors 1 and 2 attempt to operate in the same region of the dual port RAM 3, only one processor is operated using the BUSY signal and the other processors are operated later. Since it is the same as the prior art, only a case in which a message having a data width or more through the added data error prevention unit 10 is transmitted and received will be described with reference to FIG. 4.

First, an address area when a message width is greater than the data width of the memory 3 among messages transmitted and received through one memory 3 between the two processors 1 and 2 is set in the memory 3 (S200), A semaphore circuit 100 that outputs a processor operation control signal for the set memory area is implemented (S210).

Therefore, the semaphore circuit 100 must be implemented in a number of cases when the region is not continuous.

The first processor 1 inputs a low pulse signal to the semaphore circuit 100 to operate in the set region (S220).

The semaphore circuit 100 receives the low pulse signal and determines whether the second processor 2 is operating in the corresponding address area of the memory (S230). Although not shown in FIG. 4, the semaphore circuit 100 may be used. A detailed operation principle of determining whether the second processor 2 is operated will be described later.

The low pulse signal becomes an input of the semaphore circuit 100 D-type flip-flop 110.

The operation of the D flip-flops is well known in the art and will not be described in detail herein. Basically, the D flip-flop has only one binary input signal and one binary output signal so that the input signal is synchronized with the input clock signal of the D flip flop. That is, the binary output signal of the D flip-flop takes the state of the binary input signal when a specified clock pulse transition occurs.

Accordingly, the D-type flip-flop 110 outputs a low pulse signal according to the low pulse signal input, and is inverted as shown in FIG. 3 so that the high pulse signal is the first input 121 of the negative AND gate 120. ) Is entered.

In this case, when the second processor 2 is operating first, the low pulse signal output to the second processor 130 is input to the second input 122 of the negative AND gate 120. The output of the AND gate 120 becomes a high pulse signal.

That is, when the second processor 2 is operating in the step S230, the semaphore circuit 100 outputs a high pulse signal to the first processor 1 (S240), and inputs the high pulse signal. The received first processor 1 again performs step S220 of inputting a low pulse signal to the input terminal 111 of the semaphore circuit 100.

However, when the second processor 2 is not operating, the second processor 130 inputs a high pulse to the input terminal 131 of the semaphore circuit 100 to complete the operation. Since the high pulse signal output 143 to the processor 2 is input to the second input 122 of the negative gate 120, the output 123 of the negative gate 120 is a low pulse signal. Becomes

That is, when the second processor 2 is not operating in the step S230, the semaphore circuit 100 outputs a low pulse signal to the first processor 1 (S250). After performing the operation in the set area (S260) (1), a high pulse signal is input to the input terminal 110 of the semaphore circuit 100 to complete the operation (S270).

Therefore, even when both processors intend to operate in the same area at the same time, data errors can be prevented by prohibiting the operation of another processor until the processor in which the semaphore circuit operates in advance finishes the operation.

The present invention is not limited to the embodiments described above, and various modifications and changes can be made by those skilled in the art, which are included in the spirit and scope of the present invention as defined in the appended claims.

As described above, the present invention has an effect of adding a semaphore circuit to prevent data errors that may occur when a message larger than the data width of the memory is transmitted during communication between the processors.

Claims (2)

In a system that supports two processors to send and receive messages by performing a read or write operation through a single memory, The memory has an address area in which the message width to be transmitted and received is greater than the data width of the memory, A low pulse signal from a first processor for operating in an address region of the set memory, having two input terminals connected to the two processors, respectively, via control signal lines, and two output terminals outputting result values to the two processors, respectively. If is input, it is determined whether the second processor operates in the address area, and when a low pulse signal corresponding to an operation is input from the second processor, a high pulse signal is output to the first processor to output the high address signal. The data error prevention unit includes a plurality of semaphore circuits that support the operation of the control circuit and output a low pulse signal to the first processor when the high pulse signal is input from the second processor. Characterized in that further comprises Dual processor support system. Implementing a semaphore circuit that sets an address area in a memory when a message width is greater than a data width of a memory among messages transmitted and received through a memory between two processors, and outputs a processor operation control signal for the set memory area. A first step of doing; A second step of applying, by the processor, a low pulse signal to an input terminal of the semaphore circuit during operation in the set region; A third step in which the semaphore circuit receiving the low pulse signal selectively outputs a high pulse signal or a low pulse signal according to whether another process operates; When the high pulse signal is output from the semaphore circuit, the processor returns to the second step, and when the low pulse signal is output from the semaphore circuit, the processor performs an operation in the set area and then, upon completion of the operation, And a fourth step of applying a high pulse signal to an input terminal of the semaphore circuit.