JPH04277812A - Multiport access control circuit - Google Patents

Abstract

PURPOSE:To arbitrate plural access requests to a peripheral device requiring continuous access and to prevent an abnormal operation from being generated in the case of an access locking control by locking the arbitration of the access requests in the manner of a hardware and setting the continuous access to a single port corresponding to the relevant peripheral device. CONSTITUTION:Binary counters 10 and 11 are provided to count the number of times to perform access on the sides of a port (1) and a port (2) corresponding to the inputs of access requiring signals 106 and 107 and as a logic means to generate a lock control signal to an access arbitration circuit 9, a logic circuit is provided with OR gates 12 and 13, AND gates 14 and 15, NOR gates 16 and 17, data selectors 18 and 19 and inverter 20.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-port access control circuit, and more particularly to a multi-port access control circuit that arbitrates access when multiple information processing devices access the same peripheral device in an information processing device that accesses peripheral devices. This invention relates to a multiport access control circuit.

0002

2. Description of the Related Art Conventionally, this type of multiport access control circuit has functional blocks as shown in FIG. Note that in this example, in order to simplify the explanation, a case of 2-port access is used as an example.

In FIG. 5, a peripheral device 1 represents a peripheral device (peripheral I/O, memory, etc.) to be accessed. An enable signal (hereinafter referred to as ENB) that activates the buffers is input to the bidirectional buffers 2 and 3, and the access arbitration circuit 4 is a circuit that arbitrates access to the peripheral device 1, and receives a signal that accepts an access request. Terminals (hereinafter referred to as P1SEL and P2S
EL), enable signal output terminals that become active when access is accepted (hereinafter referred to as P1E and P
2E), a signal terminal for notifying that access has been completed (hereinafter referred to as P1ACK and P2ACK),
Signal terminal that locks access arbitration (hereinafter referred to as P1LOCK)
and P2LOCK), and a reset signal terminal (hereinafter referred to as RES) that initializes the operation of this access arbitration circuit.
). Actually, in addition to this, there are signal terminals that specify whether access to peripheral device 1 is read/write, and signal terminals that control the direction of bidirectional buffers 2 and 3, but these are omitted because they are irrelevant to the present invention. ing. P1SEL, P1LOCK, P1ACK, P
Each terminal of 2SEL, P2LOCK and P2ACK is
System requesting access (e.g. microprocessor)
The signal is converted and connected. Furthermore, P1E and P2E are connected to enable signal terminals of bidirectional buffers 2 and 3, respectively. Bidirectional buffers 2 and 3 are
Each data bus including data buses 102 and 103;
It is connected to the data bus 102 of the peripheral device as shown in FIG.

The operation of this example is shown in FIGS. 6(a), (b), and (c).
, (d), (e), and (f). In this time chart, P1LOCK, P
2LOCK is in a disabled state. In Figure 6, “
A” section is access request signal 1 from port (1)
06 is earlier than the port 2 access request signal 107. In the period "A", the P1SEL terminal becomes active via the initial access request signal 106, and the P2SEL terminal is inactive, so that the access arbitration circuit 4 operates on the port (1) side. Then, the P1E terminal becomes active, and after a predetermined access time, the P1ACK terminal becomes active in a pulsed manner. As a result, the port (1) side ends the access and returns the P1SEL terminal to inactive. P
When the 1SEL terminal becomes inactive, the P1E terminal becomes inactive, the bidirectional buffer 2 on the port (1) side is cut off, and the access ends. While port (1) is operating, access request signal 1 is sent from port (2) side.
If there is an access request via P2
(SEL terminal becomes active), the P2E terminal remains inactive until the access to the port (1) side is completed, and the buffer on the port (2) side is in an empty state. When access on the port (1) side ends, P2
The E terminal becomes active and the port (2) side becomes operational. Section "B" represents a case where the access request from port (2) is faster than the access request from port (1). The operation in this case is the same as in the example described above, with the port (1) side and port (2) side swapped. Section "C" is the state when there are access requests for port (1) and port (2) at the same time. In this example, priority is given to port (1), so the operation is the same as section "A". Become.

FIGS. 7(a), (b), (c), (d), (
e), (f), (g) and (h) are timing charts showing the operation of clock signals. Section "D" indicates a case where access with lock occurs simultaneously from both port (1) and port (2). As explained above, since port (1) has priority, the P1E terminal becomes inactive first, and the port (1) side becomes accessible. As in the previous example, the first access ends and the P1SEL terminal returns to inactive. At this time,
Since P1LOCK terminal is active, P1SEL
Even when the terminal is inactive and the P2SEL terminal is active, that is, there is only an access request from port (2), the P2E terminal is not enabled and port (2) does not operate. The P1SEL terminal becomes active again, access to the port (1) side is performed, and the P1LOC
When the K terminal becomes inactive, the P2E terminal becomes enabled and the port (2) side becomes accessible. The period "E" represents the state in which the P2LOCK terminal is active, and is an operation in which port (1) and port (2) are interchanged in the above explanation.

FIG. 8 shows a functional block diagram of another conventional example. The access arbitration circuit 9 is an arbitration circuit different from that in FIG. 5, and is an arbitration circuit used when there is no lock signal (P1LOCK, P2LOCK). Such an access arbitration circuit is required for systems that do not support lock signals; for example, IEEE101
4 standard (VME bus), which does not cancel the access request even after the access is completed. On the other hand, the above-mentioned example corresponds to a bus that supports a lock signal, such as the IEEE796 standard (multibus).

The operation of the conventional example shown in FIG. 8 is illustrated in FIGS.
), (c), (d), (e), and (f). Both P1SEL and P2SEL terminals become active at the same time, and since port (1) has priority, P1E terminal becomes active, and port (1)
It will be accessible from. After the specified access time,
The process is the same as the previous example until the P1ACK terminal becomes active in a pulsed manner. On the other hand, port (1)
performs lock access, the P1SEL terminal does not become inactive, the P1E terminal continues to become active, and port (1) becomes continuously accessible. When port (1) completes two accesses and lock is no longer required, P1S is activated in synchronization with the pulse of the P1ACK pin.
Return the EL terminal to inactive. In this way, lock access is performed by not canceling the access request even if the completion signal is received. timing·
The latter half of the chart shows a case where the port (2) side performs lock access.

[0008] Here, only an example of two ports is shown, but
Exactly the same processing method can be applied to the case of three or more ports. Further, in this example, two accesses are one meaningful access, but in I/O, etc., three or four consecutive accesses may be one meaningful operation.

[0009]

[Problems to be Solved by the Invention] In the above-mentioned conventional multi-port access control circuit, access lock control was originally performed on read modifier write in memory access and interrupt controller (for example, i8259
) exists to support accesses where multiple accesses have one meaning, such as the interrupt acknowledge cycle. However, there are other cases in which it is necessary to perform locking using software. A simple example is a peripheral I/O in which the I/O internal register number is specified on the first access, and the actual data is exchanged on the second access (for example, μPD720
01).

[0010] In the above-mentioned case, access must be locked, but the conventional multi-port access control circuit described above cannot lock it because it does not know this, and in some cases, access requests from other ports This may cause the system to malfunction. For example, the peripheral I/O (μPD7
2001), the access is not locked after specifying the register from port (1), so if there is an access from port (2), port (2)
There is a drawback that an abnormal operation occurs in which data is exchanged between the peripheral I/O and the peripheral I/O.

[0011]

[Means for Solving the Problems] The multiport access control circuit of the present invention arbitrates access requests through a predetermined access arbitration circuit and exclusively enables bidirectional buffers, thereby allowing access requests from multiple ports to be In a multi-port access control circuit that processes access requests, means for counting the number of accesses of each port included in the plurality of ports, and an output of the counting means,
and logic means for generating a control signal for locking the arbitration function of the access arbitration circuit.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a functional block diagram of an embodiment of the present invention. The same numbers as in the conventional example described above represent the same functional blocks. As shown in FIG. 1, this embodiment includes bidirectional buffers 2 and 3, an access arbitration circuit 4, OR gates 5 and 6, and a JK flip-flop with preset/clear, corresponding to a peripheral device 1. 7 and 8. At the rising edge of the preset inputs (hereinafter referred to as PR) of JK flip-flops 7 and 8, the Q output goes high and the inverted output of Q goes low. At the rising edge of the clear input (hereinafter referred to as CL), the Q output goes low and the inverted output of Q goes high. J input, K input of J-K flip-flops 7 and 8,
The PR input is pulled up. The access request signals 106 and 107 are connected to the CK input terminal and the P1SEL and P2SEL terminals of the access arbitration circuit 4, respectively, and are connected to the Q output and the lock request signals 108 and 10.
9 are connected to OR gates 5 and 6, respectively, and their outputs are connected to the lock input terminal (P1LOC) of the access arbitration circuit 4.
K, P2LOCK). Further, the initialization signal 112 is connected to the RES terminal of the arbitration circuit 4 and the CL terminals of the JK flip-flops 7 and 8. In J-K flip-flops 7 and 8, J input,
When both K inputs are at a high level, Q and the inverted outputs of Q are inverted at the rising edge of the CK access input.

The operation of this embodiment is illustrated in FIGS. 2(a), (b),
This will be explained using timing charts (c), (d), and (e). Now, even if the lock request signals 108 and 109 of each port are inactive, the ports constitute a locking circuit, so ports (1) and (2)
) describes the inactive case. Furthermore, since the arbitration logic itself is exactly the same as the conventional example, only the operation on the port (1) side is described.

At the rising edge of the initialization signal 112,
Q output becomes inactive. Active request signal 1
06, the Q output is inverted and accessed at the rising edge when P1SEL becomes active, and the P1LOCK terminal becomes active through OR gate 7. Therefore, as described in the conventional example, the port is locked until the next access request from port (1). When there is a second access request, P is sent via the access request signal 106.
When the 1SEL terminal becomes active and the Q output inverts to inactive at its rising edge, the port (1
) side is unlocked.

In this embodiment, the access request signal 106
and 107 inputs, P1SEL, P2SE
Connect each terminal of L to the CK of J-K flip-flops 7 and 8.
Although it is connected to the input, it is also possible to connect it to each terminal of P1E and P2E (P1SEL, P2SEL
(This is because the P1E and P2E signals change synchronously.) However, there is no need to particularly explain this example, so it will be omitted.

FIG. 3 is a functional block diagram showing a second embodiment of the present invention. This embodiment supports an access arbitration circuit that does not support lock request signals, and locks two consecutive accesses from port (1) and locks four consecutive accesses from port (2). It shows the case.

As shown in FIG. 3, this embodiment includes bidirectional buffers 2 and 3, an access arbitration circuit 9, 3-bit binary counters 10 and 11, and an OR gate, corresponding to the peripheral device 1. 12 and 13, AND gates 14 and 15, and NOR gates 16 and 17,
The data selector 18 and 19 are provided.

In FIG. 3, in binary counters 10 and 11, access request signals 106 and 10
The input pulse number 7 is counted up and the count value is output to the outputs 0 to 2. Then, at the rising edge of the CL input, the count value becomes 0 (0 to 2 outputs are all “0”).
). In the data selectors 18 and 19,
According to the binary values of the A to C inputs, if it is "0", the Q0 output becomes active, if it is "1", the Q1 output becomes active, and so on. The access request signal 106 on the port (1) side is the C of the binary counter 10.
The outputs 0 to 2 are connected to the data selector 18.
are connected to the A to C inputs of the The Q1, Q2, and Q3 outputs of the data selector 18 are input to the OR gate 16, and its output is connected to the P1SEL terminal of the access arbitration circuit 9. The access request signal 107 on the port (2) side is connected to the C input of the binary counter 11, and its output is 0.
2 are connected to the A to C inputs of the data selector 19. The Q1 to Q4 outputs of the data selector 19 are input to the OR gate 17, and the output is P2 of the access arbitration circuit 9.
Connected to the SEL terminal. The CL input of the binary counter 10 on the port (1) side receives an AND signal of the Q3 output of the data selector 18 and the access completion signal 110 output from the P1ACK terminal, and a signal obtained by inverting the initialization signal 112 by the inverter 20. NOR signal is connected. Similarly, on the port (2) side, the AND signal of the access completion signal 111 output from the Q4 and P2ACK terminals of the data selector 19 and the initialization signal 112
The NOR output of is connected.

The operation of the functional blocks of this embodiment will be explained using the timing chart of FIG. Here, for simplicity, only the operation on the port (1) side is described. When the initialization signal 112 becomes inactive, the CL input of the binary counter 10 becomes high level, and at its rising edge, the value of the counter becomes "0" and is initialized. The binary counter 10 counts up according to the access request signal 106 from port (1), and Q1 to Q3 become active according to its output. This Q1~
Since the OR output of the output signal of Q3 is input to the P1SEL terminal, the access request to P1SEL of the arbitration circuit 9 continues to be active during three accesses. 3
Q becomes active on the second access, and the pulse output from the P1ACK terminal is applied to the AND gate 14 and the NO
Since it passes through the R gate 12 and is input to CL, the counter is cleared at the end of the third access, and the Q
1 to Q3 become inactive, and the P1SEL terminal returns to inactive.

On the other hand, on the port (2) side, four consecutive accesses are locked, so the signal obtained by ORing the four signals Q1 to Q4 in the data selector 19 is
The operation is exactly the same as port (1), except that the input is input to the EL terminal and the counter is cleared at the completion of the fourth access.
Detailed explanation will be omitted.

[0022]

[Effects of the Invention] As explained above, the present invention counts up the number of accesses and locks access to the arbitration circuit during that time, thereby locking peripheral devices that must be accessed continuously using hardware. This has the effect of preventing abnormal operations.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing an operation timing chart in the first embodiment.

FIG. 3 is a functional block diagram showing a second embodiment of the present invention.

FIG. 4 is a diagram showing an operation timing chart in a second embodiment.

FIG. 5 is a functional block diagram showing a conventional example.

FIG. 6 is a diagram showing an operation timing chart when the lock signal is inactive in the conventional example.

FIG. 7 is a diagram showing an operation timing chart when a lock signal is active in the conventional example.

FIG. 8 is a functional block diagram showing another conventional example.

FIG. 9 is a diagram showing an operation timing chart in the other conventional example.

[Explanation of symbols]

1 Peripheral devices 2, 3 Bidirectional buffers 4, 9 Access arbitration circuits 5, 6 OR gates 7, 8 J-K flip-flops 10, 11
Binary counter 12, 13 OR gate 14, 15 AND gate 16, 17 NOR gate 18, 19 Data selector 20 Inverter

Claims (1)

[Claims] 1. A multi-port access control circuit that processes access requests from a plurality of ports by arbitrating access requests through a predetermined access arbitration circuit and exclusively enabling a bidirectional buffer. and logic means for generating, from the output of the counting means, a control signal for locking the arbitration action of the access arbitration circuit. Multiport access control circuit.