JPS5848194A - Address code transmitter/receiver circuit for fire sensor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address code transmitting and receiving circuit for a fire detector.

In recent years, systems have come into use in which a unique address code is assigned to each fire detector, an address designation is sent from the central monitoring device, and a fire detection signal, etc. is sent back from the addressed detector. It was gone. However, the central monitoring device and the fire detector are usually connected by a pair of alarm wires, and the upper and lower alarm codes are serially transmitted and received by the alarm wires. Therefore, the fire detector must convert the serially received signal into a parallel code using a serial-to-parallel conversion circuit constituted by, for example, a shift register, and then check whether it matches its own address code. In order to operate a serial-to-parallel conversion circuit, a timing pulse synchronized with the received signal is required, but generating this timing pulse is not easy. For example, a complicated circuit is required to extract the synchronization frequency component from the received signal train and control the oscillation frequency of the synchronization oscillator, and furthermore, preparation time is required before the synchronization pulse is generated. In other words, it is difficult to generate a synchronization pulse at the same time as reception.
It is not suitable for transmitting and receiving short codes such as address code transmission and reception. Although it is possible to send the synchronization signal through a separate transmission path, it is not economical.

SUMMARY OF THE INVENTION An object of the present invention is to provide an address code transmitting/receiving circuit for a fire detector that can demodulate a received signal without using a timing pulse on the fire detector side and detect address coincidence.

The transmitter/receiver circuit of the present invention has a signal indicating logic @1” and a signal indicating logic @
an address code sending unit that sends out a signal indicating “O” at regular intervals and with a no-signal time provided between the signals;
a demodulation circuit that demodulates the received signal and separately outputs a first pulse train corresponding to the logic @1''' and a second pulse train corresponding to the logic @O"K, and inputs the first and second pulse trains. an OR circuit, a counter that sequentially outputs @1'' to a plurality of output terminals when the output pulse of the OR circuit is input, and a counter that connects the plurality of output terminals of the counter to their respective inputs. a plurality of AND circuits into which the first pulse train is input, and a plurality of 7-lips 70 set by the respective outputs of the plurality of AND circuits.
and a multi-input AND circuit whose inputs are connected to the positive output terminals or negative output terminals of each of the plurality of 7 lip-flops, and each time a coincidence of address codes is detected by the output of the multi-power AND circuit. shall be.

Next, one embodiment of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

That is, a frequency i10 signal F as shown in FIG. 2 is sent from the address code sending unit 1 on the central monitoring device side.

and frequency f are transmitted at regular intervals, and with a no-signal time provided between the signals. The above signal F1
is a signal corresponding to logic ``1'', and signal F is a signal corresponding to logic 10'. Such a signal train, for example, outputs the signal F by the positive pulse of the bipolar RZ signal, and outputs the signal F by the negative pulse.

It can be easily configured to output K. The above signal train is simultaneously received by multiple fire detectors connected to the same alarm line. Each sensor separates and extracts the received signal into signals F1 and Fl using band V wave detectors 2 and 3, and performs envelope detection using wave detectors 4 and 5, respectively. The output of the detector 4 is a first pulse train corresponding to logic=x"ttc, and the output of the detector 5 is a second pulse train corresponding to logic @0"K. The outputs of the detectors 4 and 5 are combined by an OR circuit 6, and the output pulse of the OR circuit 6 is inputted to a counter 7. On the output side of the OR circuit 6,
One pulse is output for either logic @1" or @0", and the counter 7 outputs output terminal P1 for each input pulse.
~Ps K sequentially outputs high level. Carantuff's output terminals PI to P are ANDGOO respectively) A N
Connected to one power of D t~AN D a-,
The other inputs of the antgames ND1 to ANI) are commonly connected to the output of the detector 4.

The outputs of the AND gates AND, -ANDs are connected to the sets of flip-flops FF, -FF, respectively.

On the output side of the flip 70 knobs FFI to FFI, the positive output terminal Q or the negative output terminal - respectively, is a multi-input AND circuit 8.
For 0 input? It is continued. Terminal Q of each 7 lip-flop
The selection of or q corresponds to the unique address code assigned to the sensor. For example, the address code is '1101
In the case of 0011, the connection is as shown in FIG. The multi-input AND circuit 8 outputs a high level when one address code matches (9).

Next, the operation of this embodiment will be explained. Assume that the sensor whose address code is 1101.0011'' is now called. Signals @F, F are sent from the address code sending unit 1 of the central monitoring device as shown in FIG.

FI Ft FI FI FI Ft" is sent out, and the output of the detector 4 of the sensor is "1101001.
A first pulse train of ``1'' is output.A second pulse train of ``00101100'' is output to the output of the detector 5. Therefore, eight consecutive pulses are output from the OR circuit 6. A high level is sequentially outputted to the output terminals P1 to P- of the counter 7 along with the input pulse. Therefore, the first pulse brings the output terminal P1 to a high level and opens the AND gate ANDI. At this time, the detector 4
The output pulse of passes through the AND gate ANDst- and sets the flip-flop FF.
The + positive output terminal Q goes to the low level and maintains that state thereafter. Next, by the second pulse, the output terminal Pa of the Carantuff becomes high level, the antagonist ND is opened, and the output pulse of the detector 4 sets the 7-lip FF, and the positive output terminal Q. is at a high level. Next, the third pulse similarly opens the AND gate A N D s, but at this time the detector 4 is not outputting a pulse. Therefore, flip-flop FF
m is not set, and a high level is output from the negative output terminal q and input to the multi-input AND circuit 8. Similarly, 4
~8th pulse causes flip-flop FFs
~FF are set corresponding to the first pulse train, respectively. In other words, the first pulse sequence is @1101001
1'', all eight inputs of the multi-input AND circuit 808 are at high level, and a match of address codes is detected.

The above operation does not require one timing pulse unlike a general shift register. That is, since there is no need to synchronize between the transmitter and the receiver, there is no need for a preparation period for synchronization, and it can be configured with a simple circuit.

As mentioned above, in the present invention, signals corresponding to address codes are transmitted in series with intervals between the signals, and on the fire detector side, the received signals are separated and demodulated, and the signals corresponding to the logic @1'' are transmitted. , and a second pulse train corresponding to logic @0″.
The first and second pulse trains are combined by an OR circuit and input to a counter, and the output of the counter sequentially opens a plurality of AND gates. , a plurality of flip-flop circuits are configured to be set sequentially in response to the presence or absence of pulses in the pulse train, so the positive output terminals or negative output terminals of the plurality of flip-flops are set in accordance with the address code. By inputting it to an input AND circuit, it is possible to detect a match between address codes.

This transmitting/receiving circuit does not require a receiving timing pulse and does not require synchronization between transmitting and receiving, so it has the advantage that it can be constructed with a simple circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram including a partial logic circuit diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram showing an example of a transmission signal used in the above embodiment. . In the figure, 1... transmitter, 2, 3... bandpass filter, 4.5... detector, 6-... OR circuit, 7...
Counter, 8...Multi-input AND circuit, ANDs~A
NDs...antogame), FFr~FF1...flip-flop. Representative of Nittan Co., Ltd. Patent attorney Resident 1) Toshi So (and 2 others)

Claims (1)

[Claims] an address code transmitter that sends out a signal indicating logic ``1'' and a signal indicating logic ``0'' at regular intervals and with a signal time provided between the signals; and demodulating the received signal. a demodulation circuit that separately outputs a first pulse train corresponding to logic @1'' and a second pulse train corresponding to logic @θ''; and an OR circuit that inputs the first and second pulse trains. , a counter that sequentially outputs 11'' to a plurality of output terminals as if the output pulse of the OR circuit is input, and a plurality of output terminals of a Mukuro counter are connected to each input, and the other input is connected to the above-mentioned 11''. A plurality of AND circuits into which a pulse train is input, a plurality of 7-lip 70-tubes set by the respective outputs of the plurality of AND circuits, and the positive output terminal or negative output terminal of each of the plurality of 7-lip-flops are connected to the input. 1. An address code transmitting/receiving circuit for a fire detector, comprising: a multi-input AND circuit; and detecting coincidence of address codes based on the output of the multi-input AND circuit.