JPS5937748A - Receiver for optical transmission - Google Patents

Abstract

PURPOSE:To receive a large amount of data without any error and to simplify the constitution of a device, by using a clock pulse as a synchronizing signal, judging the extraction timing of a targeted data from the counted values of the pulse, and detecting abnormality from the break of time longer than a specific time for a transmitted signal. CONSTITUTION:A transmitter 1 and a receiver 3 are connected through an optical transmission line 2, optical information from the transmission line 2 is demodulated by the demodulating circuit 32 of the the receiver 3, and a clock/data separating circuit 34 separates data and the clock. This separated clock is counted successively by a counter circuit 35 by a start signal ST from a starting circuit 33 and the result is applied the counted value as address data to a control circuit 36 and also sends out a parity signal to a parity checking circuit 38. Then, the extraction timing of target data is judged from the counted value by a latch circuit 37, address setter 44, coincidence circuit 43, etc. Further, the circuit 38, etc., detect abnormality from the break of time longer than the specific time for a transmitted signal, and a large amount of data without any error is received.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an optical transmission/transmission receiving device that can receive a large amount of data sent through an optical transmission line using optical fibers at high speed and without error.

Transfers data from multiple terminals to the control unit (master station) that obtains detection information (temperature, drive position, pressure signals, etc.) from various sensors, etc., or controls control equipment connected to each terminal. In systems that require large amounts of data transmission, such as receiving control commands from the control unit,
By using an optical transmission method that can transmit a large amount of data using one or several wires, a system can be configured with a minimum number of wires.

As a conventional optical data transfer means, as shown in FIG.
, (b), (C), and (d), pulse transmission methods such as unipolar NRZ, unipolar RZ, and GMTlJ)Ml were used. However, these methods have disadvantages when data is transferred randomly. That is,
There is no problem when the number of communication bits is short, but when the number of bits exceeds several hundred, the electronic components that make up the oscillation circuit used in the transmitter and receiver have temperature characteristics, voltage differences,
Variations occur due to changes over time, etc. As a result, the timing of the internal clocks on the transmitting and receiving sides does not match exactly.
Timing shifts occur little by little from the start of data transfer, and data cannot be read after the number of bits at that point.

To solve this problem, in the past, data with a long number of bits was sent in sections of a certain length, or sent in combination with a synchronization block signal, or while constantly making fine adjustments. Countermeasures such as synchronizing the clocks were taken. However, in this case, the transmission time will be longer and
Alternatively, there is a drawback that the device becomes complicated and large.

SUMMARY OF THE INVENTION An object of the present invention is to provide an optical transmission receiving apparatus that can receive a large amount of data without error and eliminates the above-mentioned conventional drawbacks.

The present invention provides a clock pulse for synchronization in which pulse signals for at least the number of data are sent out 1111 times at regular time intervals, and one data inserted after the clock pulse, from among the transmitted data. When extracting the target data, the timing of extracting the target data is determined from the count value of the clock pulse while the r1 clock pulse is synchronized (IT), and an abnormality in the transmission system is detected from the interruption of transmitter 4 for a predetermined time or more. This is a book written by Shishida that can be detected easily.

FIG. 2 is a data transmission mat according to the present invention,
■The frame consists of an idling part Jl)L, a start bit S'J''R, a data part 1)ATA, a parity bit P)1., and a no-signal part (time width 1゛0). The result is as shown in Fig. 3.For convenience of explanation, the case of 15 data is shown here, but
It is not limited to the number of data. In the above, we have shown a case in which the same frame of information is repeatedly transferred by providing a non-signal section, but this is done in consideration of improving the reliability of transmission. good.

The idling portion IDL is a section in which a plurality of clock pulses (K) are sent out at regular intervals, whereby the timing of the clock is first identified.

Then the start pulse is sent) 8 T n, is the data pulse? l (This is the starting point for counting the number of seconds.

That is, the number of clock signals sent after the start bit S T H corresponds to the number of data, and the receiving side can recognize the reception timing of the required data. For example, if data 2 is required on the receiving side, it can be captured after the second CK is issued after the STR is sent.

Note that even if there is no data to be transmitted in the corresponding area, only the clock CK is transmitted (if not transmitted, the order of the data will be shifted). Parity bit PR1 after data area
is transmitted, and the parity bit for this bit is set as I" level depending on whether the number of H (high) level pulses of all data bits is even or odd.Furthermore, the non-signal part at t is, for example, 10 clocks are allocated.This no-signal part causes a timing shift when reception starts in the middle of transmission (that is, when the power on the receiving side is turned on within the signal transmission period of one frame), and from then on. This is provided to prevent all of the signals received during the period from continuing to cause errors.On the receiving side, the duration of this no-signal section is set to 1'n (for example, 10 clocks). For example, if there are 5 clocks, the reception system will be established for subsequent transmissions, and the clock will be synchronized from the subsequent clock pulse. Also, if there is no signal for more than 10 hours, the optical fiber will be disconnected. , disconnection of the connector, etc. can be determined.

In this way, synchronization can be achieved by determining timing based on clock pulses, so even if the amount of data is large, complete synchronization can be achieved and transmission reliability can be improved.

FIG. 4 is a block diagram showing an embodiment of the present invention, in which the transmission format shown in FIG. 3 is further modulated to a half period, and a signal train is transmitted from the transmitting device 1 via the optical transmission line 2. The configuration of a receiving device that receives incoming data is shown. 3 receiving devices, optical/electrical conversion circuit 31, demodulation circuit 32. Start circuit 33, clock/data separation circuit 34, counter circuit 35, control circuit: (6, latch circuit 37, validatoric circuit 38, output control circuit 39, latch circuit 40, parity error display section 41
, abnormality display section 42, matching circuit 43, address setting device 44
It consists of

The optical/electrical conversion circuit 3 converts the optical information transmitted through the optical transmission line 2 into an electrical signal and converts it into an electrical signal. The modulation signal shown in Figure i'1.5 is used. The demodulation circuit 32 converts the modulated signal into a signal train separated into a clock and data as shown in FIG. The start circuit 33 measures the length of the no-signal state and, after a certain period of time, sends out a start signal that is the starting point of clock counting.

The clock/data separation circuit 34 separates the signals transmitted in series in a predetermined order into knock and data and outputs each. The counter circuit 35 receives the start signal FJ 11 output from the start circuit 33 The clocks that are activated and output from the clock/data separation circuit 34 are sequentially counted 7, and the counted value is constantly sent to the control circuit 36 as address data, and after counting all the clocks corresponding to the data, it is sent to the parity check circuit 38. Sends a parity signal.Control circuit 3
6 synchronizes the clock of a built-in internal clock circuit (not shown) with the clock pulse output from the clock/data separation circuit 34 to output a comparison pulse, and synchronizes the timing of this comparison pulse with the data pulse. The comparison is made and the presence or absence of the data pulse is output to the latch circuit 37. Further, the control circuit 36 transfers the address signal to the latch circuit 3.
This address signal is output to counter circuit 35.
This is to transfer the address data output from.

The parity check circuit 38 counts the data pulses output from the control circuit 36 to determine whether the numbers are even or odd, and uses the parity signal from the counter circuit 35 to distinguish internal even and odd data from the parity data from the control circuit 36. Compare and match according to the specified conditions (
or mismatch), it is determined to be positive, and a gate-on signal is sent to the output control circuit 39, and all data held in the latch circuit 37 is transferred to the latch circuit 40. Matching circuit 43
latches the designated data in the latch circuit 37 only when the address setter 44 sets it (that is, the CK number of the data to be retrieved is designated). The data held in the latch circuit 37 is transferred to the latch circuit 40 by the signal output from the output control circuit 39 and the parity check circuit 38.
Transfer to.

In the above configuration, a signal received via the optical transmission line 2 is converted into a modulated signal as shown in FIG. 5 by the optical/electrical conversion circuit 31, and then demodulated into a signal as shown in FIG. 3 by the demodulation circuit 32. . Incidentally, if the signal carried on the optical transmission line 2 is modulated without using the signal format shown in FIG. 3, the transmission frequency can be set to ]/2 in order to improve responsiveness, etc.

Figure 3 (or Figure 5) output from the demodulation circuit 32
A signal such as 1 is separated into a clock and data by a clock/data separation circuit 34, and then individually outputted to a control circuit 36. On the other hand, a start signal is created by the start circuit 33, and from this start signal K S
When T Il comes, a start signal is sent to the counter circuit (5). Note that if no data signal (CK and each data) including STR is input within a certain period of time,
The start circuit 33 determines that a break in the optical fiber constituting the optical transmission line 2 is a failure in the system leading to the start circuit 32 of the transmitting device or the receiving device 3, and sends an abnormal signal to the abnormality display unit 2, indicating the abnormality. make them do Counter circuit 3
5 counts the clock CK from the time when the start signal is received, and every time the count value is updated, the address data (that is, the address of the data number)
and a parity signal to the validity check circuit 38. The control circuit 36 generates a comparison pulse while synchronizing the internal clock with the input data and clock, and compares the comparison pulse with the input data.
l) It is assumed that data exists if the %AND condition is established. If data is present, the data is transferred to the latch circuit 37 together with the address data output from the counter circuit 35. Further, when the parity check circuit 38 determines that the data is normal (based on the parity signal from the counter circuit 35, by comparing it with the even and odd data in the control circuit 36 and the parity check circuit 37), The gate of the output control circuit 39 is opened and the data held in the latch (b) path 37 is transferred to the latch circuit 40. If it is determined that the data is incorrect, a warning is displayed on the parity error display section 41, and the previous data held in the latch circuit 40 is output. The data output from the latch circuit 40 is used for various controls or as information.

In addition, in the above explanation, for convenience, the case where one receiving device is connected to the optical transmission line 2 has been shown, but if the multiple data being transmitted (data 1 to data n) Alternatively, one receiving device may read iV number of data.

As is clear from the above, according to the present invention, by synchronizing with the clock pulse, a large amount of data can be received without error, thereby improving the reliability of transmission.

[Brief explanation of drawings]

Figures 1 (3), (b), (C), ((1) is a transmission format diagram showing the conventional pulse transmission method, Figure 2 is a data transmission format diagram according to the present invention, and Figure 3 is a transmission format diagram showing the conventional pulse transmission method. 4 is a block diagram showing an example of the present invention, and FIG. 5 is a power signal waveform diagram of each part of the embodiment of FIG. 4.1. ... Transmitting device, 2... Optical transmission line, 3... Receiving device, 31... Optical/1y, air conversion circuit, 32.
...Demodulation circuit, 33...Start circuit, 34...
- Clock/data separation circuit, 35...counter circuit. 36... Control circuit, 37.40... Latch circuit, 38... Parity check circuit, 39... Output control circuit, 41... Parity error display section, 42... Abnormality display section, 43 ...matching circuit. 44...Address setting device. Agent Patent Attorney Kenzo Matsuura

Claims (2)

[Claims] (1) A receiving device that is connected to an optical transmission line that transmits an optical signal consisting of one frame by ensuring a transmission space for -data between synchronization clock pulses that are sequentially output at predetermined intervals. , a signal separation circuit that separates an electrical signal obtained by demodulating the optical signal transmitted from the optical transmission line into a data component and a clock component, and address data generated to identify each block of data from the data acquisition start point. and a control unit that outputs received data corresponding to the address data, and a latch unit that latches the data from the control unit when the address data output from the control unit and a preset data address match. 1. A receiving device for optical transmission, comprising: a parity check circuit that outputs data in the latch section only when the data in the latch section is genuine. (2) A patent characterized in that means is provided for determining and displaying an abnormality in the yarn path or device based on the fact that no signal is received from the optical transmission line within a certain period of time after the no-signal state has elapsed. An optical transmission receiving device according to claim 1.