JPS584792B2 - densimetronome - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a highly accurate and highly stable electronic metronome.

Conventional mechanical metronomes or CR oscillation type electronic metronomes not only have low accuracy, but also have large setting errors, making it difficult to accurately obtain the desired tempo.

As a solution to this problem, a device that uses a tuning fork oscillator and divides its output to obtain the desired tempo has appeared, but since the frequency of the tuning fork oscillator is relatively low, it is difficult to obtain This has the disadvantage that the tempo provided has a relatively large error with respect to the required tempo.

The present invention eliminates the above drawbacks by using a crystal oscillator with a higher frequency than a tuning fork oscillator, adding pulses to the output, and then dividing the frequency.

FIG. 1 is a block diagram of an embodiment of the invention.

1 is a crystal oscillator, which oscillates at 32.768Hz.

2 is a pulse adder, consisting of 5 stages of 2-divider circuits, with 32 inputs.
An arbitrary number of pulses from 19 to 29 can be taken out for each pulse.

Reference numeral 3 denotes a fixed frequency divider, which consists of nine stages of frequency divider circuits by 2 and a frequency divider by 5, and its frequency division number is 29×5=2,560.

4 is a variable frequency divider circuit, consisting of 4 stages of 2 frequency divider circuits,
Frequency division numbers of 3, 4, 6, 8, and 12 can be obtained.

Now, if the number of pulses taken out by the pulse adder is P1 and the division number of the variable frequency divider is V, then the tempo signal T is (However) On the other hand, according to the mechanical metronome JIS standard, it is 40 to 20.
A tempo of 39 steps of 8 (beats/minute) has been determined, and when P and V are calculated for this, the results are shown in Table 1.

FIG. 2 is a circuit diagram of an embodiment of a pulse adder, in which 5 is an input terminal, 6 to 10 are flip-flops, 11 to 19 are 2-input AND gates, 20 is a switch with 4 circuits and 11 contacts, and 21 is a 5-channel switch. Input OR gate 22 is an output terminal.

The operation of the circuit will be briefly explained with reference to FIG.

Signal Q coming from input terminal 5.

Assuming that is a waveform like A, the positive output Q1 of 6 will be the mouth, and the negative output will be like the waveform Ha.

And the output of 11 is Q. The product of Q1 and Q1 becomes 2, which is 15
The output of is the product of Qo and Q1.

Next, the positive output Q2 of 7 becomes , and the inverse output 2 becomes g.

And the output of 12 is Q. The product of -Q1 and Q2 is Q, and the output of 16 is Q.

-It is the product of Q1 and Q2.

Furthermore, the positive output Q3 of 8 becomes nu, and the inverse output Qs becomes ru.

And the output of 13 is Q. - The product of Q1/Q2 and Q3 is Q, and the output of 17 is the product of Qo-Q1/Q2 and Q3, which is Wa.

Furthermore, the positive output Q4 of 9 is a force, and the reverse output Q4 is yaw.

And the output of 14 is Q.

The product of -Q1, Q2, Q3 and Q4 is evening, and the output of 18 is Q.

The product of -Q1, Q2, Q3 and Q4 is YES.

Furthermore, since the anti-output ζ of 10 becomes tsu, this and Q.

-Q1, Q2, and Q4 result in an output penalty of 19.

Looking at the outputs 15, 16, 17, 18, and 19 (marked with * in the diagram), 16, 8, and 4 outputs are produced, respectively, for 32 Qo pulses. There are three pulses, two pulses, and one pulse, and their positions are such that they do not overlap.

Therefore, by adding 15 to 19 outputs as appropriate, any number of pulses up to 31 can be obtained for 32 input pulses.

In the example, 19 to 29 switches are required, so 20 switches are required.
This is selected by the OR gate 21, and the pulses are added together and taken out from the output terminal 22.

FIG. 4 is a circuit diagram of an embodiment of a variable frequency divider, in which 23 is an input terminal, 24 to 27 are flip-flops, 28 is a 2-input NAND gate, 29 is a 2-circuit 5-contact switch,
30 is an output terminal.

First, to explain the case of frequency division by 3, the output Q6 of 24
When the pulse enters from the input terminal 23, the output Q7 of 25 advances to 00, io, ol, and at the moment it reaches 11, the output of the NAND gate 28 becomes 0, and the count reaches 24.
．． When the reset occurs at 25, it returns to 00 seconds.

In other words, since 24 and 25 constitute a ternary counter, if the output of 25 is taken out, the input frequency will be divided by three.

Next, in the case of frequency division by 4, the output of the NAND gate 28 is 24,
Since it is separated from the reset circuit of 25, when the output of 25 is taken out, the input frequency is divided by 4.

In the case of frequency division by 6, 24 and 25 constitute a frequency division circuit by 3, and the output of 25 is divided by 2 by 26 and taken out, so the input frequency is divided by 6.

In the case of frequency division by 8, 24 and 25 become 4 frequency division circuits, which are further divided into 2 by 26 and extracted.

In the case of frequency division by 12, configure a frequency division circuit by 3 with 24.25,
This is further divided into four by 26 and 27.

By configuring the metronome as described above, errors caused by frequency division can be completely eliminated.

Of course, some fluctuation occurs in the tempo signal due to the pulse adder, but this does not exceed one output waveform of the crystal oscillator, that is, about 30 μsec, and there is no problem at all in practice.

Furthermore, it is possible to obtain a highly accurate and highly stable metronome, which is a feature of a crystal oscillator, and its practical utility is extremely large.

[Brief explanation of drawings]

1 is a block diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of an embodiment of a pulse adder, FIG. 3 is an explanatory diagram of the operation of the pulse adder, and FIG. 4 is an embodiment of a variable frequency divider. FIG.

Claims (1)

[Claims] 1. A crystal oscillator having a resonator of several tens of KHz, and a pulse adder that divides the output of this crystal oscillator with several stages of 2-divider circuits, converts the output of each stage into pulses that do not overlap with each other, and adds the pulses. It is characterized by comprising a frequency divider that divides the output of the pulse adder into a required tempo signal, a plurality of flip-flop stages, a plurality of AND gate groups, and a plurality of switch groups for configuring the pulse adder. Electronic metronome.