JPS5846062B2 - Semiconductor device and its manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an NPN (or PNP) type transistor;
The present invention relates to a semiconductor device in which a PNP (or NPN) type transistor having a base and collector internally connected to its emitter and base, respectively, is formed, and improvements in a method for manufacturing the same.

As the above-mentioned semiconductor device, one having the configuration described below with reference to FIG. 1 has been proposed.

That is, a semiconductor substrate 3 having, for example, an N+ type semiconductor layer 1 having a relatively small specific resistance and an N- type semiconductor layer 2 having a relatively large specific resistance disposed thereon.
has.

Thus, it extends into the semiconductor layer 2 of the semiconductor substrate 3 from the upper surface side to the semiconductor layer 1 side to a depth that does not reach thereto.

P+ type semiconductor regions 4 and 5 are formed, and an N+ type semiconductor region 6 is formed extending from the upper surface side of the semiconductor layer 2 to the semiconductor layer 1 side to a depth reaching thereto. A P-type semiconductor region 7 is formed extending from the upper surface side of the layer 2 to the semiconductor layer 1 side to a depth that does not reach thereto and is connected to the semiconductor region 5.

On the other hand, in the semiconductor region T, an N+ type semiconductor layer 8 is formed from the top surface side.

In addition, electrodes 9, 10.
1 (not shown) and 12 are connected.

The above is the configuration of the above-mentioned semiconductor device that has been conventionally proposed.

A semiconductor device having such a configuration includes an NPN transistor U1 having the semiconductor region 8 as a collector, the semiconductor region 7 as a base, and the semiconductor layer 2 as an emitter; 4 as an emitter.

In this case, the collector of the transistor U1 is connected via the electrode 12, the base is connected to the semiconductor region 5 and the electrode 10, and the emitter is connected to the semiconductor layer 1, the semiconductor region 6, and the electrode 11 (not shown) connected thereto. and have a configuration in which they are each connected to the outside.

Also, the collector of transistor U2 is connected to transistor U1.
The base of the transistor U1 is internally connected to the emitter of the transistor U1, and the emitter of the transistor U2 is connected to the outside via an electrode 9.

Therefore, the conventional semiconductor device shown in FIG. 1 constitutes a so-called ■■L circuit (integrated injection logic circuit), as shown in FIG. 2.

However, the conventional semiconductor device shown in FIG. 1 has - The transistor U2 requires a relatively large area on the semiconductor substrate 3 to be constructed.

Therefore, in the case of the conventional semiconductor device shown in FIG. 1, there is a certain limit to miniaturization of the device.

Further, in the conventional semiconductor device shown in FIG. 1, since the base of the transistor U2 is formed of a part of the semiconductor layer 2, there is a certain limit to reducing the width of the base.

For this reason, in the case of the conventional semiconductor device shown in FIG. 1, there was a certain limit to increasing α of the transistor U2 to a large value.

Further, in the conventional semiconductor device shown in FIG. 1, the emitter of the transistor U1 is formed of the N- type semiconductor layer 2, so the emitter injection efficiency is relatively low.

Therefore, in the case of the conventional semiconductor device shown in FIG. 1, there is a certain limit to increasing β of transistor U1 to a large value, and there is also a certain limit to reducing power consumption to a small value. It had

Furthermore, in the conventional semiconductor device shown in FIG. 1, since the emitter of the transistor U1 is formed of the N-type semiconductor layer 2, the emitter resistance is relatively large, and therefore the emitter-base junction capacitance is Charge/discharge time is relatively long.

Therefore, in the case of the conventional semiconductor device shown in FIG. 1, there is a certain limit to the gain bandwidth, and therefore there is a certain limit to the response speed. It had drawbacks such as.

Further, in the conventional semiconductor device shown in FIG.
and 5; semiconductor region 6: semiconductor region 7; and a process using a mask to obtain the semiconductor region 8, a process using a mask to form a window in the insulating layer 13, and electrodes 9, 1.
0.11 (not shown) and 12.

Therefore, in the case of the conventional semiconductor device shown in FIG. 1, six processes using a mask are required to manufacture it.

Therefore, the conventional manufacturing method for obtaining the conventional semiconductor device shown in FIG. 1 has certain limitations, even though the process is simplified.

Therefore, the present invention provides an NPN (or PNP) type transistor which does not have the above-mentioned drawbacks, and a PNP (or NPN) type transistor having a base and a collector internally connected to its emitter and base, respectively. This paper aims to propose a new semiconductor device and a new manufacturing method thereof, which will become clear from the detailed explanation below.

First, with reference to FIG. 3, the semiconductor device and its manufacturing method according to the present invention will be explained in detail by way of an example of the manufacturing method.

In an example of the method for manufacturing a semiconductor device according to the present invention, the third
As shown in Figure A, it is made of silicon, and the upper surface 31 is (10
For example, an N+ type semiconductor layer L1 having a relatively low resistivity and formed to have an O) plane is prepared in advance.

Then, on the upper surface 31 of this semiconductor layer L1, for example, by epitaxial growth, as shown in FIG. 3B,
A semiconductor substrate made of silicon, forming a P-type semiconductor layer L2 whose upper surface 32 is a (100) plane, and thus having a semiconductor layer L1 and a semiconductor layer L2 disposed thereon. form 33.

Next, on this semiconductor substrate 33, that is, the semiconductor layer L2
As shown in FIG. 3C, an oxide layer 34 mainly composed of silicon dioxide is formed as a first oxide layer thereon by, for example, a thermal oxidation method, as shown in FIG. 3C.

Next, a nitride layer 35 mainly made of silicon nitride is formed as a first nitride layer on this oxide layer 34 by, for example, a thermal decomposition method, as shown in the third diagram.

Next, the nitride layer 35 is selectively etched so that the nitride layer 35 has a width W1, as shown in FIG. 3 E-1 and E-2.
A nitride layer M1 having a structure in which windows 36 extending in a lattice shape are formed is formed as a second nitride layer.

Next, by over-etching the oxide layer 34 using the nitride layer M1 as a mask, the oxide layer 34 is etched with a width W1 corresponding to the window 36, as shown in FIG. 3F.
Width W2 slightly larger than width W1 centered on the center position of
The oxide layer M2 having a structure in which windows 38 extending in a lattice shape are formed, that is, the nitride layer M2 included in the nitride layer M1 when viewed from above, is replaced by a second oxide layer M2. Form as layers.

Next, since the semiconductor layers L2 and Ll are formed so that their upper surfaces 32 and 31 are both (ioo) planes, the semiconductor substrate 33 made of the semiconductor layers L2 and Ll is anisotropically etched. Taking advantage of the fact that the nitride layer M1 and the oxide layer M2 are used as masks,
The semiconductor substrate 33 consisting of the semiconductor layers L2 and Ll is subjected to an anisotropic etching process, and as shown in FIG.
In the above, the semiconductor layer L has a width W3 which is considerably larger than the width W2, centered on the center position of the width W1 of the window 38.
The width gradually narrows from the width W3 toward the first side, and on the lower surface of the semiconductor layer L2, the hole 41 (its The inner surface is inclined by approximately 54 degrees with respect to the upper surface 32), and the width W4 of the hole 41 on the semiconductor layer L1 side matches the width W4 of the semiconductor layer L1 on the upper surface 31 of the semiconductor layer L1. The width gradually becomes narrower from the width W4 toward the bottom on the side opposite to the layer L2 side, and then the semiconductor layer L1
A groove 42 having an inverted triangular cross section (the inner surface thereof is also inclined by approximately 54° with respect to the upper surface 31) is formed,
As a result, a groove G having an inverted triangular cross section is formed in the semiconductor substrate 33 by the hole 41 and the groove 42 .

Next, as shown in FIG. 3H, a nitride film 45 mainly made of silicon nitride is formed on the surfaces facing the outside of the nitride layer M1 and the oxide layer M2 and on the inner surface of the groove G by, for example, a thermal decomposition method.
form.

Next, using the nitride layer M1 as a mask, ions of an inert element, such as argon, are vertically implanted from above.
As shown in FIG. 3, ion implantation regions are formed in regions 46 and 48 of the nitride film 45 that are not in the shadow of the nitride layer M1.

Next, taking advantage of the fact that the ion implantation regions 46 and 48 of the nitride film 45 are more easily etched than the other regions 47, the ion implantation regions 46 and 48 are etched as shown in FIG. 3J. As shown, the region 47 of the nitride film 45 is left as the nitride film M3, and the lower part of the inner surface of the groove G is exposed as a first exposed portion.

Next, by thermal oxidation treatment, as shown in FIG. 3K, an insulating layer 49 made of an oxide mainly composed of silicon dioxide is formed on the first exposed portion of the lower inner surface of the groove G of the semiconductor substrate 33. It is formed as one insulating layer.

Next, the nitride film M3 and the nitride layer M1 are removed by an etching process, as shown in the third figure, to expose a region other than the lower part of the inner surface of the groove G as a second exposed portion.

Next, by vertically implanting nitrogen ions from above using the oxide layer M2 as a mask, as shown in FIG. 3M,
A second groove formed in the area excluding the lower part of the inner surface of the groove G mentioned above.
An ion implantation region 51 is formed in the exposed portion of the oxide layer M2 that is not shaded by the oxide layer M2.

Next, by thermal oxidation treatment, as shown in FIG. 3N, in the region 50 shaded by the oxide layer M2 of the second exposed portion formed in the region excluding the lower part of the inner surface of the groove G, An insulating layer 52 made of an oxide mainly composed of silicon dioxide is formed as a second insulating layer, and the ion implantation region 5
1, an insulating layer 51' mainly made of silicon dioxide,
Formed as a third insulating layer.

Next, the insulating layer 51' is removed by etching, so that the insulating layer 4 is etched on the inner surface of the groove G, as shown in FIG.
9 and 52 are left as the insulating layer M4, and an exposed portion 53 is formed on the inner surface of the groove G as a third exposed portion.

Next, impurity ions, such as arsenic ions, which provide N type are implanted from above into the semiconductor layer L2 so as to face the upper surface 32 of the semiconductor layer L2 at a required distance, as shown in FIG. 3P. and a side surface 55 facing the inner surface of the groove G with a required distance therebetween. A semiconductor region Q1/ is formed.

Next, by using the insulating layer M4 made up of the insulating layers 49 and 52 as a mask, the impurity giving N type is thermally diffused.
As shown in FIG. 3Q, in the semiconductor layer L2, an N-type layer extends from the exposed portion 53 of the trench G to a depth reaching the semiconductor layer L1 and a depth reaching the semiconductor region Ql'. A semiconductor region Q5' is formed.

Note that at this time, the semiconductor region Q1' is activated,
This results in an N+ type semiconductor region Q1 whose boundary is indistinguishable from the semiconductor layer L1.

Next, on the exposed portion of the groove G of the semiconductor region Q5, a semiconductor layer made of, for example, silicon doped with a P-type impurity is grown by an epitaxial growth method. Means including forming a semiconductor layer made of, for example, polysilicon doped with impurities over the entire surface including the oxide layer M2 until the trench G is filled, and then removing the semiconductor layer on the oxide layer M2 As shown in FIG. 3R, the groove G is doped with P-type impurities at a high density, has a flat upper surface, and has a relatively small resistivity. Semiconductor layer L
3 is formed in connection with the semiconductor region Q5.

Next, by heat treatment, the N-type impurity contained in the semiconductor region Q5 is introduced into the region under the insulating layer 52 forming the insulating layer M4 of the semiconductor layer L2, and the N-type impurity contained therein is introduced into the semiconductor layer L2. , while forming an N-type semiconductor region Q6 having a configuration in which the semiconductor region Q5 extends within the semiconductor layer L2 as a sixth semiconductor region, in the semiconductor region Q6,
From the semiconductor layer L3, the P-type impurity contained therein is
The semiconductor layer L1 and the semiconductor region are introduced through the exposed portion of the groove G indicated by 56, and are thus introduced from the inner surface side of the groove G in a continuous manner with the semiconductor layer L3, as shown in FIG. 3S. A P to P+ type semiconductor window hole Q2 extending to a depth reaching Q1 and an insulating layer 52 forming an insulating layer M4.
An N-type semiconductor region Q3 extending from the inner surface of the groove G to a depth reaching the semiconductor region Q1 below and connected to the semiconductor region Q2 is formed as a second and third semiconductor region, respectively. .

At this time, an insulating layer made of an oxide mainly composed of silicon dioxide is formed on the flat upper surface of the semiconductor layer L3, and the oxide layer M2 further grows, as shown in FIG. 3S. , an insulating layer 5 made of an oxide mainly composed of silicon dioxide and extending uniformly over the semiconductor layers L2 and L3.
8 is formed.

Next, by selectively etching the insulating layer 58, the insulating layer 58 is etched as shown in FIG. a window 65 having an inner edge spaced along the
to be drilled.

Next, as shown in FIG. 3U, for example, polysilicon containing a high concentration of N-type impurities is formed over the entire surface of the semiconductor layer L20) facing the window 65 and the insulating layer 58 by, for example, a thermal decomposition method. Forming a semiconductor layer 66 consisting of
A semiconductor layer 67 made of polysilicon containing no impurities is similarly formed on the semiconductor layer 66 by, for example, a thermal decomposition method, and thus a semiconductor layer 68 is formed by the semiconductor layers 66 and 67.

Next, as shown in FIG. 3V, an insulating layer 69 made of silicon dioxide, for example, is formed on the semiconductor layer 68.

Next, by selectively etching the insulating layer 69, as shown in FIG. The mask M5, which extends in the front-rear direction and is located opposite to the surface facing the window 65 of the layer L2, is attached to the insulating layer 69.
form from.

Next, by etching the semiconductor layer 68 using the mask M5, as shown in FIG.
A semiconductor layer 71 having an inverted trapezoidal cross section is formed below.

Next, the mask M5 is removed from above the semiconductor layer 71 by etching, as shown in FIG. 3Y.

Next, as shown in FIG. 3Z, an insulating layer 72 made of, for example, silicon nitride and extending uniformly over the semiconductor layer 71, the semiconductor layer L2, and the insulating layer 58 is formed by, for example, a pyrolysis method. .

Next, by heat treatment, the N-type impurity contained in the semiconductor layer 66 forming the semiconductor layer 68 described above, which is the semiconductor layer 71, is removed from the semiconductor layer 66 forming the semiconductor layer 68 described above. Therefore, as shown in FIG. 3AA, the semiconductor layer 71
From this, a semiconductor layer 73 containing a high concentration of N-type impurities is formed, and the N-type impurities contained in the semiconductor layer 73 are
The N-type semiconductor region Q4 is introduced into the region under the semiconductor layer 73 in the semiconductor layer L2, thereby forming an N-type semiconductor region Q4 on the upper surface 32 side in the semiconductor layer L2 as a fourth semiconductor region.

Next, by vertically implanting P-type impurity ions from above, as shown in FIG.
6, an ion implantation region is formed.

Next, by etching, the region 75 is left as an insulating layer 77, as shown in FIG. The front and rear surfaces and left inner surface of the window 65,
It faces a window 78 formed by the right outer side surface of the insulating layer 77.

Next, by vertical implantation of P-type impurity ions from above, the upper surface 32 in the semiconductor layer L2 is
A P-type semiconductor region Q7 is formed at a position facing the side window 78).

Next, a window (
As shown in FIG. 3AE, the electrode 80 extending over the semiconductor layer 73 and the semiconductor region Q7 and the insulating layer 58, and the semiconductor layer L3
A conductive layer 81 is formed which is connected through the window drilled in the insulating layer 58 described above, but is not connected to the semiconductor layer 73 because the electrode 80 extends over the semiconductor layer 73.

Next, by selectively etching the conductive layer 8H, as shown in FIG. 3 AF-1 and AF-2, it is connected to only one of the semiconductor regions Q7 and extends onto the insulating layer 58. The electrode 82 and the electrode connected only to the semiconductor layer L3 and extending onto the insulating layer 58 (not shown)
4), and an N-type semiconductor region connected to the semiconductor layer L1 and facing the upper surface side of the semiconductor layer L2 is formed at an appropriate position in the semiconductor substrate, and an electrode is attached to this, Alternatively, an electrode (not shown, but referred to as 83) is connected to the semiconductor layer L1 by attaching an electrode to the surface opposite to the upper surface of the semiconductor layer L1.

As described above, an example of the target semiconductor device according to the present invention is manufactured.

As described above, an example of a semiconductor device according to the present invention and an example of its manufacturing method have been clarified.

Such a semiconductor device according to the present invention (shown in FIGS. 2 AF-1 and AF-2) is an NPN transistor having a semiconductor region Q4 as a collector, a semiconductor layer L2 as a base, and a semiconductor region Q1 as an emitter. U1 and a PNP transistor U2 having the semiconductor layer L2 as the collector, the semiconductor region Q3 as the base, and the semiconductor region Q2 as the emitter. is connected to the outside through the semiconductor region Q7 and the electrode 82, and the emitter is connected to the outside through the semiconductor layer L1 and the electrode 83 (not shown) connected thereto, and the collector of the transistor U2 is internally connected to the base of the transistor U1, the base is internally connected to the emitter of the transistor U1, and the emitter is externally connected via the semiconductor layer L3 and an electrode 84 (not shown) connected thereto.

Therefore, the semiconductor device according to the present invention described above constitutes a so-called IIL circuit similar to that described above in FIG.

However, in the case of the semiconductor device according to the present invention described above, the semiconductor regions Q2 and Q3, which become the emitter and the base of the transistor U2, are arranged along the diagonal arrangement line with respect to the semiconductor layer L2, which becomes the collector. Therefore, the transistor U2 is not configured in a so-called horizontal type like the transistor U2 of the conventional semiconductor device described above in FIG.

Further, in the semiconductor device according to the present invention described above, the base of the transistor U2 is formed by the semiconductor region Q3 formed by impurity diffusion into the semiconductor layer L2.

Therefore, according to the semiconductor device according to the present invention described above, the area required by the transistor U2 on the semiconductor substrate 33 is smaller than the area required by the transistor U2 on the semiconductor substrate 3 of the conventional semiconductor device described above in FIG. Therefore, compared to the conventional semiconductor device described above in FIG. 1, it has the feature of being significantly smaller.

Further, according to the semiconductor device according to the present invention described above, since the base of the transistor U2 is formed by the semiconductor region Q3 formed by impurity diffusion into the semiconductor layer L2, the width of the base is smaller than that shown in FIG. The size is significantly smaller than that of the transistor U2 of the conventional semiconductor device described above.

Therefore, according to the semiconductor device according to the present invention described above,
The transistor U2 has a characteristic that α is much smaller than that of the transistor U2 of the conventional semiconductor device described above in FIG.

Furthermore, according to the semiconductor device according to the present invention described above, the emitter of the transistor U1 is formed by the semiconductor region Q1 formed by ion implantation into the semiconductor layer L2,
Since the impurity concentration of the semiconductor region Q1 can be easily increased as desired, the emitter injection efficiency of the transistor U1 is lower than that of the transistor U1 of the conventional semiconductor device described above in FIG. This is significantly improved compared to the previous case.

Therefore, according to the semiconductor device according to the present invention described above,
β of the transistor U1 is much smaller than that of the transistor U1 of the conventional semiconductor device described above in FIG. It has the characteristic that it is significantly smaller than the standard.

Further, according to the semiconductor device according to the present invention described above, the emitter of the transistor U1 is formed by the semiconductor region Q1 formed by ion implantation into the semiconductor layer L2,
The impurity concentration of the semiconductor region Q1 can be easily adjusted as desired, so that the emitter resistance can be reduced compared to that of the transistor U1 of the conventional semiconductor device described above in FIG. , can be made significantly smaller.

Therefore, according to the semiconductor device according to the present invention described above, the charging and discharging time for the emitter-base junction capacitance of the transistor U1 is significantly shorter than that of the transistor U1 of the conventional semiconductor device described above in FIG. As a result, the gain bandwidth is much shorter than that of the conventional semiconductor device described above in FIG. 1, and the response speed is
Compared to the conventional semiconductor device described above in FIG. 1, this semiconductor device has characteristics that are much more dog-like.

Further, according to the method for manufacturing a semiconductor device according to the present invention described above, the semiconductor device can be processed by a process using a mask to obtain the nitride layer M1, a process using a mask to obtain the window 65 of the insulating layer 58, and a process using a mask M5 to obtain the window 65 of the insulating layer 58. A process using a mask to form a window in the insulating layer 58 to connect the electrode 84 (not shown) to the semiconductor layer L3, and a mask to form the electrodes 82 to 84. Regarding the process using a mask, which is the process using , it can be obtained by a process that requires only 5 times.

Therefore, according to the method for manufacturing a semiconductor device according to the present invention described above, a semiconductor device having the above-mentioned characteristics can be manufactured through a much simpler process than the method for manufacturing the conventional semiconductor device described above in FIG. Can be manufactured and has characteristics that make it a dog.

Note that, in the above description, one example of a semiconductor device according to the present invention and one manufacturing method thereof have been described.

However, the method for manufacturing a semiconductor device described below and the semiconductor device obtained thereby can also be used as the method for manufacturing a semiconductor device according to the present invention, and the semiconductor device obtained thereby, respectively.

That is, although detailed explanation is omitted, after forming the semiconductor regions Q2 and Q3 in the semiconductor layer Ll as described above with reference to FIG. 3S, as shown in FIG. 4 Al and A2, the insulating layer 5 is formed.
8, a window 91 is bored through which the semiconductor layer L2 is exposed to the outside.

Next, as shown in FIG. 4B, N-type impurity is thermally diffused into the semiconductor layer Ll through this window 91.
A type semiconductor region Q4 is formed, and an insulating layer 92 made of an oxide mainly composed of silicon dioxide is formed on the semiconductor region Q4 and continues to the insulating layer 58.

Next, as shown in FIG. 4C, a window 93 is formed in the insulating layer 58 to expose the semiconductor layer L2 to the outside.

Next, as shown in the fourth diagram, P-type impurity is thermally diffused into the semiconductor layer Ll through the window 93.
A ten-shaped semiconductor region Q7 is formed, and an insulating layer 94 made of an oxide containing silicon dioxide as a main component is formed on the semiconductor region Q7 and continues to the insulating layer 58.

Next, as shown in FIG. 4E, the insulating layers 92 and 94 are
Windows 9 that allow semiconductor regions Q4 and Q7 to be exposed to the outside, respectively.
5 and 96, and the semiconductor layer L3 is formed in the insulating layer 58.
A window (not shown) is drilled to allow the outside to be seen.

Next, a fourth
As shown in FIG. F, windows ( A conductive layer 97 is formed extending over a region facing the outside through a conductive layer (not shown).

Next, by selectively etching the conductive layer 97, the electrode 80 shown in FIG. 3 AE and AF is connected only to the semiconductor region Q4, as shown in FIG. 4 G-1 and G-2. The corresponding electrode 98, the electrode 99 corresponding to the electrode 82 shown in FIG. 3 AE and AF, which is connected only to the semiconductor region Q7, and the electrode 99 shown above in FIG. 3, which is connected only to the semiconductor layer L3. An electrode (not shown) corresponding to the electrode 84 (not shown) is formed next or before the electrode 84 described above in FIG. 3 is connected to the semiconductor layer L1.
An electrode (not shown) corresponding to No. 3 (not shown) is formed.

In the manner described above, a target semiconductor device is manufactured that provides the same effects as those of the semiconductor device according to the present invention described above with reference to FIG.

Further, in the above description, after forming the insulating layer M4 made of the insulating layers 52 and 49 on the inner surface of the groove G, the semiconductor region Q
Although the case where the semiconductor region Q1 is formed has been described, the insulating layer M4 can also be formed after the semiconductor region Q1 is formed.

Various other modifications and changes may be made without departing from the spirit of the invention.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a conventional semiconductor device, which is the basis of a semiconductor device according to the present invention. FIG. 2 is its equivalent circuit diagram. Figure 3 A-D. E-2, F-8, T-2, U, V, W-
2, X to Z, AA-AE, and AF-2 are line cross-sectional views of successive steps showing an example of the method for manufacturing a semiconductor device according to the present invention; , AF-1
These are route plan views from which the route sectional views shown in FIG. 3 E-2, T-2, W-2, and AF-2 are obtained when the cross sections are taken along the line ■-■. Figure 4 A-2, B, C-2, DF and G-2 are
4Ai, c-i, and G-1, which are line cross-sectional views showing other examples of the method for manufacturing a semiconductor device according to the present invention in sequential steps, are respectively Third
It is a line plan view from which the line cross-sectional views shown in Figures A-2, C2, and G-2 are obtained. Ll, L2. L3... Semiconductor layer, 33...
...Semiconductor substrate, 34, 35, 45, 58, 69, 72
...Insulating layer, M1 to M5...Mask,
G...Groove, Q1-Q7...Semiconductor region, 68...Semiconductor layer, 71.73...
Layer, 80, 82... Electrode, Ul. U2...Transistor.

Claims (1)

[Claims] 1. A first semiconductor layer of a first conductivity type having a relatively small resistivity, and a second semiconductor layer of a first conductivity type opposite to the first conductivity type disposed on the first semiconductor layer. The silicon semiconductor substrate includes a second semiconductor layer of a conductive type, and the silicon semiconductor substrate includes:
A groove having an inverted triangular cross section extending from the upper surface side of the second semiconductor layer to the first semiconductor layer side is formed in the second semiconductor layer. a first semiconductor layer having an upper surface facing the upper surface with a required distance therebetween, and a side surface facing the inner surface of the groove with a required distance therebetween, and connected to the first semiconductor layer; a first semiconductor region of a conductivity type; and, from an inner surface side of the groove, the first semiconductor layer and the first
a second semiconductor region having a second conductivity type extending to a depth reaching the semiconductor region; and a second semiconductor region extending from the inner surface of the groove to a depth reaching the first semiconductor region, and a third semiconductor region having a first conductivity type that is connected to the second semiconductor region; A fourth semiconductor region having a first conductivity type is formed, and a fourth semiconductor region having a relatively small resistivity is formed in the groove, and a fourth semiconductor region is connected only to the second semiconductor region and has a relatively small specific resistance. a first transistor having a collector, a base, and an emitter, respectively, using the fourth semiconductor region, the second semiconductor layer, and the first semiconductor region; an emitter internally connecting the semiconductor region, the third semiconductor region, and the second semiconductor layer to the third semiconductor layer, and a base internally connecting the emitter of the first transistor; and a second transistor whose collector is internally connected to the base of the first transistor. 2. A first semiconductor layer of a first conductivity type having a relatively small resistivity, and a second semiconductor layer having a second conductivity type opposite to the first conductivity type disposed on the first semiconductor layer. on a silicon semiconductor substrate consisting of a first oxide layer and a first semiconductor layer.
nitride layers in order, then selectively etching the first nitride layer to form a second nitride layer; over-etching the first oxide layer using as a mask to form a second oxide layer included in the second nitride layer when viewed from above; and a step of masking the second nitride layer and performing an anisotropic etching process on the silicon semiconductor substrate to form a groove having an inverted triangular cross section; A nitride film is applied to the surface facing the outside of the material layer and the inner surface of the groove, and then the second layer is coated with a nitride film.
masking the nitride layer and implanting inert element ions,
forming a first ion implantation region in a region of the nitride film that is not shadowed by the second nitride layer; Taking advantage of the fact that it is easily etched, the first ion implantation region is removed to expose the lower part of the inner surface of the groove as a first exposed portion, and then thermal oxidation treatment is performed to remove the first ion implantation region. forming a first insulating layer on the first exposed portion; and removing the nitride film and the second nitride layer to expose a region other than the lower inner surface of the groove as a second exposed portion. Next, by implanting nitrogen ions using the second oxide layer as a mask, a second ion implantation is performed in a region of the second exposed portion that is not in the shadow of the second oxide layer. forming a second ion implantation region on the inner surface of the groove other than the second ion implantation region; and forming a third insulation layer on the second ion implantation region. Each was formed by a thermal oxidation method, and then
removing the third insulating layer by etching to form a third exposed portion on the inner surface of the groove; and implanting impurity ions imparting a first conductivity type from above to the second insulating layer. the first semiconductor layer, the semiconductor layer having an upper surface facing the upper surface thereof with a required distance therebetween, and a side surface facing the inner surface of the groove with a required distance therebetween; forming a first semiconductor region containing an impurity of a first conductivity type connected to the semiconductor region; and using the first and second insulating layers as masks, diffusing the impurity imparting the first conductivity type. By this, in the second semiconductor layer, the groove extends from the third exposed portion of the trench to a depth that reaches the first semiconductor layer, and extends to a depth that reaches the first semiconductor region. a step of forming a fifth semiconductor region of the first conductivity type, a step of providing a third semiconductor layer containing an impurity of the second conductivity type in the groove, and a step of forming the fifth semiconductor region of the first conductivity type by heat treatment. A first conductivity type impurity is introduced from the fifth semiconductor region into a region of the second semiconductor layer below the second insulating layer, so that the fifth semiconductor region is injected into the second semiconductor layer. While forming a sixth semiconductor region having a configuration that extends inward, a second conductivity type is introduced from the third semiconductor layer into the sixth semiconductor region through the third exposed portion of the groove. A second conductivity type that is introduced with an impurity and extends from the inner surface side of the groove to a depth that connects with the third semiconductor layer and reaches the first semiconductor layer and the first semiconductor region. a second semiconductor region, and a first semiconductor region that extends below the third insulating layer from the inner surface of the groove to a depth reaching the first semiconductor region, and is connected to the second semiconductor region. a step of forming a third semiconductor region of a conductivity type, and forming a third semiconductor region in the second semiconductor layer from the upper surface side thereof.
selectively introducing an impurity having a first conductivity type,
forming a fourth semiconductor region having a first conductivity type, and forming the fourth semiconductor region, the second semiconductor layer, and the first semiconductor region into a collector, a base, and an emitter, respectively. a first transistor, an emitter connecting the second semiconductor region, the third semiconductor region, and the second semiconductor layer to the third semiconductor layer, respectively; A semiconductor device comprising a base internally connected to an emitter, and a second transistor serving as a collector internally connected to the base of the first transistor. manufacturing method.