JPS5844817A - Pulse width modulating system - Google Patents

Abstract

PURPOSE:To obtain a correction pulse width modulation wave with a simple constitution, high accuracy, and low ripple, by providing the 1st and 2nd memories respectively storing the contents of an upper-order bit early in the period of the 1st counter output and a lower-order bit slow in the period. CONSTITUTION:The 2nd counter 25 counts the 2nd pulse CP1 with a start pulse P1, a lower-order bit of the counter 25 is stored in a memory 30 and an upper- order bit is to a memory 26 at the incoming of a pulse P2. The 1st pulse CP2 is counted at a counter 28 and when it is coincident with the value in the memory 26, an FF29 is reset to obtain a pulse width signal. When a value of a counter 31 counting a carry output of the counter 28 is coincident with the value of the memory 30, a pulse applied to the counter 28 is inhibited at a one pulse inhibiting gate 34 and the output pulse width is incremented by one pulse's share of the 2nd pulse CP2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse width modulation method, and is suitable for use in, for example, a servo circuit of a rotary head disk motor or a capstan motor of a home video tape recorder (hereinafter referred to as VTR).

In general, the rotating head disk motor or capstan motor of a home VTR has speed control and phase control in order to synchronize it with the vertical synchronization signal of the recording video signal and to accurately control tape running using playback control pulses. It is necessary to go there and apply the servo precisely.

Conventional servo systems using discrete transistor circuits or bipolar integrated circuits use a CR time constant created by a capacitor and resistor to perform sampling and hold processing to obtain a DC error voltage and control the motor.

Later, with the advancement of digital ICs, the phase difference between the signals to be measured, or the period of the signal, was converted into a digital number, based on the accurate lock pulse of a crystal oscillation, etc., and this was converted from digital to analog to the manipulated variable. A method has been developed to feed back to the motor drive circuit. In this case, digital-to-analog conversion involves converting the digital
Depending on the number, a precise reference clock pulse is used to perform pulse width modulation (PWM).

FIG. 1 shows a conventional pulse width modulation circuit, in which a counter 11
can count the second clock pulse CP2 as soon as the start pulse Pl is input. The count output of this counter 1 is added to the memory 12,
This memory 12 can latch the count output of the counter 11 when the store pulse P2 is input. Here, the vertical synchronization pulse is used as the start pulse P1, and the rotation detection pulse of the rotary head disk is used as the store pulse P2.For example, the phase difference between the vertical synchronization pulse and the rotation detection pulse is calculated by the count value of the counter 1. .

The contents of memory 12 are applied to one input of comparator 13. The count output of the counter 14 is applied to the other input terminal of the comparator 13. This counter 14 counts the second clock pulse CP2, and its carry output is applied to the set input terminal of the flip-flop circuit 15. In addition, the reset input terminal of this flip-flop circuit 15 has a
The coincidence pulse of the comparator 13 is applied. Therefore, the output of the flip-flop circuit 15 is set when a carry output of a certain period is obtained, and
The PWM wave is reset at the point in time when the coincident pulse whose generation timing differs depending on the contents of 2 is lost.

Incidentally, for an automatic control system, it is desirable that the sampling frequency, which is the period of the signal for detecting rotation, be high, and on the other hand, it is desirable that the carrier frequency of PWM be sufficiently high. The higher the number of bits, which determines the accuracy of digital numbers, the better. Taking these into consideration, the reference clock pulse frequency becomes very different. For example, if the sampling frequency is 200H7, and the PWM frequency is 5KH2,
If the precision of the digital number is 12 bits, the reference clock pulse frequency reaches 20 MHz. With this, MO8IC and IL (Integrate
d Injection Logic) does not work, so conventionally one countermeasure has been to unavoidably lower the PWM frequency to about 2KH2 and further lower the digital precision to about 10 bits. However, this method has the disadvantage that the characteristics of the low-pass filter for removing the carrier of the PWM wave may affect the phase characteristics of the servo loop, and furthermore, the response characteristics in the nonlinear region may deteriorate. Ta.

This invention was made to deal with the above-mentioned situation, and uses relatively low frequency clock pulses and
It is an object of the present invention to provide a modified pulse width modulation method that allows the M carrier frequency to be relatively high.

FIG. 2 is a basic configuration diagram of this system, and 25 is a first counter, which starts counting clock pulses CP1 when a start pulse P is input to the input terminal 2. Of the count output of this counter 25, the lower bit is added to one input terminal of the first memory 26,
The upper bits are applied to the input terminal of the second memory 3o. 1st. The second memo 1) 2e and 3o retain the content that was previously applied to the input terminal when the store pulse P2 applied via the input terminal 22 was input, and output it to the output terminal.

The contents of the first memory 26 are applied to one input of a comparator 27. The count output of a second counter 28 is applied to the other input terminal of the comparator 27. The carry output of the second counter 28 and the coincidence output of the comparator 27 are applied to the set terminal and reset terminal 4 of the flip-flop circuit 29, respectively.

As far as we can see from the system of the counter 25, memory 26, comparator 27, counter 28, and flip-flop circuit 29, the functions and operations are similar to those of the 11th unit 1.

Next, in this invention, the carry output is the third
It is also input to counter 3. This third counter 3
The count output of 0 is input to one side of the comparator 32.

The holding output of the memory 30 of η42 is added to the other side of this ratio +11M632. This comparator 32 uses the output of the counter 3 to determine the degree of PWM wave modification according to the content held in the second memory 30.

In other words, the memory 30, comparator 32, and counter 31 are
The output of the comparator 32 is used to determine the positive magnitude of the WM wave 1, and this operation will be explained in detail later.
3 is input.

This synchronization circuit 33 connects the input terminal 23 to the inhibition circuit 34.
This is to set the timing for prohibiting input of the clock pulse CP2 to the counter 28 after inputting the clock pulse CP2.

The circuit shown in FIG. 3 is a concrete example of the circuit shown in FIG. 2 as a receiver. The same parts as in FIG. 2 are denoted by the same reference numerals between songs. In Figure 3, the two counters are 1+1], for example, 1
2 bits, the first memory 26 is 8 bits, the second memory 5o114 bits, and the counter 31 is 4 bits. □The count output of the counter 31 and the count output of the second memory 30 have the same number of output bits. The comparator 32 is provided with the same number of AND circuits 41, 42, 43, and 44 as the number of output bits. Each AND circuit performs a logical product between corresponding bits of the contents of the second memory 3 and the contents of the counter 3. The corresponding person here is
- When looking at each content in the upper and lower directions, the contents are correlated so that the upper and lower parts are in opposite directions.

In other words, the upper bits and lower bits are correlated so that they are in reverse order. The outputs of the AND circuits 41 to 44 are connected to the corresponding data input terminals of the D-quib flip-flop circuits 45 to 48 constituting the synchronization circuit 33,
It is applied to each first input terminal of OR circuits 49 to 52. The respective inverted outputs of the previous ieD type flip-flop circuits 45 to 48 are applied to the second input terminals of the OR circuits 49 to 52, and the l) type flip-flop circuits 45
A clock pulse applied from the previous input terminal 23 is input to each of the input terminals 48 to 48. Each output terminal of the OR circuits 49 to 52 is connected to an AND circuit serving as a stop circuit 34. The synchronization circuit 33 c, in response to the clock pulse CP2, prohibits the outputs of the AND circuits 41 to 44 (if any one of them becomes zero (low level), then σ) falls. Outputs pulses.

Next, the operation of the above circuit will be explained. According to this circuit, the clock pulse cp,p for example is 1,28 MH
Even though the Z is old, the memory 26 is 8 hits and the counter 28 is also 8.
Since it is a human, a PWM wave of 5 Hz is generated. In this case, the quantification error is large, so in order to compensate for this and increase the accuracy, the characteristic part of this circuit operates. As shown in Figure 4, the PWM wave generator with an 8-bit configuration requires 256 clock pulses CP2 in one cycle, but if this clock pulse CP2 is inhibited at an appropriate timing, 257 PWM wave generators can be generated. In other words, the period of the PWM wave can be extended to the period of the PWM wave as shown in Fig. 4 fa), f
As shown in comparison with b), from 256Δt to 257Δ
For example, the period T1 from the rising edge to the falling edge
can be set to T1+]Δ1. However, Δt- and fcpcp are clock pulse frequency contrasts. In order to do this, for example, at the beginning of the cycle, i.e., at the start (before obtaining the carry output), the clock pulse CP2 is applied to the counter 2.
It is sufficient to prohibit inputting one item into 8. This modification is
If only the high level period changes, the cycle also changes, but the correction part is small compared to the whole cycle, so it is 1/256 and 1/2
It can be considered that it is almost the same as 57.

Such correction is applied once every 16 cycles of the PWM wave, for example.
If the correction is made only once, the analog voltage has changed by 1/16, and the digital-to-analog conversion rate has increased by that much.

Next, if you make multiple corrections in 16 cycles,
It is better to distribute the correction positions as evenly as possible. For example, if you do it 4 times in 16 cycles, 1 time every 4 cycles.
When the 2wM wave is converted to analog, the effect of the correction appears on average over time. Therefore, in this circuit,
When making corrections using the 4b data in the memory 30, ■When making corrections in even-numbered cycles, make sure to make even corrections and
Modification is performed in a base-addition manner, and the modification position for each bit is not changed. In order to set the conditions of ■■, the count bits "1, 2, 4, 8" are extracted from the count content output of the memory 30.

Specifically, referring to FIG. 5, FIG. 5(a) shows
This is an unmodified PWM wave, and FIG.

Now, assuming that the PWM wave is corrected once every 16 cycles T+6, the timing pulse l)1 shown in FIG. 5(b) is obtained. Next, if correction is made twice in 16 cycles T141, the timing pulse C1 of cl is obtained in FIG. Bit output Y+
+ Yt r Yt lX8 is shown in Fig. 6(a) to (di
It becomes as shown in . Here, each bit output of the memory 30, Xl r For example, now each bit output rx,.

Suppose that "x2, x number, Xs" is rl, O, O, OJ. In this case, it is possible to obtain an output "1" from the AND circuit 44. Bit output of counter 31 “yλ”
falls every 16 cycles, so the synchronization circuit 32 outputs the inhibit pulse at this falling timing and in synchronization with the clock pulse CP2. The prohibited pulse mode at this time is 16 cycles above the PWM wave as shown in FIG. 5fbl, and the waveform at this time is corrected.

I'xI lX2 lX4 +xsJ=rl, O,
If "0°0" does not change, this correction is repeated, and if the whole is averaged, rl, 0,0. This means that it has been revised to correspond to the content of the OJ. Also' xl+ X2 1 x
41 xa J −r O+ 1 + O*0”, the output of the AND circuit 43 can be “1”. "y4
” is a pulse train that falls every 8 cycles, so Figure 5 (c
This becomes a prohibited pulse train mode as shown in FIG. Furthermore [xl
+X2+x4+X, J=rl, 1,0. O.J.
If so, the output of AND circuits 43 and 44 is "1"
It can be. And rysJr-y*J are each 1
Since the pulse falls every 6th or 8th period, it becomes the prohibited pulse mode shown in Fig. 5(di). However, this mode is
bl , (can be obtained by combining the modes of C1 in a binary additive manner. Therefore, if we try to modify each of the 16 cycles, [xl , X2.x4.x8''=rl, ], 1.
It is sufficient to set it to IJ, and in this case, it is necessary to set it to IJ.
(C1, tel, (I's mote can be synthesized. This allows the whole to be corrected and complemented on the average.

The above rx+ + X2! X4, Xs J
As an example, rl, 0. O, OJ I'0.1. O, O
J.

rl, 1. O, OJ, rl, 1,1. Although IJ is shown, the meaning of this count content can be explained as follows. Now, the target value of the PWM wave is that the contents of the memory 26 are r
o, o, ...1,0. OJ, and the contents of the memory 30 are ro, 0, 0 . Suppose that it is ideal when OJ is OJ.

In this case, a PWM wave corresponding to the contents of the memory 26 is obtained. (Uncensored) Here, the timing of store pulse P2 is delayed and the contents of memo IJ s o are
lX2 1X4 +X5J=rl+ 0.0゜0"
, this is one of the clock pulses CP,
This means that the latch timing is delayed by an amount equal to 1. Therefore, in this case, correction is performed once every 16 cycles as before. If the PWM wave is converted to analog by this, the output will be 9? A is done. Next, the contents of the memory 30 are "'+, X2 1 X41 x8 J = r
011°0.0''. This means that the latch timing is further delayed by the store pulse P2. Therefore, in this case, PWM wave correction is performed once every eight cycles as before. In other words, for minute deviations, the PWM wave is corrected in accordance with the timing deviation, depending on the contents of the 4bth memory 30.

According to the present invention, as described above, the clock pulse CP2
There is no need to set the frequency of
ζ can be selected, increasing the degree of freedom in design1, and
However, just because the frequency of the clock pulse CP is lowered, it is not necessary to lower the carrier frequency of the PWM wave as in the conventional case. Use the second memory to select the upper level!・
This is due to the division of the lower bits.

Furthermore, according to the present invention, it is possible to modify an unmodified PWM wave, thereby increasing its overall accuracy. As a correction method, please refer to the second memo IJ.
The contents of s0 may be inputted to an arithmetic unit that stores the prohibited pulse mode in advance, and the correction timing may be obtained in accordance with the contents, but in this case, the circuit configuration becomes sloppy. However, if the embodiments of the present invention are used, they can be implemented at low cost with a very simple structure, and are suitable for integration into an integrated circuit. In the above explanation, the number of bits to be extracted for correction is often 4 bits, but this number of bits is arbitrary. In addition, the circuit shown in Figure 3 has a pulse that is extremely dazzling.
Of course, various other modifications can be made depending on the number of bits.

As described above, the present invention can provide a pulse width modulation method that can generate a modified PWM wave with high precision and low ripple with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram of a conventional pulse width modulation circuit, FIG. 2 is a configuration explanatory diagram showing an embodiment of the present invention, and FIG. 3 is a configuration explanatory diagram of a conventional pulse width modulation circuit.
FIG. 4 (al.
, (bl, Fig. 5 (al~ (pl, Fig. 6 (al~
(d) is an operation signal waveform diagram shown to explain the circuit operation of FIG. 3. 25.28.31...Counter, 26.30...Memory, 27...Comparator, 32...Comparator, 33
...Synchronization circuit, 34...Prohibition circuit.

Claims (1)

[Claims] The interval between the first pulse and the second pulse to be compared is determined by the first clock pulse count number of the first counter, this count content is held in memory, and the second pulse is
A comparator compares the count number of a second counter that counts clock pulses with the contents of the memory,
In a pulse width modulation method in which a coincidence output of the comparator and a carry output of the second counter are added to a flip-flop circuit to obtain a pulse width modulation output, the upper part of the count output of the first counter with a faster cycle is used as the memory. The first . A second memory is provided, and a third counter for counting the carry output of the second counter is provided, and the count output corresponds to the contents of each bit of the first memory holding the contents of the high-order bits having a fast cycle. The third
The pulse width modulated wave is modified by selecting each bit output of the counter and determining the prohibited position of the second clock pulse input to the second counter based on the selected output. Pulse width modulation method.