JPS5844723A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5844723A JPS5844723A JP56142531A JP14253181A JPS5844723A JP S5844723 A JPS5844723 A JP S5844723A JP 56142531 A JP56142531 A JP 56142531A JP 14253181 A JP14253181 A JP 14253181A JP S5844723 A JPS5844723 A JP S5844723A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- particulates
- rate
- grooves
- sintering
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/40—Oxides
- C23C16/401—Oxides containing silicon
- C23C16/402—Silicon dioxide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
Abstract
Description
【発明の詳細な説明】
本発明は、誘電体絶縁分離法を施した半導体装置夕製造
方法に関するもので、さらに詳しくは、高耐圧回路素子
を形成するだめの複数の半導体結晶領域がそれぞれ誘電
体を介して(Y特休に埋め込まれた構造の基板の製造方
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device using a dielectric isolation method, and more specifically, the present invention relates to a method for manufacturing a semiconductor device using a dielectric isolation method, and more specifically, a plurality of semiconductor crystal regions forming a high voltage circuit element are each made of a dielectric material. This article relates to a method for manufacturing a substrate having a structure embedded in the Y special holiday.
従来のこの種の装置の製造方法は、半導体基板表面の分
離領域に蝕刻溝を形成した後に、熱酸化により酸化膜を
当該溝部分に形成させ、さらに600〜400μmの厚
さの多結晶シリコンをCVDで形成させて保持体として
いたので、多結晶シリコンの成長速度が3〜5μm/分
程度と遅く、その上誘電体分離するために熱酸化する等
の必要があった。The conventional manufacturing method for this type of device is to form an etched groove in an isolation region on the surface of a semiconductor substrate, then form an oxide film in the groove by thermal oxidation, and then deposit polycrystalline silicon with a thickness of 600 to 400 μm. Since the holding body was formed by CVD, the growth rate of polycrystalline silicon was slow at about 3 to 5 μm/min, and furthermore, it was necessary to perform thermal oxidation for dielectric isolation.
本興明はこれらの欠点を解決するため、四塩化硅素(8
1C14) を主成分とする原料を酸水素炎で火炎加
水分解させろことによって生じるガラス(5102)の
微粒子を半導体基板上に堆積した後1゜焼結させたもの
で、以下図面について詳細に説明する。In order to solve these drawbacks, this Komei has developed silicon tetrachloride (8
Fine particles of glass (5102) produced by flame hydrolysis of a raw material whose main component is 1C14) with an oxyhydrogen flame are deposited on a semiconductor substrate and then sintered by 1°.The drawings will be explained in detail below. .
第1図は本発明の製造方法の原理説明図である。FIG. 1 is an explanatory diagram of the principle of the manufacturing method of the present invention.
図において、1は半導体基板(単結晶基板)で、2は蝕
刻溝、6は吹き付はバーナ、4は火炎である。In the figure, 1 is a semiconductor substrate (single crystal substrate), 2 is an etched groove, 6 is a burner for spraying, and 4 is a flame.
第2図は本発明によって形成された半導体装置の断面図
である。図において、5は透明な硬質ガラス(保持体)
である。FIG. 2 is a cross-sectional view of a semiconductor device formed according to the present invention. In the figure, 5 is transparent hard glass (holder)
It is.
本発明の製造方法を行彦うにあたっては、分離領域に蝕
刻溝2を形成した半導体基板1にS i Cl 4を主
成分(この他にガラスの膨張係数、焼結に必要な温度等
の調整用に;例えばB2O3,P2O5等を加えてもよ
い。)とする原料を酸水素炎とともに溝形成表面に吹き
付はバーす6から吹き付けて、微粒子のガラスを付着さ
せ、多孔質ガラスの保持体を形成する。更に、1000
〜1600℃の高温で加熱すると、この多孔質ガラスの
保持体は体積が六程度に減少するとともに透明の硬質ガ
ラスとなる。In carrying out the manufacturing method of the present invention, a semiconductor substrate 1 in which etched grooves 2 are formed in separation regions is coated with S i Cl 4 as a main component (in addition, it is used to adjust the expansion coefficient of glass, the temperature required for sintering, etc.). For example, B2O3, P2O5, etc. may be added.) A raw material containing oxyhydrogen flame is sprayed onto the groove forming surface from a bar 6 to deposit fine glass particles and form a porous glass holder. Form. Furthermore, 1000
When heated at a high temperature of ~1600° C., the volume of this porous glass holder decreases to about 600° C. and becomes transparent hard glass.
次に実施例を説明する。Next, an example will be explained.
吹き付はバーナ6(第1図参照)に、S i(−1!
4を100CC/分、[I2を2000CC/分、02
を3000cc/分の割合で送り込んで、蝕刻溝を設け
た半導体基板1の表面にガラス(SiO2)の微粒子を
堆積させた。6インチの半導体基板上に600μmのガ
ラスを形成するためには、およそ6分で充分であった。For spraying, apply S i (-1!) to burner 6 (see Figure 1).
4 at 100CC/min, [I2 at 2000CC/min, 02
was fed at a rate of 3000 cc/min to deposit glass (SiO2) fine particles on the surface of the semiconductor substrate 1 provided with the etched grooves. Approximately 6 minutes was sufficient to form 600 μm of glass on a 6 inch semiconductor substrate.
すなわち、ガラスの成長速度は0.5g/分程度である
。その後熱処理を行なったが、熱処理時間は温度が12
00℃のとき、およそ120分程度であった。焼結後、
透明の硬質ガラスが形成された面と反対側の面を所望の
厚さになるまで加工□し、高耐圧素子形成用の分離領域
を備えた基板が構成できた。That is, the growth rate of glass is about 0.5 g/min. After that, heat treatment was performed, but the heat treatment time was at a temperature of 12
At 00°C, it took about 120 minutes. After sintering,
The surface opposite to the surface on which the transparent hard glass was formed was processed until the desired thickness was reached, and a substrate with a separation region for forming a high-voltage element was constructed.
以上説明したように、本発明の製造方法は誘電体である
S r 02を直接当該基板に付着させるため、熱酸化
工程が不要である上に、成長速度が一桁向上する。また
、焼結後、透明体の保持体が形成されるため、その後の
溝と逆方向からの加工工程の際の加工量測定が光学的に
容易に計測できる等の利点がある。 □As explained above, in the manufacturing method of the present invention, since the dielectric S r 02 is directly attached to the substrate, a thermal oxidation step is not necessary, and the growth rate is improved by one order of magnitude. Furthermore, since a transparent holder is formed after sintering, there are advantages such as the ability to optically easily measure the amount of processing during the subsequent processing step from the direction opposite to the groove. □
第1図は本発明の製造方法の原理説明図、第2図は本発
明によって形成された半導体装置の断面図である。
1・・・半導体基板 2・・・蝕刻溝6・・・吹
き付はバーナ 4・・・火炎5・・・硬質ガラス(保
持体)
特許出願人 日本電信電話公社
代理人弁理士 中村純之助FIG. 1 is a diagram explaining the principle of the manufacturing method of the present invention, and FIG. 2 is a sectional view of a semiconductor device formed according to the present invention. 1... Semiconductor substrate 2... Etched groove 6... Burner for spraying 4... Flame 5... Hard glass (holding body) Patent applicant Junnosuke Nakamura, patent attorney representing Nippon Telegraph and Telephone Public Corporation
Claims (1)
後に、5IC14を主成分とする原料を酸水素炎ととも
に該溝形成側基板表面に吹き付けて、火炎加水分解反応
で生じるガラス微粒子を層状に堆積させて多孔質母材と
し、その後1000℃以上で高温熱処理することにより
多孔質1母材を焼結させ、当該基板の保持体を形成させ
ることを特徴とする半導体装置の製造方法。After forming etched grooves in the area to be separated on the surface of the semiconductor substrate, a raw material containing 5IC14 as a main component is blown onto the surface of the substrate on the side where the grooves are to be formed together with an oxyhydrogen flame, so that the glass fine particles produced by the flame hydrolysis reaction are formed into a layer. 1. A method for manufacturing a semiconductor device, comprising: depositing the substrate to form a porous base material, and then performing high-temperature heat treatment at 1000° C. or higher to sinter the porous base material to form a holder for the substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56142531A JPS5844723A (en) | 1981-09-11 | 1981-09-11 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56142531A JPS5844723A (en) | 1981-09-11 | 1981-09-11 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5844723A true JPS5844723A (en) | 1983-03-15 |
Family
ID=15317518
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56142531A Pending JPS5844723A (en) | 1981-09-11 | 1981-09-11 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5844723A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61242033A (en) * | 1985-04-19 | 1986-10-28 | Nippon Telegr & Teleph Corp <Ntt> | Bonding process of semiconductor substrate |
-
1981
- 1981-09-11 JP JP56142531A patent/JPS5844723A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61242033A (en) * | 1985-04-19 | 1986-10-28 | Nippon Telegr & Teleph Corp <Ntt> | Bonding process of semiconductor substrate |
NL8600983A (en) * | 1985-04-19 | 1986-11-17 | Nippon Telegraph & Telephone | METHOD FOR MANUFACTURING A SEMI-CONDUCTOR SUBSTRATE |
US4978379A (en) * | 1985-04-19 | 1990-12-18 | Nippon Telegraph And Telephone Corporation | Method of joining semiconductor substrates |
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