JPS5844715A - Forming method for minute pattern - Google Patents

Forming method for minute pattern

Info

Publication number
JPS5844715A
JPS5844715A JP56142385A JP14238581A JPS5844715A JP S5844715 A JPS5844715 A JP S5844715A JP 56142385 A JP56142385 A JP 56142385A JP 14238581 A JP14238581 A JP 14238581A JP S5844715 A JPS5844715 A JP S5844715A
Authority
JP
Japan
Prior art keywords
resist
layer
pattern
etched
baking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56142385A
Other languages
Japanese (ja)
Other versions
JPH0143450B2 (en
Inventor
Toshihiko Yoshida
俊彦 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56142385A priority Critical patent/JPS5844715A/en
Publication of JPS5844715A publication Critical patent/JPS5844715A/en
Publication of JPH0143450B2 publication Critical patent/JPH0143450B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004Photosensitive materials
    • G03F7/075Silicon-containing compounds
    • G03F7/0751Silicon-containing compounds used as adhesion-promoting additives or as means to improve adhesion

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To form the patterns having high accuracy to both upper and lower layers by specifically treating a resist etching the upper layer when the layer to be etched of the two upper and lower layers is etched. CONSTITUTION:A poly Si layer is deposited onto a Si substrate, an oxide film is shaped to the surface, and a poly Si layr is further formed onto the oxide film. A positive resist is spin-coated onto the poly Si layer, and the resist pattern is shaped through baking, exposure, development, washing and post baking. A substance consisting of acidic phenol resin reacting and combining with hexamethyldisilazane is used as the positive resist. The pattern of the poly Si layer of the upper layer is shaped by the resist pattern. The hexamethyldisilazane is impregnated to the positive resist and the resist pattern is reinforced through baking. A positive resist pattern is formed onto the pattern, and the poly Si layer of the lower layer is etched by the positive resist pattern.

Description

【発明の詳細な説明】 本発明は基板の上に設けた上下2層の被工ψチンダ層の
エツチングを行なうために、2層のレジストノ譬ターン
を精度よく形成する微細ノ譬ターン形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a fine pattern pattern forming method for forming two resist pattern patterns with high accuracy in order to etch two upper and lower ψ pattern layers provided on a substrate. .

一般にレゾストノ豐ターンの形成方法は、レジストをス
ピンコードし、これをグリベークしてレノストから溶剤
を蒸発させて固形化し、紫外線などで露光して着像を形
成し、現俸液でdターンを形成し、さらにIストベーキ
ングによって強化し、゛かつ基板との書着性を高める。
In general, the method for forming resist turns is to spin-code the resist, bake it to evaporate the solvent from the resist, solidify it, expose it to ultraviolet light to form an image, and form a d-turn with the current solution. It is further strengthened by I-strength baking and improves the adhesion to the substrate.

さて上下2層の被エツチング層のエツチングを行なうに
は2層OVシストを必要とする場合がある・上層のエツ
チングを行なう第1のレゾストノ母ターンに特別のII
JIImを施さないで、この上に1s2のレゾストをス
ピンコードすると、第1のレジストがこれに溶解し、*
に鎖2の露光に感光し、さらに3jl儂液および洗浄液
に溶解する。このように第1のレジストパターンが変化
すると、第2層0ノ譬ターン形成が乱れる欠点がToり
た。
Now, in some cases, a two-layer OV system is required to perform etching of the upper and lower two layers to be etched.
If you spin code 1s2 resist on top of this without applying JIIm, the first resist will dissolve into this and *
Then, strand 2 is exposed to light and further dissolved in 3jl solution and washing solution. When the first resist pattern is changed in this way, there is a drawback that the formation of zero-count turns in the second layer is disturbed.

本発明の目的は上記欠点を解消することである争本発明
の上記目的は、上下2層の被工、チンダ層の上に、 /
ジレジストでTo−)て、露光、iJL儂および洗浄の
後に、 −sキサメチルジシラデンと反応させると、第
20露光[偉および洗浄を行なっても感光または溶解し
碌い物質に変換する第104−)レゾストをスピンコー
ドし、常法によるグリベーキング、露光、現像、洗浄お
よびIストベーキングによりて第1のレジストパターン
を形成し、こQt!ターンによって工、テングを行なっ
て上層のパターンを形成する工@において、第1のレゾ
スト/4ターンの形成の後または上層の/ぐターンを形
成し九後に1第1のレジストにヘキサメチルゾシラデン
を含浸させて温度110〜1iSO℃に加熱する第3ベ
ーキングを行ない、次に上層の被エツチング層を工、チ
ングし九後第2のdFジレゾストを使用し、常法により
て第2のレジストパターンを形成しこOAパターンより
てエツチングを行なりて下層のノ青ターンを形成するこ
とを特徴とする徴11、lターン形成方法によりて達成
することができる0本発明で使用する第1の/ジレダス
トは、アルカリ性のヘキサメチルノシラデンと反応して
結合する酸性のフェノール樹脂からなる4I−)レノス
ートであればよく、たとえば東京応化工業l0FPRφ
SOO、シ、!レイ1IAZ1350、ハント製11P
R−204などを使用することができる・第2のレゾス
トとしては、ヘキサメチルジシラデンと反応した第1の
レゾストが、第2のレジストがネガレノストであるとき
は、ツヤターン形成工程において溶解するので使用する
ことができない。従りてポジレジストを使用する。
The object of the present invention is to eliminate the above-mentioned drawbacks.
After exposure, iJL and washing, it is reacted with -sxamethyldisiladene to form a substance that is photosensitive or soluble even after the 20th exposure and washing. -) A first resist pattern is formed by spin-coding the resist, exposing, developing, cleaning and I-st baking according to a conventional method, and Qt! In the process of forming the pattern of the upper layer by performing etching and pronging by turning, after the formation of the first resist/4 turns or after forming the upper layer/g turns, hexamethylzosilane is applied to the first resist. A third baking process is performed in which the densified film is impregnated with dF and heated to a temperature of 110 to 1 SO°C, and then the upper layer to be etched is etched. Feature 11, characterized in that a pattern is formed and then etched using an OA pattern to form a blue turn in the lower layer, can be achieved by the l-turn forming method. / Giredust may be 4I-)renosuto, which is made of an acidic phenolic resin that reacts with alkaline hexamethylnosiladene and bonds with it; for example, Tokyo Ohka Kogyo 10FPRφ
SOO, sh! Ray 1IAZ1350, Hunt made 11P
R-204 etc. can be used. ・As the second resist, the first resist that reacted with hexamethyldisiladene is used because it dissolves in the gloss turn forming process when the second resist is a negative resist. Can not do it. Therefore, a positive resist is used.

本実lJIow徴はこのような第1および第2のレゾス
トを使用し、かつ通常のレジストパターン形成工11に
よりて4ストベーキングを終了した第1のレゾストイタ
−νを)キナメチルゾシラデンに、九とえば25′cで
浸漬し九後、温度110〜150C。
The present invention uses the first and second resists and converts the first resist resistor (v) which has been subjected to four-stroke baking by the usual resist pattern forming process 11 to quinamethylzosiladene, For example, after soaking at 25'C, the temperature is 110-150C.

好ましくは130℃において第3ベーキングな行なりて
、第1のレゾストパターンを強化し、これKよって第2
のレジストノリーン形成工程において、パターンが乱れ
ることを防止することができる。この第3ベーキングは
、上層のノリーンを形成する第1のエヅチングの前、す
なわち通常のポストベーキングの後でありてもよいが、
第1のエツチングの後でもよい。
A third baking is preferably carried out at 130° C. to strengthen the first resist pattern and thereby strengthen the second resist pattern.
It is possible to prevent the pattern from being disturbed in the resist nolene forming step. This third baking may be performed before the first etching to form the upper layer of Noreen, i.e. after the normal post-baking, but
It may be done after the first etching.

次に実施例によって本発明の詳細な説明する・クリコン
基板の上に厚み0.5μmのシIリシリコン層をCVD
法によって沈着させ、その表面を酸化して厚み0.1μ
mの酸化gt影形成、さらに厚み0.5j購のポリシリ
コン層を沈着させた。ポジレジストは東京応化工業製0
FPRす800を500Orpmでスピンコードして厚
み約1.0−とし、温度−85℃で20分グリベークし
、波長436 arm(D紫外光で露光して潜儂を゛形
成し、東京応化工業製NMD−3で現像し、水洗の後に
温[130℃で20分ポストベークした0以上は通常の
処理である。ζうして形成しIF、/)・−ターンによ
−zて、025−を含むCF4でグラズマエ、チングし
て、上層のポリシリコン層のツヤターンを形成した。
Next, the present invention will be explained in detail with reference to an example. A 0.5 μm thick silicon layer is deposited on a silicon substrate by CVD.
method, and the surface is oxidized to a thickness of 0.1 μm.
m oxidized gt shadowing and a further 0.5 j thick polysilicon layer was deposited. Positive resist is made by Tokyo Ohka Kogyo 0
FPR 800 was spin-coded at 500 rpm to a thickness of approximately 1.0 mm, grilled at -85°C for 20 minutes, exposed to wavelength 436 arm (D ultraviolet light to form a latent film, and coated with Tokyo Ohka Kogyo Co., Ltd.). Developed with NMD-3, washed with water, and then post-baked at 130°C for 20 minutes. 0 or more is normal processing. A glossy turn of the upper polysilicon layer was formed by glazing with CF4 containing CF4.

次に本発明に従って、基板を温度25COヘキサメチル
ノシラデンに40分浸漬して引上げ、これを温度130
℃で20分aI3ベーキングを行なって、第1のレジス
トパターンを強化した。
Next, in accordance with the present invention, the substrate is immersed in hexamethylnosiladene at a temperature of 25 CO for 40 minutes and pulled up;
The first resist pattern was strengthened by performing aI3 baking at .degree. C. for 20 minutes.

さらに通常の方法によって第2のポジレジストとして通
常の東京応化工業#I 0FPIIφ800を500 
Orpmでスピンコードして厚み104嘴とし、温度8
5℃で20分間グリベークし、波長436!1g11の
紫外光で露光して着像を形成し、東京応化工業製NMD
−3で現像し、水洗して温*13ocで20分ポストベ
ークして第2の/ジレゾストノ譬ターンを形成した。こ
のツヤターンによって、まずフ、酸系工、チンダ液で酸
化膜をエツチングし、次KO□59!を含むCF4グラ
ズマエ、チングによって下層のポリシリコン層を工、テ
ンダした。これによって上下2層とも精度の高い・母タ
ーンを形成することができ九。
Further, as a second positive resist, 500% of ordinary Tokyo Ohka Kogyo #I 0FPIIφ800 was applied in a conventional manner.
Spin coded with Orpm to a thickness of 104 mm and a temperature of 8 mm.
Gribake at 5°C for 20 minutes, expose to ultraviolet light with a wavelength of 436!1g11 to form an image, and use Tokyo Ohka Kogyo NMD.
-3, washed with water, and post-baked for 20 minutes at *13 oc to form a second/direzost pattern. With this gloss turn, first, the oxide film is etched with acid-based etching solution, and then KO□59! The underlying polysilicon layer was etched and tenderized by CF4 glazing. This makes it possible to form highly accurate mother turns on both the upper and lower layers.9.

Claims (1)

【特許請求の範囲】 1、上下2層の被工、チング層の上に、 /ジレジスト
であって、露光、現像および洗浄の後に1ヘキサメチル
ゾシラデンと反応させると、第2の露光、現像および洗
浄を行なっても感光を九は溶解しない物質に変換する第
1の/ジレノストをスピンコードし、常法によるグリベ
ーキング、露光、現像、洗浄および?ストベーキングに
よりて第1のレジストIり一ンを形成し、このノ9ター
ンによりてエツチングを行なうて上層のノリーンを形成
する工程において、第1のレノストΔターンの形成の後
または上層のノ々ターンを形成した後に、第1のレジス
トにヘキサメチルジシラデンをtaさせて温度110〜
150℃に加熱する第3ぺ一午ングを行ない、次に上層
の被エツチング層を工。 テングした後、第2の/ジレノストを使用し、常法によ
って第2のレジストノターンを形成し、このΔターンに
よりて下層の被エツチング層のエツチングを行なって下
層の/ダターンを形成することを特徴とする微細Δター
ン形成方法。
[Claims] 1. On top and bottom two layers of the coating layer, /diresist, which is reacted with 1 hexamethylzosiladene after exposure, development and washing, a second exposure, The first/gylenost, which converts the photosensitive material into a substance that does not dissolve even after development and washing, is spin-coded, and then subjected to conventional methods such as baking, exposure, development, washing and ? In the step of forming the first resist I line by strike baking and etching using this 9 turn to form the upper layer, after the formation of the first resist Δ turn or the upper layer no line, After forming the turns, the first resist is heated to a temperature of 110~110℃ by applying hexamethyldisiladene.
A third period of etching is performed by heating to 150°C, and then the upper layer to be etched is etched. After etching, a second resist pattern is formed by a conventional method using a second resist, and the lower layer to be etched is etched by this Δ turn to form a lower pattern. Features a fine Δ turn formation method.
JP56142385A 1981-09-11 1981-09-11 Forming method for minute pattern Granted JPS5844715A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56142385A JPS5844715A (en) 1981-09-11 1981-09-11 Forming method for minute pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56142385A JPS5844715A (en) 1981-09-11 1981-09-11 Forming method for minute pattern

Publications (2)

Publication Number Publication Date
JPS5844715A true JPS5844715A (en) 1983-03-15
JPH0143450B2 JPH0143450B2 (en) 1989-09-20

Family

ID=15314129

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56142385A Granted JPS5844715A (en) 1981-09-11 1981-09-11 Forming method for minute pattern

Country Status (1)

Country Link
JP (1) JPS5844715A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61218133A (en) * 1985-03-19 1986-09-27 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Pattern formation of semiconductor device
JPS6224625A (en) * 1985-07-24 1987-02-02 Nippon Telegr & Teleph Corp <Ntt> Formation of pattern
JPS6225424A (en) * 1985-07-26 1987-02-03 Nippon Telegr & Teleph Corp <Ntt> Pattern forming method
JPS62165650A (en) * 1986-01-14 1987-07-22 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Manufacture of positive photoresist
JPS62258449A (en) * 1986-04-24 1987-11-10 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Making of two-layer resist image
JPS62297837A (en) * 1986-06-10 1987-12-25 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Resist pattern formation
JPS6371843A (en) * 1986-06-30 1988-04-01 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション Treatment of polymer resist
JPH02158737A (en) * 1988-10-31 1990-06-19 Internatl Business Mach Corp <Ibm> Generation of relief pattern and use
JPH02291562A (en) * 1989-03-17 1990-12-03 Internatl Business Mach Corp <Ibm> Processing of photoresist image
KR20110002797A (en) * 2009-06-26 2011-01-10 롬 앤드 하스 일렉트로닉 머트어리얼즈, 엘.엘.씨. Methods of forming electronic devices

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5267270A (en) * 1975-12-01 1977-06-03 Toshiba Corp Photo etching method
JPS52152173A (en) * 1976-06-14 1977-12-17 Tokyo Ouka Kougiyou Kk Method of hardening aqueousssoluble resist pattern
JPS5429574A (en) * 1977-08-08 1979-03-05 Ibm Method of forming antiifluidity resist mask
JPS5448485A (en) * 1977-09-26 1979-04-17 Hitachi Ltd Photo etching method
JPS5649526A (en) * 1979-09-29 1981-05-06 Toshiba Corp Manufacture of semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5267270A (en) * 1975-12-01 1977-06-03 Toshiba Corp Photo etching method
JPS52152173A (en) * 1976-06-14 1977-12-17 Tokyo Ouka Kougiyou Kk Method of hardening aqueousssoluble resist pattern
JPS5429574A (en) * 1977-08-08 1979-03-05 Ibm Method of forming antiifluidity resist mask
JPS5448485A (en) * 1977-09-26 1979-04-17 Hitachi Ltd Photo etching method
JPS5649526A (en) * 1979-09-29 1981-05-06 Toshiba Corp Manufacture of semiconductor device

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61218133A (en) * 1985-03-19 1986-09-27 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Pattern formation of semiconductor device
JPS6224625A (en) * 1985-07-24 1987-02-02 Nippon Telegr & Teleph Corp <Ntt> Formation of pattern
JPS6225424A (en) * 1985-07-26 1987-02-03 Nippon Telegr & Teleph Corp <Ntt> Pattern forming method
JPS62165650A (en) * 1986-01-14 1987-07-22 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Manufacture of positive photoresist
JPH0456980B2 (en) * 1986-01-14 1992-09-10 Intaanashonaru Bijinesu Mashiinzu Corp
JPS62258449A (en) * 1986-04-24 1987-11-10 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Making of two-layer resist image
JPH0456977B2 (en) * 1986-06-10 1992-09-10 Intaanashonaru Bijinesu Mashiinzu Corp
JPS62297837A (en) * 1986-06-10 1987-12-25 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Resist pattern formation
JPS6371843A (en) * 1986-06-30 1988-04-01 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション Treatment of polymer resist
JPH02158737A (en) * 1988-10-31 1990-06-19 Internatl Business Mach Corp <Ibm> Generation of relief pattern and use
JPH02291562A (en) * 1989-03-17 1990-12-03 Internatl Business Mach Corp <Ibm> Processing of photoresist image
KR20110002797A (en) * 2009-06-26 2011-01-10 롬 앤드 하스 일렉트로닉 머트어리얼즈, 엘.엘.씨. Methods of forming electronic devices
JP2011066393A (en) * 2009-06-26 2011-03-31 Rohm & Haas Electronic Materials Llc Method of forming electronic device
JP2011071479A (en) * 2009-06-26 2011-04-07 Rohm & Haas Electronic Materials Llc Method for forming electronic device

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