JPS5843631A - Current injection type logical gate circuit using josephson effect - Google Patents

Current injection type logical gate circuit using josephson effect

Info

Publication number
JPS5843631A
JPS5843631A JP56142749A JP14274981A JPS5843631A JP S5843631 A JPS5843631 A JP S5843631A JP 56142749 A JP56142749 A JP 56142749A JP 14274981 A JP14274981 A JP 14274981A JP S5843631 A JPS5843631 A JP S5843631A
Authority
JP
Japan
Prior art keywords
current
gate circuit
input
logic gate
resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56142749A
Other languages
Japanese (ja)
Other versions
JPH0234493B2 (en
Inventor
Junichi Sone
曽根 純一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56142749A priority Critical patent/JPS5843631A/en
Priority to EP82108223A priority patent/EP0074604B1/en
Priority to DE8282108223T priority patent/DE3268138D1/en
Priority to US06/415,877 priority patent/US4538077A/en
Priority to CA000411147A priority patent/CA1189916A/en
Priority to AU88311/82A priority patent/AU553981B2/en
Publication of JPS5843631A publication Critical patent/JPS5843631A/en
Publication of JPH0234493B2 publication Critical patent/JPH0234493B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/195Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices
    • H03K19/1954Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices with injection of the control current
    • H03K19/1956Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices with injection of the control current using an inductorless circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To make a logical gate circuit of the product of a wide operation margin small-sized, by connecting 2 input lines to a resistance and a Josephson junction, connecting an output line to the Josephson junction and the resistance, and connecting each resistance in common, CONSTITUTION:Input lines 38, 39 for injecting input current Ia, Ib are connected to Josephson JS junctions 30, 32 whose one terminal is grounded, respectively, and resistances 33, 35. An output line 36 terminated by a resistance 37 is connected to a JS junction 31 whose one terminal has been grounded 40, and a resistance 34, and the other terminal of the resistances 33-35 are connected in common. A critical current values of the JS 30-32 and resistance values of the resistances 33-35 are denoted as I01-I03 and r1-r3, respectively, and set to I01=I03=I02/2=I0, and r1=r3=r2/2, respectively. When only one current in the currents Ia, Ib flows, the logical gate is not transferred to a voltage state unless a current exceeding 3I0 flows. When 2 input currents exceeding a current Ia= Ib=I0 flow, the logical gate circuit is transferred to the voltage state, and since the inductance is not used, an AND gate having a wide operation margin, which has been made small-sized is obtained.

Description

【発明の詳細な説明】 本発明はジ1セフソン効果を用いた論理ゲート回路に関
し、より具体的には積の論理を行なう電流注入製の論理
ダート回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic gate circuit using the Di1-Cefson effect, and more specifically to a current injection logic dart circuit that performs product logic.

ジー七7ノン効果を用いた論理ゲート回路は例えば文献
アプライド フィシ〜クス レター誌(Appli@d
 Physies Iatt@rm ) Vol、 3
3. N18. pp、7111〜70を参照すればわ
かるように、蟲技術分野では広(知られている。ヒれら
の論理ゲート回路では、値数個Oジ嘗セフソン接金と、
これらを電気的に紬会するインダクタンスからなるルー
プ−路で構成されたジ嘗セ7ソン干渉微論理ゲート回路
が干渉履論衰ゲート回路への直談の電流注入によって、
または干渉層論理ゲート回路の制御線中の入力電流との
電磁結合によってスイッチされる・第1IIは電流注入
により積O論島檜肴歌う論理ゲート回路の従来例1説−
するための図で、−)図は回路図、伽)図は該論理ゲー
ト回路の制御特性であp、横軸、縦軸はそれぞれ論理ゲ
ート回路に注入される2本の入力電流Ia%Ibt示す
。−)図において、10.11 tjそれぞれ゛ジ謬セ
フノン電流の臨界値がIo1%Ion であるジーセフ
ソン接合、 12.13はそれぞれインダクタンス値り
、%L2含有する一インダクタンス、14S Isはそ
れぞれ入力電流Ia%Ibが注入される入力電流路、1
6社出力釦117は負荷抵抗、18は*mである。
Logic gate circuits using the G77non effect are described, for example, in the literature Applied Physics Letters (Appli@d
Physies Iatt@rm) Vol, 3
3. N18. pp. 7111-70, it is widely known in the field of technology. In their logic gate circuit, several values of Sefson metallization and
The interference fine logic gate circuit, which is composed of a loop path made of inductance that connects these electrically, is created by directly injecting current into the interference logic decay gate circuit.
Or, it is switched by electromagnetic coupling with the input current in the control line of the interference layer logic gate circuit.The first theory is a conventional example of a logic gate circuit that produces products by current injection.
The -) figure is a circuit diagram, and the (a) figure is the control characteristic of the logic gate circuit, p, and the horizontal and vertical axes are the two input currents Ia%Ibt injected into the logic gate circuit, respectively. show. -) In the figure, 10.11 tj are respectively the G-Sefson junctions where the critical value of the fault current is Io1%Ion, 12.13 are the inductance values, respectively, the inductance containing %L2, and 14S Is are the input currents Ia, respectively. Input current path where %Ib is injected, 1
6 company output button 117 is load resistance, 18 is *m.

上記インダクタンス値L1、Iasジーセフソン臨界電
流値Io1、Ionの関係は LIIoim l4Io雪   ・・・−・・・・−・
・・・・・・・・・・・・・・・−〇)I6意(Ll 
+ Lx)−φ。 ・・・・−一・・・・・・・・・・
・・・・・・・・・・・(2)會濃足するように選ぶ。
The relationship between the above inductance value L1, Ias G-Sefson critical current value Io1, and Ion is LIIIoim l4Io snow...
・・・・・・・・・・・・・・・-〇)I6 (Ll
+Lx)-φ.・・・・-1・・・・・・・・・・・・
・・・・・・・・・・・・(2) Choose as many people as possible.

上式でφ。は磁束量子と呼゛ばれる自然定数で、2.0
7pH−m& m1ll gD値をもつ0(b) m 
4D m御勢性においては、図中、斜線部で示される領
域にλ力電111a、lbがあるときは、ジーセフノン
接合to、ii轢零電圧状謹にあり、従りて出力−路1
6には出力電流は流れておらず、該論理ゲート回路は論
理ovMIIKある。図中、斜線部で1にい領域はジ嘗
セツソシ績合10%11が有隈電圧状1!IIK遍移し
た状mt−示し、徹って出力−路16には出力電流が流
れ・竺、i、mグー)回路は論3110状態iIcある
O 積O論iat行なう論理ゲート回路Ow御畳性として社
、入力電@1aSt九轄Ibだけ流れている状態で咳論
理ゲート回路が電圧状態に遷移するに必at入力電11
16%家九轄IbO値に比べ、勢しい値O入力電流Ia
%Ibがと4に流飢て−る状態で、餓論理ダート回路が
電圧状態に遷移するに必IN′&人力電@ Ia (−
Ib )の値が小さい1、動作マージンが大きく、かつ
論理ゲート回路として05m4大きく、最適であると−
える・ 本論瀧ゲート回路においては、2つのジーセ7ソン後会
10 、11のジlセ7ソン臨界電流値O比Ica/I
on が30と1KIa−IbO状1で該論理ゲ−)l
lllが電圧状態に遷移するに必ll!な最小の入力電
流値Ia&よびToの値が、(Io1+ IM)/3 
m1llと1に膠、最も最適&制御畳性となる。従りて
入力電@Ia、ll5O値を2(I・1+ Ios)/
I II直に設計すれば、入力電流夏a%xbがと%K
tILれでいる状態は伽)−!0′eI[わさ些5、積
の論理を行なうことがわかる。
In the above formula, φ. is a natural constant called magnetic flux quantum, which is 2.0
0(b) m with a gD value of 7 pH-m & m1ll
In the 4D m control mode, when the λ power lines 111a and lb are in the shaded area in the diagram, they are in the G-Sefnon junction to, ii trip zero voltage state, and therefore the output-path 1
No output current flows through 6, and the logic gate circuit has a logic ovMIIK. In the figure, the shaded area is 1, where the diagonal voltage is 10% and 11 is 1! The output current flows through the output path 16, and the circuit is in the logic 3110 state iIc. In order for the logic gate circuit to transition to the voltage state when only the input voltage @1aSt and Ib is flowing, the input voltage 11 is required.
16% Stronger value O input current Ia than IbO value
In the state where %Ib is starved to 4, it is necessary for the starved logic dart circuit to transition to the voltage state.
If the value of Ib) is small 1, the operating margin is large, and the logic gate circuit is 05m4 large, it is optimal.
In this paper, in the waterfall gate circuit, the critical current value O ratio of the two circuits, 10 and 11, Ica/I
When on is 30 and 1KIa-IbO state 1, the logic game)
It is necessary for lll to transition to the voltage state! The minimum input current value Ia & To is (Io1+IM)/3
M1ll and 1 glue provide the most optimal & controlled mating properties. Therefore, input voltage @Ia, ll5O value is 2(I・1+Ios)/
I II If you design directly, the input current summer a%xb and %K
tIL is in a state of failure) -! 0'eI [wasa trivial 5, it can be seen that the logic of product is performed.

以上に述ぺ一′:如く、本論理ゲート回路は動作!゛°
′1 一ジνが大tIい、あるいは論理グー)回路としてO利
得が大1(1tうて高速動作が可能という長所管もりが
・同時に以下のような欠点も有するOlりの欠点韓前記
伽)式(?*件のため、電流レベルIo雪とインダクタ
ンス値L1s 14を同時に小さくすることができず、
l!うて一路OR造に大暑亀チップ面積を畳することで
ある・tf#−他の欠点性、鋏、論理ゲート回路がイン
メタタンスおよびジII噌フソン接舎O容量tともに含
む九め、高速動作のため減衰させなければならない共振
を有することである。さもにこのようta路は超電導状
111に転移するとき、浮遊011束をトラップし中す
く、ζOトラップされた磁束により誤動作を起ζす七云
う問題があった。
As stated above, this logic gate circuit works!゛°
'1 The advantage of the circuit is that it has a large gain of 1 (1 t) and can operate at high speed. At the same time, it also has the following disadvantages: )Formula (?*), it is not possible to reduce the current level Io and the inductance value L1s at the same time,
l! The key is to reduce the chip area in a single-direction OR structure. tf# - Other shortcomings, scissors, logic gate circuits include both inmetance and capacity, high-speed operation. Therefore, it has a resonance that must be damped. In addition, when such a ta path transitions to the superconducting state 111, it traps the floating 011 flux, causing a malfunction due to the ζO trapped magnetic flux.

本発@O目的は従来例の輪部ゲート回路と同様の広い動
作マージン、高い利得を維持しながら一前記欠点を除去
せしめ九ジ謬セフソシ効呆tm%/′hた電流注入朦論
理ゲート回路を提供するととにあるO 本発明によれは、一方がII地された第1のジ曽セフノ
ン接合に第1の入力線と、jllD抵抗の一端とをII
I!L、一方が接地された第20ジ曹セフノン接合に社
、出力−と、菖!!O抵抗の一端と管接続し、一方が接
地された第3のジ謬セフノン績舎には%jI2の入力−
と第3の抵抗の一端とを接続し、前記第1、第2sPよ
び第3011抗のそれぞれO偽畷紘一点で亙いEl!I
!されえことを特徴とするジーセフノ341會j11%
/%九電流注入瀧論履ゲート−路が得られる・ 以下1本発明をaiii管用IA−(@明する0第8i
g+a本11i@t)−実施例である1ジ嘗竜アソ/−
11JIk*M−九電流注入瀝論履ゲ−シ1路を説明す
る大めの図で%伽)閣は回路図、Ql)図はその一軸4
11性である。図#csI−いで30%31 、 a2
#iそれぞれジ嘗セアソシ臨界電流値Io1s Isか
Ioat有するジ曽七フン/II会、33、$4 * 
35はそれぞれ抵抗値r1、電、iの抵抗%86性抵抗
値諏盾有する負荷抵抗37でIl&端される出力鎗、3
8 、JIIJはそれぞれ入力信号Is s 1bO#
lれる入力線、40は接地を表わす0本実施例において
は前記ジ■セフノン臨界電流値、IM、1句、I(13
sシよび抵抗値1、糟5rJlは下記の関係式を構えす
ように設定されている・ I旬m Ion # I@/!!sl Io  ・”=
=・−・” I)r1纏r1−n/!!・−・−一・・
−一軸−(4)い12本の入力電jlIa 、 Ibの
うち、一方だけ、例えば入力電流1mだけが該論理ゲー
ト回路に注入され九と龜を想定する・IaOIlを(3
)式で定義されるIoよ)も大きく選べに、ジ謬セフノ
ン接合5oFi電圧状1liI#c遷移し、注入された
入力電FIL Iaa、抵抗33を流れた後、(4)式
の関係に従いh・Iaが抵抗34を通9て、ジ曽セフノ
ン綴合31#C%iたに・Iaが抵抗35を過りて、ジ
■セ7ソン接合32に注入される。ここで Ia ■≦1o   ・・・・・・・・・・−・・・・・・−
・−・・・・・・・・・−・−・ (5)Ia > I
o   −・・−・・・・・・・−・・−・−・−・・
・・−・・・ (6)の関係式が満たされれば、前記ジ
ーセフンン接会社、32は零電圧状IIKあり、出力線
36には出力電流は流れない。
The purpose of this invention is to eliminate the aforementioned drawbacks while maintaining the same wide operating margin and high gain as the conventional limbal gate circuit. According to the present invention, the first input line and one end of the jllD resistor are connected to the first jisocefnon junction, one of which is grounded, and one end of the jllD resistor is grounded.
I! L, the 20th dicarbonate junction with one side grounded, the output - and the irises! ! The input of %jI2 is connected to one end of the O resistor, and one end is grounded.
and one end of the third resistor, and each of the first, second sP and 3011th resistors is crossed at a single point El! I
! G-Sefno 341 meeting j 11% featuring Sareko
/% 9 current injection Taki logic gate-path is obtained・The following 1 present invention is used for aiii tube IA-(@clarified 0th 8i
g + a book 11i@t) - Example 1 Jijoryu Aso/-
11JIk*M-9 Current injection logic circuit 1 This is a large diagram to explain the circuit diagram.
She is 11 years old. Figure #csI-30%31, a2
#i Each has the critical current value Io1s Is or IoatJiso Shichifun/II Association, 33, $4 *
35 are the output rods, which are connected to the load resistor 37 having the resistance value r1, electric current, i, and the resistance value %86, respectively.
8, JIIJ is the input signal Is s 1bO#
In this embodiment, the input line 40 represents the ground.
s, resistance value 1, and resistance 5rJl are set so as to form the following relational expression.Ion #I@/! ! sl Io・”=
=・−・” I)r1 tate r1−n/!!・−・−1・・
- One axis - (4) Assume that only one of the 12 input currents jlIa and Ib, for example, only an input current of 1 m, is injected into the logic gate circuit, and IaOIl is (3
) is also largely selected, the dielectric junction 5oFi voltage state 1liI#c transitions, and after the injected input voltage FIL Iaa flows through the resistor 33, h according to the relationship of equation (4)・Ia passes through the resistor 34 and is injected into the junction 31#C%i through the resistor 35 and into the junction 32. Here, Ia ■≦1o ・・・・・・・・・・−・・・・・・−
・−・・・・・・・・・−・−・ (5) Ia > I
o −・・−・・・・・−・・−・−・−・・
. . . If the relational expression (6) is satisfied, the above-mentioned connection company 32 is in a zero voltage state IIK, and no output current flows through the output line 36.

次に下記の関係式を満足する入力電流!bが皺論理ゲー
ト回路に注入されると、 Ia/3 + Ib > Io  =−−==−−= 
 (7)Ia + Ik > 2Io   ==−”=
”===  (8)(7)式に従りてジ謬セ7ソン接合
店が電圧状mK遷移し、入力電fiIa、Ibはジ田セ
ツノン接合31に注入される。(荀式#C従うてジ嘗セ
フノン接合31も電圧状11に11111L、入力電流
Iawlbは出力−36を通うて負荷抵抗37に流れ込
む。入力電流1bがIaよ〕1先に@論理ゲート回路に
注入された場合は1上記e@明でIaとIbを入れ替え
れば、同様の説@が成夛立り・ 第31I伽)は(5)、(6)、(η、(荀式およびI
aとIbl入れ替え九FlllO式よ)得られる峡論理
ゲート回路の制御特性を示したものである◇本図かられ
かるようにλ力電jllIa−1bのうち1本だけが流
れている状態では、大きさ3I(1以上の入力電流が流
れないと該論通グート回路社電圧状態に遷移しない・一
方、大暑さの等しい入力tmIa−Ibが流れていると
I #iIa −Ib −Is以上の入力電流値が流れ
れば論理ゲート1路は電圧状lIK遷移する◎l!うて
、第111に従来例として示した電流注入層論理ゲート
回路と同様に1本発明の論理ゲート回路は広い動作マー
ジシ智ゲート1路・として高−利得を有しておp、高遮
な動作が可能である・さらに、本実施例etai注入履
論理ゲート回路では、ジ嘗セフソン臨界電流値、抵抗値
は−)、←)弐に示される相対的な関係式會満足すれば
良<、111図の従来例におけ墨前記錦)式のような回
路パラメータの絶対値を規定するような関係式がなく、
従ってリングラフィ技術の許す隈*Oa路の小渥化が可
能である。を九インダクタンスを用いていないため、イ
ンダクタンスとジ謬セツソン接合のキヤ、<ンタンスか
ら生ずる共振現象がなく、回路上、共振會抑える工夫を
施す必要がないatた超電導ループ回路を使ったゲート
回路ではないため、たとえ接地面で浮遊O磁場管トラッ
プし1しまりたとして4%何ら動作には影IPを受けな
い0 本実施例の電流注入朦論理ゲート回路は、その高利得特
性から電流増@器としても使用可能である。
Next, input current that satisfies the following relational expression! When b is injected into the wrinkled logic gate circuit, Ia/3 + Ib > Io =−−==−−=
(7) Ia + Ik > 2Io ==-”=
”=== (8) According to equation (7), the voltage level mK transition occurs at the junction junction 31, and the input voltages fiIa and Ib are injected into the junction 31. Therefore, the di-icefnon junction 31 is also in the voltage state 111111L, and the input current Iawlb passes through the output -36 and flows into the load resistor 37.If the input current 1b is injected into the logic gate circuit before Ia] 1 If Ia and Ib are swapped in the above e@Ming, a similar theory will come true.
This shows the control characteristics of the isthmus logic gate circuit obtained by exchanging a and Ibl (FlllO formula) ◇ As seen from this figure, when only one of the If an input current of magnitude 3I (1 or more) does not flow, it will not transition to the non-continuous circuit voltage state.On the other hand, if inputs tmIa-Ib of equal magnitude are flowing, an input of I #iIa -Ib -Is or more When a current flows, the logic gate 1 undergoes a voltage-like lIK transition ◎l!U!The logic gate circuit of the present invention has a wide operational margin, similar to the current injection layer logic gate circuit shown in No. 111 as a conventional example. It has a high gain as a single-channel gate, and is capable of high-blocking operation.Furthermore, in the injection logic gate circuit of this embodiment, the critical current value and resistance value are -) , ←) It is sufficient if the relative relational expression shown in 2 is satisfied.
Therefore, it is possible to make the Kuma*Oa path smaller as permitted by phosphorography technology. In a gate circuit using a superconducting loop circuit, there is no need to take measures to suppress resonance on the circuit, since no inductance is used. Therefore, even if a stray O magnetic field tube is trapped on the ground plane and becomes stuck, it will not affect the operation by 4%. It can also be used as

第3図は増幅器として本実施例を用いえ場合O構成を示
す0第2図の実施例における、入力電*xbが流れる入
力939には當に一定の電流Igt概しておく。動作マ
ージンを考慮して、電流値Igを入力電@ Ia m 
Oのときの、論理ゲートー路の臨界電流値31・Om 
K設定する・従って、そのときの動作点は112mの制
御41性において、41で表わすことがで龜ゐ。こO状
態で本論理ゲート1路を電圧状態に遷移させるに必豪な
最小や人力t ill IAはOj% I・である・電
圧状ll#ICおけゐジ曹セフノン接舎のリーク電流を
無視すれば、本論理ゲート回路の出力電流は3Io X
 O,75+ 0.25Io −2,,5Io と1に
り、電流利得lOが得られることElkゐ0111図に
示しえ従来例OIE流注入履論理ゲート回路における同
様の電流利得は、性1tss度であ〕、増幅器としてe
lms、本発′@O電流注入飄論理グート回路の方が壕
さることがわかる。なお、実際の動作では、動作マージ
ン等を考え、入力電流lムの大きさはOMI・よJIも
大きな値が選dれ、従りて、電圧状11KThける本論
理ゲート回路の動作点は第3wJ42 K対応するよう
な点に設定される・以上に述べてきえ如く、本発明のジ
ーセフソン効果を用い九電流注入鳳論理ゲート1路によ
れは、ジ酵セフノン集積回路管構成するうえでOSS本
的なゲート−路である、積6論理ゲート回路を、従来の
ジーセフノン干渉履論履ゲート回路に劣らぬ、広い動作
!−ジン、高利得特性を維持した11゜インダクタンス
を用いない構造の論理ゲート回路で実現できる。このた
め、上記の論理ゲート回路は、従来の干渉飄論理ゲート
回路と異1に9、回路の小蓋化が可能、共振現象を避け
るための回路上の工夫が不weの利点も同時に有する論
理ゲート−路であるe
FIG. 3 shows a configuration in which the present embodiment can be used as an amplifier. In the embodiment of FIG. 2, a constant current Igt is applied to the input 939 through which the input voltage *xb flows. Considering the operating margin, input current value Ig @ Ia m
The critical current value of the logic gate path when O is 31・Om
Set K. Therefore, the operating point at that time can be expressed as 41 in the control characteristic of 112 m. The minimum human effort needed to transition this logic gate 1 to the voltage state in this O state is Oj% I.・Ignore the leakage current of the voltage state ll#IC case and connection. Then, the output current of this logic gate circuit is 3Io
O,75+ 0.25Io -2,,5Io becomes 1, and a current gain of 10 is obtained.As shown in Fig. A], as an amplifier e
lms, it can be seen that the original '@O current injection logic gate circuit is more stable. In actual operation, considering the operating margin, etc., the magnitude of the input current lm is selected to be a large value for OMI and JI. Therefore, the operating point of this logic gate circuit with a voltage level of 11KTh is 3wJ42K is set at a point corresponding to K. As stated above, the 9 current injection logic gate 1 circuit using the G-Sefson effect of the present invention is suitable for the OSS book in constructing the D-Cefson integrated circuit tube. The product 6 logic gate circuit, which is a gate-path, has a wide range of operation that is comparable to the conventional gsefnon interference logic gate circuit! - It can be realized with a logic gate circuit having a structure that does not use an 11° inductance while maintaining high gain characteristics. For this reason, the logic gate circuit described above is different from conventional interference-based logic gate circuits in that it can be made smaller in size, and it also has the advantage that it is not possible to make circuit improvements to avoid resonance phenomena. gate-road e

【図面の簡単な説明】[Brief explanation of the drawing]

第imlはジ−セフノン効果を用い九電流注入皺論理ゲ
ート回路の従来例を説明する丸めの図で、(a)は回路
図、(b)は皺論理ゲート回路の制御特性管示す0 同図−)において、10%llはジ−セフノン効果、1
2.13はインダクタンス、14 % 15は入力電流
路1.6゜ヵ11.7o−・::一0.1jF、*m?
あ、。、同ml (b) において20は鋏ゲート(ハ
)路が積の論理動作を行なう動作点を示すO 第2図は本発明のジ−セフノン効果を用い九電流注入蓋
論理ゲート回路の一実施例を説−するためOllで、(
ロ)は回路図、伽)は腋論理ダート回路の制御特性であ
る。岡ll(転)において30.31.32t!ジ謬−
に7ノンwk舎、33 % 34 s 315 a抵抗
、36ハ出力線、17#i負゛荷抵抗、38.39は入
力線、40tj接地を示す〇岡1iI(転)において4
1.42紘諌論理ゲート1路を電流増幅器として用いた
場合O動作点を示す。 gssaは第3図に示す本発−の一実施例である・電線
注入撒論理ゲート回路を電流増IIIIとして用いた場
合O構成を示す回路図である。 1PJ1図 ((2) lΔ tb) −、)bIo++Iog 晃 2 図 (Q) Cb)
No. iml is a rounded diagram explaining a conventional example of a nine-current injection wrinkled logic gate circuit using the G-Cefnon effect, (a) is a circuit diagram, and (b) is a diagram showing the control characteristics of the wrinkled logic gate circuit. -), 10%ll is the di-cefnon effect, 1
2.13 is the inductance, 14% 15 is the input current path 1.6° 11.7o-:-0.1jF, *m?
a,. , the same ml (b), 20 indicates the operating point at which the scissor gate (c) circuit performs the product logic operation. To illustrate an example, in Oll (
B) is the circuit diagram, and C) is the control characteristic of the armpit logic dart circuit. 30.31.32t in Okall (transformation)! The error
7 non-wk building, 33% 34s 315 a resistance, 36c output line, 17#i load resistance, 38.39 is input line, 40tj grounding 〇oka 1iI (turn) 4
1.42 When one logic gate is used as a current amplifier, the O operating point is shown. GSSA is an embodiment of the present invention shown in FIG. 3. It is a circuit diagram showing an O configuration when a wire injection logic gate circuit is used as a current increase III. 1PJ1 figure ((2) lΔ tb) −,)bIo++Iog Akira 2 figure (Q) Cb)

Claims (1)

【特許請求の範囲】[Claims] 一方がII地された第1のジ■セ7ソン接会に、$11
の入力鐘とll110抵抗01端とte絖し、一方が接
地されたjI20ジ■47ノン接合には、出力−と、籐
2の抵抗の一端とを接続し、一方が接地されたJI3の
ジ■セフソシ接合には、第2の入力−と、第30抵抗の
一端とを接続し、前記第1゜第2、および@SO抵抗の
それぞれの他端は一点で互い#C接続されたことを特徴
とするジ曹七フソン効果を用いた電流注入瀝論理ゲート
回路。
$11 for the 1st Ji Se 7 Son meeting where one was placed II
Connect the input bell to the terminal of the resistor 01 of ll110, one end of which is grounded, and the non-junction of jI20 of ■ Connect the second input - and one end of the 30th resistor to the safe junction, and make sure that the other ends of the 1st, 2nd, and @SO resistors are #C connected to each other at one point. A current injection logic gate circuit using the characteristic Jiso-Nanfuson effect.
JP56142749A 1981-09-10 1981-09-10 Current injection type logical gate circuit using josephson effect Granted JPS5843631A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP56142749A JPS5843631A (en) 1981-09-10 1981-09-10 Current injection type logical gate circuit using josephson effect
EP82108223A EP0074604B1 (en) 1981-09-10 1982-09-07 Circuit utilizing josephson effect
DE8282108223T DE3268138D1 (en) 1981-09-10 1982-09-07 Circuit utilizing josephson effect
US06/415,877 US4538077A (en) 1981-09-10 1982-09-08 Circuit utilizing Josephson effect
CA000411147A CA1189916A (en) 1981-09-10 1982-09-10 Circuit utilizing josephson effect
AU88311/82A AU553981B2 (en) 1981-09-10 1982-09-10 Josephson junction and gate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56142749A JPS5843631A (en) 1981-09-10 1981-09-10 Current injection type logical gate circuit using josephson effect

Publications (2)

Publication Number Publication Date
JPS5843631A true JPS5843631A (en) 1983-03-14
JPH0234493B2 JPH0234493B2 (en) 1990-08-03

Family

ID=15322682

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56142749A Granted JPS5843631A (en) 1981-09-10 1981-09-10 Current injection type logical gate circuit using josephson effect

Country Status (1)

Country Link
JP (1) JPS5843631A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62151694A (en) * 1985-12-23 1987-07-06 日本ラインツ株式会社 Member for sealing exhaust pipe joint section and manufacture thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62151694A (en) * 1985-12-23 1987-07-06 日本ラインツ株式会社 Member for sealing exhaust pipe joint section and manufacture thereof
JPH0546476B2 (en) * 1985-12-23 1993-07-14 Nippon Reinz Co Ltd

Also Published As

Publication number Publication date
JPH0234493B2 (en) 1990-08-03

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