JPS61274422A - Current injection type logical gate circuit using josephson effect - Google Patents
Current injection type logical gate circuit using josephson effectInfo
- Publication number
- JPS61274422A JPS61274422A JP60087927A JP8792785A JPS61274422A JP S61274422 A JPS61274422 A JP S61274422A JP 60087927 A JP60087927 A JP 60087927A JP 8792785 A JP8792785 A JP 8792785A JP S61274422 A JPS61274422 A JP S61274422A
- Authority
- JP
- Japan
- Prior art keywords
- current
- gate
- circuit
- junction
- gate circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明はジ羅セフソン効果を用いた電流注入型論理ゲー
ト回路に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a current injection type logic gate circuit using the Jira Sefson effect.
(従来技術とその問題点)
ジョセフソン接合と抵抗とよりなる電流注入製論理ゲー
ト回路としては、いくつかの回路製式が提案されており
、その1例はアプライド、フィジックス、レターズ誌(
Applied Physics Letters)第
40巻、第8号、第741〜744頁に示される抵抗結
合域ジ璽セフソン論理回路である。(Prior art and its problems) Several circuit construction methods have been proposed for current injection logic gate circuits consisting of Josephson junctions and resistors, one example of which is published in Applied, Physics, Letters (
This is a resistance-coupled area Jisefson logic circuit shown in Applied Physics Letters, Vol. 40, No. 8, pp. 741-744.
第2図は従来例である和の論理を行なう電流注入型論理
ゲート回路の回路図を示す。該論理ゲートは各々臨界電
流値2工。/3.工。、■。をもつ3つの接合10.
11. 12.同一の抵抗値rをもつ4つの抵抗13〜
16からなっているロ該論理ゲート回路は電源電流供給
端子17よシゲート電流工 が供給され、工 は抵抗1
3.15で2等分さg
g
れた後、接合11.12を通って、接地18へ流れ込む
◇この状態で入力電流工、が入力端子19n
よシ注入されると、接合11.12がこの順に零電圧状
態から高抵抗状態にスイッチし、ゲート電流I は主に
接合IQ、抵抗16を通って接地に流れるようになる。FIG. 2 shows a circuit diagram of a conventional current injection type logic gate circuit that performs summation logic. The logic gates each have a critical current value of 2m. /3. Engineering. ,■. Three junctions with 10.
11. 12. Four resistors 13~ with the same resistance value r
16, the logic gate circuit is supplied with a gate current from a power supply current supply terminal 17, and is connected to a resistor 1.
3.15 equal parts g
◇In this state, when the input current is injected into the input terminal 19n, the junctions 11 and 12 change from a zero voltage state to a high resistance state in this order. The gate current I mainly flows through the junction IQ and the resistor 16 to ground.
この時、接合10を流れる電流が臨界電流値2I/3を
越えると、接合10は高抵抗状態にスイッチし、ゲート
電流工、は出力端子20に流れ出し、また入力電流Ii
nは入力端子よシ抵抗16を通りて接地に流れ、入出力
分離が果たされるとともにゲート回路のスイッチングが
完了する。上記の説明よ)該ゲート回路のスイッチング
動作中、入力抵抗16には接合10がスイッチする直前
に最大となる工tn+2Io/3 トいう値の電流が流
れることがわかる。At this time, when the current flowing through the junction 10 exceeds the critical current value 2I/3, the junction 10 switches to a high resistance state, the gate current flows out to the output terminal 20, and the input current Ii
n flows from the input terminal to ground through the resistor 16, thereby completing input/output separation and completing switching of the gate circuit. It can be seen that during the switching operation of the gate circuit (according to the above explanation), a current of a maximum value of tn+2Io/3 flows through the input resistor 16 immediately before the junction 10 switches.
第3図は第2図の和の論理ゲート回路をファン・イン2
.ファン・アウト2の構成で接続したものである0図中
、21,22.23は該論理ゲート回路を示し、17,
19.20は各々第1図同様、電源電流供給端子、入力
端子、出力端子を表わす。ゲート21とゲート22は線
路24.負荷抵抗25.ゲート23とゲート22は線路
26゜負荷抵抗27を通じて各々接続されている。ゲー
ト21が入力電流工、。の印加によシミ圧状態にスイッ
チすると、ゲート電流工、は出力電流とな9等分されて
、その一方が線路24.抵抗25を流れ、ゲート22に
入力される。この結果、ゲート22は電圧状態ヘスイッ
チするが、この時ゲート23は零電圧状態であシ、抵抗
27はゲート回路22の入力端子19よシ、ゲート回路
23の前記ジョセフソン接合12を通って接地されてい
ることになる。このため、第2図のゲート回路の動作に
おいて説明したスイッチング動作中に入力抵抗16に流
れる電流I、、+2I。/3=Ig/2+2I。/3は
入力抵抗16と負荷抵抗27に、両者の抵抗比に従った
大きさで分流され流れ込む。通常の設計では入力抵抗1
6の抵抗値rと負荷抵抗27の抵抗値rLの比r/rL
は1/lO程度なのでゲート22のスイッチング動作中
、ゲート23には線路26を通りてゲート23の前記ジ
曹セフソン接合12K(Ig/2+2I。/3)/10
の大きさのリーク電流が流れ込むことになる。前記接合
12にはゲート電流Igの印加によう既に工、/2の大
きさの電流が流れているので、前記リーク電流により前
記ジ日セフソン接合12がスイッチしないためには
(I、/2+2I。/3 )/10<Io−Ig/2既
ち、Ig(1,716にゲート電流を設定しておく必要
がらる0もし、ゲート電流Igを1.7I0以上に設定
すると、前記リーク電流によシ前記ゲート回路23の前
記接合12が電圧状態にスイッチし、ゲート電流工 が
前記ゲート23の前記接合11に集中して流れるように
な勺、接合11がンδツチする。続いて、ゲート電流I
gは前記ゲート23の前記接合10に集中して流れ、接
合lOも電圧状態にスイッチし、ゲート電流Igは、ゲ
ート回路23の出力電流として線路26,28に流れる
ようになる。これは前記ゲート23が入力電流が印加さ
れていないにもかかわらず、出力電流を出力したことに
対応し、ゲート回路が誤動作をしたことになる0このよ
うなリーク電流によるゲート回路の誤動作が生じなけれ
ば、ゲート回路のゲート電流工は2I ’!で増大さ
せても正常動作が保g 。Figure 3 shows the sum logic gate circuit in Figure 2 as a fan-in 2
.. In the figure, 21, 22, and 23 indicate the logic gate circuits connected in a fan-out 2 configuration, and 17,
19 and 20 respectively represent a power supply current supply terminal, an input terminal, and an output terminal as in FIG. Gate 21 and gate 22 are connected to line 24. Load resistance 25. The gates 23 and 22 are connected through a line 26 and a load resistor 27, respectively. Gate 21 is the input current. When switched to the stain pressure state by applying , the gate current is divided into nine equal parts as the output current, one of which is connected to the line 24. The signal flows through the resistor 25 and is input to the gate 22. As a result, the gate 22 switches to a voltage state, while the gate 23 is in a zero voltage state and the resistor 27 is connected to the input terminal 19 of the gate circuit 22 and to ground through the Josephson junction 12 of the gate circuit 23. This means that it has been done. Therefore, the currents I, , +2I flowing through the input resistor 16 during the switching operation described in the operation of the gate circuit in FIG. /3=Ig/2+2I. /3 is shunted and flows into the input resistor 16 and the load resistor 27 in a magnitude according to their resistance ratio. In a typical design, the input resistance is 1
Ratio r/rL of resistance value r of 6 and resistance value rL of load resistor 27
is about 1/1O, so during the switching operation of the gate 22, the dicarbonate Sefson junction 12K(Ig/2+2I./3)/10 of the gate 23 passes through the line 26 and passes through the line 26 to the gate 23.
A leakage current of the magnitude will flow. Since a current of magnitude /2 is already flowing through the junction 12 due to the application of the gate current Ig, in order for the dielectric junction 12 not to switch due to the leakage current, (I, /2+2I) is required. /3)/10<Io-Ig/2 It is necessary to set the gate current to Ig(1,716)0 If the gate current Ig is set to 1.7I0 or more, the leakage current When the junction 12 of the gate circuit 23 switches to a voltage state and the gate current flows concentratedly to the junction 11 of the gate 23, the junction 11 turns on.Subsequently, the gate current I
g flows concentratedly in the junction 10 of the gate 23, the junction IO is also switched to a voltage state, and the gate current Ig flows to the lines 26, 28 as the output current of the gate circuit 23. This corresponds to the fact that the gate 23 outputs an output current even though no input current is applied, and the gate circuit malfunctions. This leakage current causes the gate circuit to malfunction. If not, the gate current of the gate circuit is 2I'! Normal operation is maintained even when increased.
証されるわけなので、上記のリーク電流による誤動作は
ゲートの動作マージンを著しく制限していることになる
◎これを防ぐためには負荷抵抗値r1と入力抵抗rとの
比を大きく取ればよいわけだが、ゲートの出力電流を十
分に取るために負荷抵抗値r1とゲート電流工、との積
は超電体材料固有の量であるギャップ電圧7g以下に設
定しなければならず、また入力抵抗rを下げることも1
文献電子通信学会電子デバイス研究会資料ED83−5
1号、第39頁に述べられている如く、ゲートのスイッ
チング時間を増大させることになプ、ジ璽セフソン効果
を用いたゲート回路のもつ高速スイッチング特性を著し
く損なうことになる。Therefore, the malfunction due to the leakage current described above significantly limits the operating margin of the gate. To prevent this, the ratio between the load resistance value r1 and the input resistance r should be increased. , in order to obtain a sufficient gate output current, the product of the load resistance value r1 and the gate current must be set to a gap voltage of 7g or less, which is an amount specific to the superelectric material, and the input resistance r must be set to 7g or less. You can also lower it by 1
References Institute of Electronics and Communication Engineers Electronic Devices Study Group Materials ED83-5
As stated in No. 1, page 39, increasing the switching time of the gate significantly impairs the high-speed switching characteristics of the gate circuit using the G-Sefson effect.
(発明の目的)
本発明の目的は従来の論理ゲート回路の持つ狭いゲート
電流マージン特性を除去した新規なジ育セ7ソン効果を
用いた電流注入型論理ゲート回路を提供することにある
。(Objective of the Invention) An object of the present invention is to provide a current injection type logic gate circuit using a novel dielectric effect that eliminates the narrow gate current margin characteristic of conventional logic gate circuits.
(発明の構成)
本発明によれば複数個の前段論理ゲート回路の出力端子
と次段論理ゲート回路の入力端子とが接続されてなるジ
目セフソン効果を用いた電流注入型論理ゲート回路にお
いて、前記出力端子に第1の抵抗を接続し、該第1の抵
抗の他の一端に第2の抵抗を接続し、該第2の抵抗の他
の一端を前記入力端子に接続し、前記第1の抵抗と第2
の抵抗の接続点と接地との間にジョセフソン接合を接続
したことを特徴とする前記ジョセフソン接合を用いた電
流注入型論理ゲート回路が得られる。(Structure of the Invention) According to the present invention, in a current injection type logic gate circuit using the Jime Sefson effect, in which the output terminals of a plurality of pre-stage logic gate circuits and the input terminals of a next-stage logic gate circuit are connected, A first resistor is connected to the output terminal, a second resistor is connected to the other end of the first resistor, another end of the second resistor is connected to the input terminal, and the first resistor is connected to the input terminal. resistance and the second
A current injection type logic gate circuit using the Josephson junction is obtained, characterized in that the Josephson junction is connected between the connection point of the resistor and the ground.
(構成の詳細な説明、実施例)
以下、本発明を図面を用いて説明する。第1図は本塁間
の一実施例であるジョセフソン接合を用いた電流注入量
論理ゲート回路を説明するための図である。本実施例で
はファン・インを2とした論理ゲート回路を想定してい
る。図中に示される3個の電流注入屋ゲート回路30,
31.32の各々は例えば第2図に等価回路で示した論
理ゲート回路と同一の回路構造を持つも、のと想定する
。(Detailed Description of Configuration, Examples) The present invention will be described below with reference to the drawings. FIG. 1 is a diagram for explaining a current injection amount logic gate circuit using a Josephson junction, which is an example of a home base. In this embodiment, a logic gate circuit with a fan-in of 2 is assumed. Three current injection gate circuits 30 shown in the figure,
It is assumed that each of 31 and 32 has the same circuit structure as the logic gate circuit shown as an equivalent circuit in FIG. 2, for example.
論理ゲート回路32の入力端子19には第2の抵抗であ
る抵抗33.34が接続され、さらに該抵抗33.34
には各々の一端が接地されたジョセフソン接合35.3
6が接続され、該接続点37゜38には第1の抵抗であ
る抵抗39.40を介して前段のゲート回路30.31
の出力端子が接続される。A second resistor 33.34 is connected to the input terminal 19 of the logic gate circuit 32;
Josephson junction 35.3 with one end of each grounded.
6 is connected to the connection point 37.38, and the previous stage gate circuit 30.31 is connected to the connection point 37.38 via the first resistance 39.40.
output terminal is connected.
ここで前記各接続点37.38から入力される入力電流
の大きさを工、とすると、前記ジ冒セフ鳳n
ソン接合35.36の臨界電流値工、はを満足するよう
に選ばれる。ここで2I/3は接合10の臨界電流値、
rは抵抗16の抵抗値、RLは抵抗33.34の抵抗値
である。前段のゲート回路30.31のどちらか、例え
ば30が電圧状態にスイッチすると出力電流は前記接合
35に流れ込む。上記の条件式よシこのときの出力電流
の大きさI、は接合35の臨界電流値11より太き用い
ので、接合35はスイッチし、前段のゲート回路30の
出力電流が入力端子19より注入され、ゲート回路32
のスイッチングが起きる。このスイッチング動作中、抵
抗16および抵抗34に流れる最大電流の総和は、第2
図の従来例のゲートで、抵抗34を通って接合36に流
れ込む電流はいので、接合36は零電圧状態のままであ
る。従って前記接続点38よシ抵抗40を介して接続さ
れたゲート回路31には何もリーク電流は流れ込まず、
ゲート回路31の誤動作スイッチングは起きない。本実
施例のゲート回路を用い、第1図の構成′のような論理
ゲート回路のネットワークを作となる。動作マージンを
考慮した典型的なゲート電流設定値I=1.5Iを用い
ると曲成はg 。Here, if the magnitude of the input current input from each of the connection points 37 and 38 is , then the critical current value of the junction 35 and 36 is selected to satisfy . Here, 2I/3 is the critical current value of junction 10,
r is the resistance value of the resistor 16, and RL is the resistance value of the resistor 33.34. When either of the preceding gate circuits 30, 31, for example 30, switches to a voltage state, the output current flows into the junction 35. According to the above conditional expression, the magnitude of the output current I at this time is larger than the critical current value 11 of the junction 35, so the junction 35 is switched and the output current of the previous gate circuit 30 is injected from the input terminal 19. and the gate circuit 32
switching occurs. During this switching operation, the sum of the maximum currents flowing through the resistor 16 and the resistor 34 is the second
In the conventional gate shown, no current flows through resistor 34 into junction 36, so junction 36 remains at a zero voltage state. Therefore, no leakage current flows into the gate circuit 31 connected from the connection point 38 through the resistor 40.
Malfunction switching of the gate circuit 31 does not occur. Using the gate circuit of this embodiment, a network of logic gate circuits as shown in FIG. 1 can be constructed. Using a typical gate current setting value I = 1.5I, which takes operational margin into account, the bending is g.
接合35.36の臨界電流値を選べば良いことがわかる
。It can be seen that the critical current value of junctions 35 and 36 should be selected.
(発明の効果)
以上、本発明によるジョセフソン接合を用いた電流注入
型論理ゲート回路を用いれば、7ア/・インが複数のゲ
ート回路がスイッチした時に生ずるリーク電流が該ゲー
ト回路の入力端子に抵抗を介して接続されたジョセフソ
ン接合によシ吸収されるので、該ゲート回路の入力4子
と接続される前段の、零電圧状態にあるゲート回路には
出力側から何らリーク電流は注入されず、ゲート回路の
ゲート電流値I を入力電流が印加されない時のゲート
回路のゲート電流しきい値工m(前記実施例においては
2 I。)まで上げることができ、ゲート回路を広いゲ
ート電流マージンで動作させるととができる。また本発
明では、この目的を入力抵抗値を下げることなく実現で
きるので、ゲート回路の遅延時間を増大させることもな
い。(Effects of the Invention) As described above, if a current injection type logic gate circuit using a Josephson junction according to the present invention is used, the leakage current generated when a plurality of gate circuits is switched is the input terminal of the gate circuit. Since the leakage current is absorbed by the Josephson junction connected to the gate via a resistor, no leakage current is injected from the output side into the gate circuit in the zero voltage state in the previous stage connected to the four inputs of the gate circuit. The gate current value I of the gate circuit can be increased to the gate current threshold value m (2 I in the above embodiment) of the gate circuit when no input current is applied, and the gate current value I of the gate circuit can be increased to a value of 2 I. If you operate it in the margin, you can do it. Furthermore, in the present invention, this objective can be achieved without lowering the input resistance value, so there is no need to increase the delay time of the gate circuit.
第1図は本発明のジョセフソン接合を用いた電流注入型
論理ゲート回路から構成されるネットヮ−クを説明する
ための回路図、第2図は電流注入型論理ゲート回路の従
来例を説明するだめの回路図、第3図は従来例の電流注
入型論理ゲート回路から構成されるネットワークを説明
するための回路図である。
10、 11. 12・・・ジ1セ7ン/接合、13゜
14.15.16・・・抵抗、17・・・電源電流供給
端子、18・・・接地、19・・・入力端子、20・・
・出力端子、21,22.23・・・電流注入型論理ゲ
ート回路、24,26,28・・・出力線、25. 2
7・・・負荷抵抗、 30. 31. 32・・・電流
注入屋論理ゲート回路、33,34,39,40・・・
抵抗、35゜36・・・ジ冒セ7ソン接合、37.38
・・・接続点0氏子人弁7士内IK 晋
第2 図
第3図Fig. 1 is a circuit diagram for explaining a network constructed from a current injection type logic gate circuit using the Josephson junction of the present invention, and Fig. 2 is a circuit diagram for explaining a conventional example of a current injection type logic gate circuit. The circuit diagram shown in FIG. 3 is a circuit diagram for explaining a network constructed from conventional current injection type logic gate circuits. 10, 11. 12...Ji1sen/junction, 13°14.15.16...Resistor, 17...Power supply current supply terminal, 18...Grounding, 19...Input terminal, 20...
- Output terminal, 21, 22. 23... Current injection type logic gate circuit, 24, 26, 28... Output line, 25. 2
7...Load resistance, 30. 31. 32... Current injection shop logic gate circuit, 33, 34, 39, 40...
Resistance, 35° 36... Jisen 7son junction, 37.38
・・・Connection point 0 Shrine Jinben 7 Shinai IK Shin 2nd Figure 3
Claims (1)
論理ゲート回路の入力端子とが接続されてなるジョセフ
ソン効果を用いた電流注入型論理ゲート回路において、
前記出力端子に第1の抵抗を接続し、該第1の抵抗の他
の一端に第2の抵抗を接続し、該第2の抵抗の他の一端
を前記入力端子に接続し、前記第1の抵抗と第2の抵抗
の接続点と接地との間にジョセフソン接合を接続したこ
とを特徴とする前記ジョセフソン効果を用いた電流注入
型論理ゲート回路。In a current injection logic gate circuit using the Josephson effect, in which the output terminal of each of a plurality of pre-stage logic gate circuits is connected to the input terminal of the next-stage logic gate circuit,
A first resistor is connected to the output terminal, a second resistor is connected to the other end of the first resistor, another end of the second resistor is connected to the input terminal, and the first resistor is connected to the input terminal. A current injection type logic gate circuit using the Josephson effect, characterized in that a Josephson junction is connected between the connection point of the resistor and the second resistor and ground.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60087927A JPS61274422A (en) | 1985-04-24 | 1985-04-24 | Current injection type logical gate circuit using josephson effect |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60087927A JPS61274422A (en) | 1985-04-24 | 1985-04-24 | Current injection type logical gate circuit using josephson effect |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61274422A true JPS61274422A (en) | 1986-12-04 |
JPH0516772B2 JPH0516772B2 (en) | 1993-03-05 |
Family
ID=13928548
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60087927A Granted JPS61274422A (en) | 1985-04-24 | 1985-04-24 | Current injection type logical gate circuit using josephson effect |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61274422A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59181725A (en) * | 1983-03-31 | 1984-10-16 | Agency Of Ind Science & Technol | Resistance coupling type josephson decoder |
JPS59185428A (en) * | 1983-04-05 | 1984-10-22 | Agency Of Ind Science & Technol | Resistance coupling type josephson decoder circuit |
-
1985
- 1985-04-24 JP JP60087927A patent/JPS61274422A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59181725A (en) * | 1983-03-31 | 1984-10-16 | Agency Of Ind Science & Technol | Resistance coupling type josephson decoder |
JPS59185428A (en) * | 1983-04-05 | 1984-10-22 | Agency Of Ind Science & Technol | Resistance coupling type josephson decoder circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH0516772B2 (en) | 1993-03-05 |
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