JPS6157739B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a superconducting logic gate that uses Josephson junctions and is capable of low-power, high-speed operation and has a wide operating margin.

Conventionally, various types of superconducting logic gates have been proposed. Among these, the inventors previously proposed in Japanese Patent Application No. 55-78082 that since no inductance is included in the loop, it is compact, capable of high-speed, low-power operation, has high sensitivity, and has a large number of output lines. Furthermore, we presented a superconducting logic gate that has features such as being able to operate stably without being affected by external magnetic fields. FIG. 1a shows its circuit configuration, and FIG. 1b shows its operating threshold characteristic diagram.

In the figure, T ₁ and T ₂ are signal input terminals, T ₀ is an output terminal, G is a ground terminal, R ₁ , R ₂ , R ₃ , and R _L are resistors.
J ₁ , J ₂ , and J ₃ are Josephson junctions, and P ₁ is the intersection of resistance R ₁ and Josephson junction J ₁ . For details of the structure, operation, effects, etc. of this circuit, please refer to Japanese Patent Application No. 55-78082, and an outline thereof will be shown here.

As shown in Figure 1, the gate circuit structure proposed earlier incorporates Josephson junctions and resistors in a bridge shape. The usual method of use is to connect a load resistor R _L to the resistor R L and use the current flowing into it as an output. The operation of this logic gate will be explained with reference to FIG. The current to be drawn into the load resistor after the logic gate switches is supplied to the input terminal T1 as a gate bias current I _g .

(Step 1) In this state, a portion of I _g flows to ground through resistor R1, superconducting (resistance O) junction J1, and J2 as shown by the solid line, and the rest flows through resistor R3 and junction J3. flows through the ground to ground. In this case, since the junction J3 is in a superconducting state, the load R _L
No current flows. In this state, input terminal T2
If a control current: I _c is supplied to , all of it flows to ground through the superconducting junction J2. This is because other branches have finite resistance and cannot flow there. In addition,
When supplying currents I _g and I _c , resistors R1,
Let the values of R2, R3, and R _L be R ₁ , R ₂ , R ₃ , and R _L , respectively, and let the maximum superconducting current (or maximum Josephson current) of Josephson junctions J ₁ , J ₂ , and J ₃ be Let I ₁ , I ₂ , I ₃ .

In step 1 of Fig. 5, in the direction of the arrow,
A current flows through each Josephson junction.

That is, only a branched portion of I _g flows through Josephson junctions J ₁ and J ₃ . According to the theory of electric circuits, the current flowing through J ₁ is easily R ₃ /R ₁ + R ₃ I _g , and J ₃
It is derived that R ₁ /R ₁ +R ₃ I _g flows.

On the other hand, in Josephson junction J ₂ , the above-mentioned branched portion of I _g and I _c all flow in the same direction.

Therefore, R ₃ /R ₁ +R ₃ I _g +I _c flows to J ₂ .

Therefore, R ₃ /R ₁ +R ₃ I _g +I _c >I ₂ (1) R ₃ /R ₁ +R ₃ I _g <I ₁ (2) R ₁ /R ₁ +R ₃ I _g <I ₃ .........(3) Each resistance value R ₁
~ _R3 , the supply current values _Ig , _Ic , and the maximum superconducting current values _I1 to _I3 of each Josephson junction, only the Josephson junction _J2 switches to the voltage state (high resistance state), A state in which J ₁ and J ₃ are maintained in a superconducting state (see step 2) can be realized.

Note that when each of the above equations (1) to (3) is illustrated in a diagram with I _g on the vertical axis and I _c on the horizontal axis, as shown in Figure 1b, they are represented by straight lines indicated by , respectively. Of the areas divided into two, this is the area indicated by the arrow.

Note that FIG. 1b consists of a group of straight lines indicating the threshold values at which each Josephson junction switches to a high resistance state, and the overlapping range of these regions is the operating region that determines the normal operating region of the Josephson logic gate. In this logic gate, input and output can be separated and normal operation can be performed by setting I _g and I _c , respectively, as shown in the shaded area A, which will be explained in detail later. . In addition, in region B with horizontal lines, the logic gate is switched and current can be taken out to the load resistor, but the input I
This shows a state in which current is taken out to the load without separation of bias _Ig and bias _Ig .

It should be noted that the slope of the straight line in Fig. 1 b, which shows the above equation (1), is large, and that the slope is the resistance R ₁ , R ₃
By the ratio of , if other conditions are ignored, it can be made arbitrarily large. That is, the greatest feature of this logic gate is that the sensitivity of the gate can be increased.

(Step 2) When Josephson junction _J2 switches to a high resistance state, the combined resistance value of the parallel circuit: P of _J2 and _R2 changes. If the value of resistor R ₂ is set to be sufficiently small compared to the high resistance after J ₂ switches (this usually becomes a sub-gap resistance), the combined resistance value of parallel circuit: P (this R ₂ ′) is approximately R ₂ . That is, R ₂ ′≒R ₂ .

Therefore, in the following operation, R ₂ '=R ₂ will be explained. Parallel circuit: When the combined resistance value of P changes, the shunt state of I _g and I _c changes. That is,
As shown in step 2 of Fig. 5, I _g is (R ₃ and
J ₃ ) and {R ₁ and J ₁ and P: (i.e. J ₂ and R ₂
parallel circuit)}. Also I _c
is divided into a component flowing through {P} and a component flowing through {J ₁ , R ₁ , R ₃ , and J ₃ }. Note that since J ₃ is in a superconducting state, no current flows through the load R _L at this stage.

Furthermore, as is clear from the arrows (solid line, dotted line) shown in step 2, the branched portions of I _g and I _c flow in the same direction in J ₃ , but flow in opposite directions in J ₁ .

Therefore, it is easier to set _J3 to enter the high resistance state first. When determining the conditions for J ₃ to switch to a high resistance state, I _c is R ₂ /R ₁ +R ₂ +R ₃ and R ₁ +R ₃ /R ₁ +
Of the divided R ₂ + R ₃ , the former flows to J ₃ and the latter flows to J ₁ . Similarly, I _g is R ₁ +R ₂ /R ₁ +R ₂ +R ₃ and R ₃ /R ₁ +R
₂ + R ₃ , the former flows to J ₂ and the latter flows to J ₁ in the opposite direction.

Therefore, if the following relationship is obtained: R ₁ +R ₂ /R ₁ +R ₂ +R ₃・I _g +R ₂ /R ₁ +R ₂ +R ₃・I _c >I ₃ (4), then Josephson junction J ₃ Switch to high resistance state and proceed as shown in step 3.
J ₁ is in a superconducting state, and J ₂ and J ₃ are in a high resistance state.
When J ₃ becomes a high resistance state, its resistance value becomes approximately the sub-gap resistance of J ₃ , and the externally added resistance R
It is usually larger than _L. Therefore, the output current flows to R _L .

The threshold value of equation (4) above is shown by the straight line in FIG. 1b, and the area indicated by the arrow is the area where _J3 is switched.

(Step 3) When Josephson junction J ₃ switches to a high resistance state, the parallel combined resistance value of J ₃ and load resistor R _L changes similarly to the parallel circuit P of R ₂ and J ₂ described above.
Further, since the resistance after the Josephson junction is normally switched to the high resistance state is an extremely high resistance value on the order of sub-gap resistance, its value is also extremely high compared to the value of the load resistance R _L . Therefore, if the parallel combined resistance value of J ₃ and R _L is R _L ', then R _L '= _RL . Therefore, in the following description, it will be assumed that R _L '=R _L . As shown in the diagram in step 3, J ₂ and
When J ₃ becomes high resistance and J ₁ becomes superconducting, I _g and I _c are divided as shown below.

That is, I _g is the component that flows to the ground via {R ₃ and (parallel circuit of R _L and J ₃ )} (However, most of this flows to the ground via R ₃ and R _L , Step 3 (equal to the flow of the solid arrow inside) and {R ₁ and J ₁
(parallel circuit of R ₂ and J ₂ )}, and the component that flows to the ground via R ₁ , J ₁ , and R ₂ .

Similarly, I _c is divided into a component shown by the dotted line that flows to the ground via {J ₁ , R ₁ , R ₃ , and R _L }, and a component shown by the dotted line that flows to the ground via {R ₂ }. Can be divided.

Therefore, the I _g component flowing to J ₁ is R ₃ +R _L /R ₁ +R ₂ +R ₃ +R _L ·I _g , which flows from T ₁ to T ₂ direction.

On the other hand, the I _c component flowing to J ₁ is R ₂ /R ₁ +R ₂ +R ₃
+ _RL・_Ic , which flows from _T2 to _T1 direction.

Therefore, if the following relationship is obtained: (R ₃ +R _L )/R ₁ +R ₂ +R ₃ +R _L・I _g −R ₂ /R ₁ +R ₂ +R ₃ +R _L・I _c >I ₁ ………(5) J ₁ switches to high resistance state.

(Step 4) If _J1 is switched to a high resistance state (approximately sub-gap resistance), high resistance will be created between the _Ig and _Ic input terminals, so _Ig and _Ic will be separated. That is, as shown in step 4 of FIG. 5, I _g flows to ground via R ₃ and R _L and I _c flows to ground via R ₂ . The control input of the gate is I _c , and the output current is the one that flows out to R _L when I _g is switched, so separating I _g and I _c means that the input and output can be separated. It is something to do.

Note that in equation (5), if R ₁ , R ₂ , R ₃ <<R _L , equation (5) is approximately equal to I _g >I ₁ (6).

The threshold value shown in FIG. 1b is expressed by equation (6).

The operation has been clarified above, and the threshold characteristics shown in FIG. 1b can be summarized as follows. That is, in the figure, region A is the region where the logic gate according to the present invention operates with sufficient input/output separation, and region B is
indicates the area where input/output separation is insufficient.

Note that the threshold values in FIG. 1b are I ₁ = I ₂ = I ₃ , R ₁ = R ₃
In this case, the sensitivity is 2, but if R ₁ is increased, the sensitivity can be further improved.

However, depending on the conditions of the manufacturing process, general superconducting circuits may have problems such as not being able to sufficiently reduce the resistance after the voltage transition of the Josephson junction, or manufacturing deviations due to contact resistance. It's possible.

When such a problem occurs in this conventional gate, the positive source operation region becomes narrow as shown in the example below. That is, in the case of step 2 in the switching sequence, Josephson junction J ₂
Even if transition occurs, a large leakage current flows through the Josephson junction J ₂ to the ground, so that the shunt of the signals I _g and I _c to the Josephson junction J ₃ is reduced.
Therefore, the signals I _g and I _c must be large in order to transfer Josephson junction J ₃ . This corresponds to the straight line indicating the threshold moving toward the upper right in the figure, and as a result, the operating region becomes narrower. Signal I _g ,
Increasing the shunt of I _c to Josephson junction J ₃ can be achieved by making resistances R ₁ and R ₃ sufficiently small, but in this case, the deviation in resistance value due to contact resistance becomes large. Larger other deviations in resistors R ₁ and R ₃ will lead to direct variations in the threshold line. As described in Japanese Patent Application No. 55-78082, the straight line indicating this threshold value is an important threshold value that determines the sensitivity of the gate, and its fluctuation is a major drawback.

Further, in the conventional example shown in FIG. 1a, in order to extract a large output current, it is necessary to reduce the load resistance. Generally, when the load resistance is reduced, in step 3 of the switch sequence, a current flows through the load resistance after the Josephson junctions J ₂ and J ₃ transition, so that the shunt to the Josephson junction J ₁ is reduced. As a result, the Josephson junction J ₁ becomes difficult to transition, and the threshold value shown by the straight line in FIG. 1b shifts to a region where the signal i _g is large, resulting in a disadvantage that the operating region becomes narrower.

In order to eliminate these drawbacks, the present invention
To provide a superconducting logic gate capable of stable and high-speed operation over a wide range by adopting a structure in which a bypass resistor and an inductance for blocking transient current are added to the circuit of 55-78082. With the goal.

An embodiment of the first invention of the present application will be described below with reference to the drawings. In Figure 2, R ₄ is a bypass resistor whose value is sufficiently small compared to resistors R ₁ , R ₂ , R _{3 ,} etc. The smaller the value of resistor R ₄ is compared to R ₁ , R ₂ , R _3, etc. good. Further, as in the conventional example, the resistance R ₂ needs to be smaller than the value of the load resistance R _L . However, the resistors R ₁ and R ₃ may have arbitrary values. This embodiment has the same structure as the previous structure in FIG. 1a, except that a bypass resistor is inserted between terminals P ₁ and T ₀ .

The switching operation in this embodiment is the first
The structure is almost the same as that in Figure a. That is,
As shown in FIG. 6, when the signals I _g and I _c are simultaneously applied from the input terminals T ₁ and T ₂ , the gate is switched and an output signal is obtained at the output terminal T ₀ . The switching sequence is as follows.

(Step 1) First, the signal of the shunt of the signal I _g by the resistors R ₁ and R ₃ ,
The signal I _c causes the Josephson junction J ₂ to transition to a voltage. Note that the threshold for this is the voltage difference between terminals P ₁ and T ₀ unless the Josephson junction J ₂ undergoes a voltage transition.
As is clear from the fact that no potential difference occurs between them and no current flows through _R4 , this is exactly the same as the example shown in FIG. The conditions for I _g and I _c for this purpose are the same as in equation (1).

In other words, the condition for the transition of J ₂ is R ₃ /R ₁ +R ₃ I _g +I _c >I ₂ (1)' Also, in this state, the conditions for J ₁ and J ₃ to not undergo voltage transition are as described in (2) above. The same conditions as in equation (3) are required. That is, R ₃ /R ₁ +R ₃ I _g <I ₁ ......(2)', R ₁ /R ₁ +R ₃ I _g <I ₃ ......(3)' (Step 2) Josephson junction J ₂ When the voltage transition occurs, a part of the signal I _c becomes a resistance because it has a large resistance value.
R ₁ , R ₃ and the bypass resistor R ₄ to the Josephson junction J ₃ and the signal I _g flows through the Josephson junction J ₃
The amount of water diverted to the area will also increase. (B ₁ in step 2 is
The I _c component flowing through R ₄ is shown. ) As a result, Josephson junction J ₃ transfers to voltage. In addition, the terminal
The input signal I _c to T ₂ passes not only through resistors R ₁ and R ₃ but also through resistor R ₄ to Josephson junction J ₃ and to resistor
As is clear, the signal I _g that has flowed to point P ₁ through R ₁ also flows into Josephson junction J 3 through resistor R ₄ (during step 2, the I _g component passes through R ₄ and flows into Josephson junction J ₃ ).
In this circuit, after _{the Josephson junction J 2 transfers} , the signal shunted to the Josephson junction J ₃ increases by the amount flowing through _the resistor R ₄ , so the input signal I _g with a small value , I _c , the Josephson junction J ₃ transitions to the voltage state. The conditions for the input signals I _g and I _c for this are resistance
The Δ connection formed by R ₁ , R ₄ , and R ₃ may be transformed into a Y connection to calculate the shunt to J ₃ . In this case, as explained in the case where there is no bypass resistor, the combined resistance value of the parallel circuit P is R ₂ ', which means that R ₂ and Josephson junction J ₂ are the parallel resistance value of the high resistance value after voltage transition. Become. To summarize the calculation results, R ₁ (R ₄ +R ₂ ′)+R ₂ ′(R ₃ +R ₄ )/(R ₂ +R ₄ )(R ₁ +R ₃ )+R ₂ ′R ₄ I _g +R ₂ ′(R ₁ +R ₃ +R ₄ )/R ₂ ′(R ₁ +R ₃ +R ₄ )+R ₄ (R ₁ +R ₃ )I _c >I ₃ ………(4)′ This means that the threshold straight line in Figure 1b is bypassed. Compared to the case without the resistor R ₄ , since it corresponds to downward movement, it has the great advantage of having a wider operating range.

(Step 3) As a result of Step 2 above, the Josephson junction _J3 transitions to a voltage state and becomes high resistance, so the output terminal
The parallel combined value with the external load resistance R _L connected to T ₀ is approximately equal to R _L . This parallel composite value is R _L ′
Then, the conditions for J ₁ to finally transition to the voltage state are as follows.

R ₄ (R ₃ +R _L ′)+R _L ′(R ₁ +R ₃ )/(R ₂ ′+R _L ′)(R ₁ +R ₃ +R ₄ )+R ₄ (R ₁ +R ₃ )I
_g −R ₂ ′(R ₁ +R ₃ +R ₄ )/(R ₁ +R ₃ +R ₄ )(R ₂ ′+R _L ′)+R ₄ (R ₁ +R ₃ )I _c >I ₁ ………(
5)' In this case as well, it is possible to flow part of the shunt of the input signal I _g to point T ₁ to point P ₁ via resistor R ₄ (B ₃ in step 3 in Figure 6). ), the threshold for transition of Josephson junction J ₃ shifts to a region where the input signal I _g is smaller than in the case without bypass resistor R ₄ .

(Step 4) Through the above sequence, the gate of the present invention completes the switch and can supply current to the load R _L via the terminal T ₀ .

By the way, in the present invention, even if problems such as a decrease in contact resistance or the resistance value of the bond after transfer occur due to process conditions, large value resistances R ₁ and R ₃ are used that are relatively easy to achieve accuracy. , by reducing only the resistance R ₄ , it is possible to increase the shunt to the Josephson junction J ₃ after the Josephson junction J ₂ transition. Therefore, the straight line representing the threshold value can be kept within a small region of the signals I _{g and} I _c without affecting the straight line representing the main threshold value shown in FIG. 1b, that is, a wide operating range can be secured.

Note that there is a possibility that the straight line indicating the threshold value in Figure 1b may vary slightly due to manufacturing deviation of the resistor _R4 , but this is because the straight line indicating the main threshold value that gives sensitivity will vary in the absence of a bypass resistor. Compared to the points mentioned above, there is no problem at all in practice.

Note that the operating speed of this type of logic gate increases as the values of the signals I _g and I _c , which are the operating points thereof, deviate from the threshold values. Conversely, when operating at the same operating point, the wider the operating range, the faster the operating speed. In this sense, the embodiments of the present invention also have the advantage of being able to operate at higher speeds than when there is no bypass resistor.

FIG. 3 shows an embodiment of the second invention of the present application.
This embodiment has the same circuit configuration as in FIG. 2 except that an inductance L ₁ is inserted in series with a resistor R ₂ .

By the way, normally, when a Josephson junction undergoes a voltage transition, a transient signal with a sharp rise and large amplitude flows. The aim of this embodiment is to utilize the fact that the inductance appears to have a large resistance value when viewed from this transient signal to improve the characteristics by controlling the direction of the shunted current. Therefore, the inductance
The value of L ₁ is the transition time (number of
If the frequency determined by the reciprocal of PS) is f ₀ , then 2πf ₀ L ₁
It suffices to make it approximately the same as the resistance _R2 . The operating principle of this circuit is almost the same as that shown in Figure 2, but in the absence of inductance L ₁ , the transient signal generated when Josephson junction J ₂ transitions to voltage is passed through resistor R ₂ with a small resistance value. It has not been used effectively due to restrictions on However, with such a configuration, it appears that the resistance R ₂ is not connected to the Josephson junction J ₂ transiently. Therefore, for both the signals I _g and I _c , most of the current flows in the Josephson junction J ₃ direction, and the Josephson junction J ₃ operates under the low level signals I _g and I _c as a result. It turns out.
This corresponds to moving the straight line representing the threshold value in FIG. 1b to a region where the signals I _g and I _c are small. Therefore, the operating range can be further expanded.

Incidentally, for the same reason as explained in the embodiment of FIG. 2, the embodiment of FIG. 3, which can have a wide operating range, also has an advantage in terms of high-speed operation.

FIG. 4 shows another embodiment of the first invention of the present application shown in FIG. In this example, the inductance
Except that L ₂ is inserted in series with the load resistor R ₁ .
It has the same circuit configuration as FIG. 2. The effect of the inductance L ₂ in this case is similar to that of the inductance shown in FIG. That is, the operation of the embodiment of FIG. 4 follows approximately the same sequence as that of FIG. 2, but in this structure, most of the transient signal when the Josephson junction J ₃ undergoes a voltage transition flows to the Josephson junction J _1. . Therefore, the bias signal level at which the Josephson junction J ₁ transitions to the voltage state may be low. That is, by inserting the inductance L ₂ , the straight line indicating the threshold value falls into the region where the signal I _g is small, and there is an advantage that the normal operation region can be widened. Note that in this structure, the rise of the output current is slightly blunted, but the magnitude of the output current that can be finally extracted after the transient response is the same value as when there is no inductance _L2 .

As described above, according to the present invention, in a superconducting logic gate of the type that directly injects current into a junction, which is small and capable of low-power, high-speed operation, it operates in a wide operating range, allowing a large margin. This provides the great advantage of being able to perform high-speed operations.

[Brief explanation of the drawing]

FIGS. 1a and 1b are diagrams showing the previously proposed superconducting logic gate and its operating threshold curve. FIG. 2 is a wiring diagram showing an embodiment of the first invention of the present application in which performance is improved by a bypass resistor _R4 . Third
The figure is a line diagram showing an embodiment of the second invention of the present application, which uses inductance to improve performance. FIG. 4 is a line diagram showing another embodiment of the first invention of the present application in which performance is improved by using inductance. FIG. 5 is an explanatory diagram of the operation sequence of the previously proposed superconducting logic gate shown in FIG. 1a. FIG. 6 is an explanatory diagram of the operation sequence of the superconducting logic gate of the present invention shown in FIG. 2. R ₁ , R ₂ , R ₃ , R ₄ ...Resistance, R _L ...Load resistance,
T ₁ , T ₂ ... Input terminal, T ₀ ... Output terminal, J ₁ ,
J ₂ , J ₃ ... Josephson junction, L ... inductance.

Claims (1)

[Claims] 1. A first input terminal T1 and a second input terminal T2.
, an output terminal T0, a ground terminal G, a first Josephson junction J1 and a first resistor R1 provided between the first and second input terminals, and the first input terminal T1 a series circuit S1 in which a first resistor R1 is connected to the second input terminal T;
A parallel circuit P consisting of a second Josephson junction J2 and a second resistor R2 is provided between the first input terminal T1 and the output terminal T0, and a third parallel circuit P is provided between the first input terminal T1 and the output terminal T0. and a resistance R3 of
A third Josephson junction J3 is provided between the output terminal T0 and the ground terminal G, and a connection point P1 between the first resistor R1 and the first Josephson junction J1 is provided between the output terminal T0. A superconducting logic gate comprising a fourth resistor R4. 2 First input terminal T1 and second input terminal T2
, an output terminal T0, a ground terminal G, a first Josephson junction J1 and a first resistor R1 provided between the first and second input terminals, and the first input terminal T1 a series circuit S1 in which a first resistor R1 is connected to the second input terminal T;
2 and the ground terminal G, the parallel circuit P consists of a second Josephson junction J2 and a series circuit S2 of an inductance L1 and a second resistor R2.
and the first input terminal T1 and the output terminal T.
0, the third Josephson junction J3 provided between the output terminal T0 and the ground terminal G, and the connection point P1 between the first resistor R1 and the first Josephson junction J1. and output terminal T0
and a fourth resistor R4 provided between the superconducting logic gate and the fourth resistor R4. 3. Claim 1, characterized in that the output terminal T0 is connected to a load resistor R _L or a series circuit S3 of the load resistor R _L and an inductance L2.
Superconducting logic gate as described in Section. 4. Claim 2, characterized in that a load resistor R _L or a series circuit S3 of the load resistor R _L and an inductance L2 is connected to the output terminal T0.
Superconducting logic gate as described in Section.