JPH0226418B2 - - Google Patents
Info
- Publication number
- JPH0226418B2 JPH0226418B2 JP60217934A JP21793485A JPH0226418B2 JP H0226418 B2 JPH0226418 B2 JP H0226418B2 JP 60217934 A JP60217934 A JP 60217934A JP 21793485 A JP21793485 A JP 21793485A JP H0226418 B2 JPH0226418 B2 JP H0226418B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- josephson
- josephson junction
- resistance
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010586 diagram Methods 0.000 description 13
- 230000010354 integration Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 230000005668 Josephson effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Logic Circuits (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明はジヨセフソン効果を用いた論理ゲート
回路に係り、具体的には積の論理を行う電流注入
形の論理ゲート回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a logic gate circuit using Josephson effect, and specifically relates to a current injection type logic gate circuit that performs product logic.
ジヨセフソン素子を用いて積の論理を行う論理
ゲート回路には、複数のジヨセフソン接合とその
接合を超電導ループで接続した量子干渉回路と、
接合間を抵抗で接続した抵抗結合形回路がある。
A logic gate circuit that performs product logic using Josephson elements includes a quantum interference circuit that connects multiple Josephson junctions and the junctions with a superconducting loop,
There is a resistance-coupled circuit that connects the junctions with a resistor.
第１図に量子干渉回路の回路図とそのしきい値
特性を示す。この回路は例えばアプライド・フイ
ジツクス・レター誌（Applied Physics
Letters.）Vol.33、No.８第781〜783頁に記載され
ているが、超電導ループを含むため、その面積が
大きく集積化には不向きである。また磁束がトラ
ツプしやすく、しきい値変動による回路の誤動作
が起りやすい欠点がある。 FIG. 1 shows a circuit diagram of a quantum interference circuit and its threshold characteristics. For example, this circuit was published in Applied Physics Letters magazine.
Letters.) Vol. 33, No. 8, pages 781-783, but since it includes a superconducting loop, its area is large and unsuitable for integration. Another disadvantage is that magnetic flux is easily trapped, and circuit malfunctions are likely to occur due to threshold fluctuations.
第２図に抵抗結合形AND回路の回路図とその
しきい値特性を示す。この回路は例えば特開昭58
−43630号公報に記載されているが、その面積が
小さくでき集積化に適し、かつ磁束トラツプによ
る回路の誤動作が少ない利点を有している。しか
しながら、OR−AND構成のAND回路における
スイツチング時間を評価した結果、量子干渉の回
路より遅いという欠点があつた。 Figure 2 shows a circuit diagram of a resistance-coupled AND circuit and its threshold characteristics. This circuit is, for example, published in Japanese Unexamined Patent Publication No.
This is described in Japanese Patent No. 43630, but it has the advantage of being small in area, suitable for integration, and less prone to circuit malfunctions due to magnetic flux traps. However, as a result of evaluating the switching time of an AND circuit with an OR-AND configuration, it was found that the switching time was slower than that of a quantum interference circuit.
本発明の目的は従来の積の論理を行う抵抗結合
形回路の欠点を改善し、スイツチング時間を高速
化し、集積化に適した論理ゲート回路を提供する
ことにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a logic gate circuit which improves the drawbacks of conventional resistance-coupled circuits that perform product logic, speeds up switching time, and is suitable for integration.
本発明は、第１および第２の入力線と、出力線
に接続され、一方が接地された第３のジヨセフソ
ン接合の他方とを抵抗を介して接続し、入力側の
第１および第２のジヨセフソン接合が電圧状態に
スイツチングする前に入力電流の一部を出力側の
第３のジヨセフソン接合に注入（バイアス）して
おくことにより、そのスイツチング時間を高速化
するものである。
The present invention connects the first and second input lines and the other of the third Josephson junction connected to the output line and one of which is grounded via a resistor, and connects the first and second input lines on the input side By injecting (biasing) a portion of the input current into the third Josephson junction on the output side before the Josephson junction switches to the voltage state, the switching time is speeded up.
以下、本発明の実施例を図面により説明する。
第３図に本発明の一実施例を示す。第３図におい
て、３１，３２，３３はそれぞれI01、I02、I03の
ジヨセフソン臨界電流を有するジヨセフソン接合
であり、４１，４２，４３，４４，４５，４６，
４７はそれぞれ抵抗値r1，r2，r3，r4，r5，r6，r7
の抵抗である。さらに、５１，５２はそれぞれ第
１、第２の入力線、５３は出力線である。ジヨセ
フソン接合３１，３２，３３はそれぞれ抵抗４
３，４４，４５によつてデルタ結線されている。
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 3 shows an embodiment of the present invention. In FIG. 3, 31, 32, 33 are Josephson junctions having Josephson critical currents of I 01 , I 02 , I 03 , respectively; 41, 42, 43, 44, 45, 46,
47 are resistance values r 1 , r 2 , r 3 , r 4 , r 5 , r 6 , r 7 respectively
resistance. Furthermore, 51 and 52 are first and second input lines, respectively, and 53 is an output line. Josephson junctions 31, 32, and 33 each have a resistance of 4
3, 44, and 45 are connected in delta.
本回路のしきい値特性は以下のようにして求め
られる。 The threshold characteristics of this circuit are determined as follows.
第１の入力線５１にIaなる入力電流が流入した
時第１のジヨセフソン接合３１が電圧状態にスイ
ツチする条件は
Ia・r6／r1＋r6＞I01 ……(1)
となる。第１のジヨセフソン接合３１が電圧状態
にスイツチした後、第２の入力線５２にIbなる入
力電流が流入し、第２のジヨセフソン接合３２が
電圧状態にスイツチする条件は、
Ia・r6／r1＋r6・r4／r3＋r4＋Ib・r7／r2＋r7＞I02
……(2)
となる。 The condition for the first Josephson junction 31 to switch to a voltage state when an input current I a flows into the first input line 51 is I a · r 6 / r 1 + r 6 > I 01 ...(1) . After the first Josephson junction 31 switches to the voltage state, an input current I b flows into the second input line 52, and the conditions for the second Josephson junction 32 to switch to the voltage state are I a · r 6 /r 1 +r 6・r 4 /r 3 +r 4 +I b・r 7 /r 2 +r 7 >I 02
...(2) becomes.
第１および第２のジヨセフソン接合３１および
３２が電圧状態にスイツチした後、第３のジヨセ
フソン接合が電圧状態にスイツチする条件は
Ia＋Ib＞I03 ……(3)
となる。 After the first and second Josephson junctions 31 and 32 switch to the voltage state, the condition for the third Josephson junction to switch to the voltage state is I a +I b >I 03 (3).
さらに、第１のジヨセフソン接合３１が電圧状
態にスイツチし、第２のジヨセフソン接合３２が
零電圧状態にある時、第３のジヨセフソン接合３
３が電圧状態にスイツチしない条件は
Ia・r1／r1＋r6＋Ia・r6／r1＋r6・r3／r3＋
r4＋Ib・r2／r2＋r7＜I03……(4)
ここで、第１、第２および第３のジヨセフソン
接合の臨界電流I01，I02およびI03と、各抵抗、r1，
r2，r3，r4，r5，r6およびr7の間の関係を次のよう
に設定すると、
I01＝I02＝１／ｍI03＝I0 ……(5)
r1＝r2＝１／n1r6＝１／n1r7 ……(6)
r4＝r5＝１／n2r3 ……(7)
(1)、(2)、(3)および(4)式は(5)、(6)、(7)式より次
の
ように表わされる。 Furthermore, when the first Josephson junction 31 switches to a voltage state and the second Josephson junction 32 is in a zero voltage state, the third Josephson junction 3
The condition that 3 does not switch to the voltage state is I a・r 1 /r 1 +r 6 +I a・r 6 /r 1 +r 6・r 3 /r 3 +
r 4 +I b・r 2 /r 2 +r 7 <I 03 ...(4) Here, the critical currents I 01 , I 02 and I 03 of the first, second and third Josephson junctions, each resistance, r1 ,
Setting the relationship between r 2 , r 3 , r 4 , r 5 , r 6 and r 7 as follows, I 01 = I 02 = 1/mI 03 = I 0 ...(5) r 1 = r 2 = 1/n 1 r 6 = 1/n 1 r 7 ……(6) r 4 = r 5 = 1/n 2 r 3 ……(7) (1), (2), (3) and Equation (4) can be expressed as follows from equations (5), (6), and (7).
(1)式は
Ia・n1／１＋n1＞I0 ……(8)
(2)式は
Ia・n1／１＋n1・１／１＋n2＋Ib・n1／１＋n1＞I0(9
)
(3)式は
Ia＋Ib＞mI0 (10)
(4)式は
Ia｛１＋n2＋n1n2／（１＋n1）（１＋n2）｝＋Ib・１／
１＋n1＜mI0(11)
入力信号Ia，Ibの流入過程を逆にしても回路的
に対称であるため上述と同じ式が得られる。第４
図に(8)〜(11)式の直線から得られる本発明のしきい
値特性の模式図を示す。直線１，２は(8)式から求
まる直線であり、直線３，４は(9)式から求まる直
線である。また、直線５は(10)式、直線７，８は(11)
式から求まる直線である。本回路しきい値特性は
(8)〜(11)式からも判るように、直線１，２，３，
４，５よりも大きく、直線６，７より小さな電流
範囲、すなわち、第４図の太線となる。 Equation (1) is I a・n 1 /1+n 1 >I 0 ...(8) Equation (2) is I a・n 1 /1+n 1・1/1+n 2 +I b・n 1 /1+n 1 >I 0 (9
) Equation (3) is I a + I b > mI 0 (10) Equation (4) is I a {1+n 2 +n 1 n 2 /(1+n 1 )(1+n 2 )}+I b・1/
1+n 1 <mI 0 (11) Even if the inflow process of the input signals I a and I b is reversed, the same equation as above can be obtained because the circuit is symmetrical. Fourth
The figure shows a schematic diagram of the threshold characteristics of the present invention obtained from the straight lines of equations (8) to (11). Straight lines 1 and 2 are straight lines found from equation (8), and straight lines 3 and 4 are straight lines found from equation (9). Also, straight line 5 is expressed by (10), and lines 7 and 8 are expressed by (11).
This is a straight line found from the formula. This circuit threshold characteristic is
As can be seen from equations (8) to (11), the lines 1, 2, 3,
4 and 5 and smaller than straight lines 6 and 7, that is, the thick line in FIG.
第５図にジヨセフソン臨界電流I01，I02を
50μA、I03を150μA（ｍ＝３）、抵抗値n1，n2を２
とした場合のしきい値特性の具体例を示した。斜
線内が零電圧状態であり、正方形内がAND回路
として動作する領域である。この動作領域は従来
の抵抗結合形回路と同程度の広さを有している。 Figure 5 shows Josephson critical currents I 01 and I 02 .
50μA, I 03 is 150μA (m = 3), resistance value n 1 , n 2 is 2
A specific example of the threshold characteristics when The area inside the diagonal line is the zero voltage state, and the area inside the square is the area that operates as an AND circuit. This operating region has a width comparable to that of a conventional resistance-coupled circuit.
つぎに本発明の他の実施例を第６図で説明す
る。第３図に示した回路の変形であり、６１，６
２，６３はジヨセフソン接合であり、７１，７
２，７３，７４，７５，７６，７７はそれぞれ
r1，r2，r3，r4，r5，r6，r7の抵抗値を有する抵抗
であり、８１，８２は第１、第２の入力線、８３
は出力線である。ジヨセフソン接合６１，６２，
６３はそれぞれ抵抗７３，７４，７５によつてス
ター結線されている。本発明のしきい値特性も第
３図で示した回路と同様となる。 Next, another embodiment of the present invention will be explained with reference to FIG. This is a modification of the circuit shown in Figure 3, with 61,6
2,63 is a Josephson junction, 71,7
2, 73, 74, 75, 76, 77 are respectively
These are resistors having resistance values of r 1 , r 2 , r 3 , r 4 , r 5 , r 6 , and r 7 , 81 and 82 are the first and second input lines, and 83
is the output line. Josephson junction 61, 62,
63 are star-connected by resistors 73, 74, and 75, respectively. The threshold characteristic of the present invention is also similar to that of the circuit shown in FIG.
第７図に本発明の回路を用いたOR−AND構成
のAND回路におけるスイツチング時間の一例を
示す。この値はOR回路自体のスイツチング時間
を差し引いたAND回路のみの値を示した。参考
までに従来の量子干渉回路、抵抗結合形回路のス
イツチング時間も図示した。曲線１が量子干渉回
路、曲線２が従来の抵抗結合形回路、曲線３が本
発明の抵抗結合形回路のスイツチング時間の一例
である。図示したように、本発明の回路のスイツ
チング時間は従来の抵抗結合形回路により速く、
量子干渉回路と同程度である。 FIG. 7 shows an example of switching time in an AND circuit having an OR-AND configuration using the circuit of the present invention. This value shows only the value of the AND circuit after subtracting the switching time of the OR circuit itself. For reference, the switching times of conventional quantum interference circuits and resistance-coupled circuits are also illustrated. Curve 1 is an example of the switching time of the quantum interference circuit, curve 2 is the conventional resistance-coupled circuit, and curve 3 is the switching time of the resistance-coupled circuit of the present invention. As shown, the switching time of the circuit of the present invention is faster than that of conventional resistive coupled circuits.
It is on the same level as a quantum interference circuit.
本発明によれば、従来の抵抗結合形回路と同程
度の動作領域（しきい値特性）を有し、そのスイ
ツチング時間が従来のそれより速く、集積化に適
した電流注入形論理（AND）ゲート回路を提供
することができるという効果がある。
According to the present invention, the current injection logic (AND) has the same operating range (threshold characteristics) as the conventional resistance-coupled circuit, has a faster switching time than the conventional one, and is suitable for integration. This has the advantage that a gate circuit can be provided.
第１図は従来の量子干渉回路の回路図としきい
値特性を示す図、第２図は従来の抵抗結合形回路
の回路図としきい値特性を示す図、第３図は本発
明の抵抗結合形回路の実施例を示す回路図、第４
図は第３図の抵抗結合形回路のしきい値特性を示
す模式図、第５図はしきい値特性の具体例を示す
図、第６図は本発明の他の実施例を示す回路図、
第７図は量子干渉回路、従来の抵抗結合形回路、
および本発明の抵抗結合形回路のスイツチング時
間比較図である。
４６，４７，７６，７７……入力電流の一部を
事前に出力側のジヨセフソン接合に流入するため
の抵抗。
Figure 1 is a diagram showing the circuit diagram and threshold characteristics of a conventional quantum interference circuit, Figure 2 is a diagram showing the circuit diagram and threshold characteristics of a conventional resistive coupling type circuit, and Figure 3 is a diagram showing the resistive coupling type circuit of the present invention. Circuit diagram showing an embodiment of the shaped circuit, No. 4
The figure is a schematic diagram showing the threshold characteristics of the resistor-coupled circuit shown in FIG. 3, FIG. 5 is a diagram showing a specific example of the threshold characteristics, and FIG. 6 is a circuit diagram showing another embodiment of the present invention. ,
Figure 7 shows a quantum interference circuit, a conventional resistance-coupled circuit,
FIG. 3 is a comparison diagram of switching times of the resistance-coupled circuit of the present invention. 46, 47, 76, 77...Resistors for allowing a portion of the input current to flow into the Josephson junction on the output side in advance.
Claims (1)
セフソン接合と、該第１、第２及び第３のジヨセ
フソン接合の他方間をそれぞれ接続した複数の抵
抗と、該第１のジヨセフソン接合の他方に接続さ
れた第１の入力線と、該第２のジヨセフソン接合
の他方に接続された第２の入力線と、該第３のジ
ヨセフソン接合の他方に接続された出力線とから
なるジヨセフソン論理ゲート回路において、前記
第１の入力線と前記第１のジヨセフソン接合の他
方との間、前記第２の入力線と前記第２のジヨセ
フソン接合の他方との間にそれぞれ抵抗を設け、
前記第１及び第２の入力線と前記第３のジヨセフ
ソン接合の他方との間をそれぞれ抵抗を介して接
続したことを特徴とするジヨセフソン論理ゲート
回路。 ２ 特許請求の範囲第１項において、上記第１、
第２及び第３のジヨセフソン接合の他方間が３つ
の抵抗のデルタ結線で接続されたことを特徴とす
るジヨセフソン論理ゲート回路。 ３ 特許請求の範囲第１項において、上記第１、
第２及び第３のジヨセフソン接合の他方間が３つ
の抵抗のスター結線で接続されたことを特徴とす
るジヨセフソン論理ゲート回路。[Scope of Claims] 1: first, second and third Josephson junctions, one of which is grounded; a plurality of resistors each connected between the other of the first, second and third Josephson junctions; a first input line connected to the other side of the first Josephson junction; a second input line connected to the other side of the second Josephson junction; and an output connected to the other side of the third Josephson junction. and a resistor between the first input line and the other of the first Josephson junction, and between the second input line and the other of the second Josephson junction, respectively. established,
A Josephson logic gate circuit, characterized in that the first and second input lines and the other of the third Josephson junction are connected via resistors, respectively. 2 In claim 1, the above first,
A Josephson logic gate circuit, characterized in that the other of the second and third Josephson junctions is connected by a delta connection of three resistors. 3 In claim 1, the above first,
A Josephson logic gate circuit characterized in that the other of the second and third Josephson junctions is connected by a star connection of three resistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60217934A JPS6278916A (en) | 1985-10-02 | 1985-10-02 | Jhosephson logical gate circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60217934A JPS6278916A (en) | 1985-10-02 | 1985-10-02 | Jhosephson logical gate circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6278916A JPS6278916A (en) | 1987-04-11 |
| JPH0226418B2 true JPH0226418B2 (en) | 1990-06-11 |
Family
ID=16711998
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60217934A Granted JPS6278916A (en) | 1985-10-02 | 1985-10-02 | Jhosephson logical gate circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6278916A (en) |
-
1985
- 1985-10-02 JP JP60217934A patent/JPS6278916A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6278916A (en) | 1987-04-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5455519A (en) | Josephson logic circuit | |
| CA1198484A (en) | Circuit utilizing josephson effect | |
| JPH0226418B2 (en) | ||
| JPS5840945U (en) | 3 Josephson junction direct connection type separation circuit | |
| CA1189916A (en) | Circuit utilizing josephson effect | |
| JP2783032B2 (en) | Josephson reverse current prevention circuit | |
| JPH0342019B2 (en) | ||
| JP2674652B2 (en) | Josephson logic cell gate | |
| JPH0425640B2 (en) | ||
| JPH023326B2 (en) | ||
| JPH047132B2 (en) | ||
| JPH0425639B2 (en) | ||
| JPH0234493B2 (en) | ||
| JPH0417566B2 (en) | ||
| JPS6141173B2 (en) | ||
| JPS64850B2 (en) | ||
| JPS60260225A (en) | Josephson or circuit | |
| JPH047131B2 (en) | ||
| JPH0378008B2 (en) | ||
| JPH0114730B2 (en) | ||
| JPS6367773B2 (en) | ||
| JPS60239123A (en) | Superconduction inverter circuit | |
| JPH0544203B2 (en) | ||
| JPH0257378B2 (en) | ||
| JPS6158319A (en) | Superconductive logical gate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |