JPS5843630A - Current injection type logical gate circuit using josephson effect - Google Patents

Current injection type logical gate circuit using josephson effect

Info

Publication number
JPS5843630A
JPS5843630A JP56142748A JP14274881A JPS5843630A JP S5843630 A JPS5843630 A JP S5843630A JP 56142748 A JP56142748 A JP 56142748A JP 14274881 A JP14274881 A JP 14274881A JP S5843630 A JPS5843630 A JP S5843630A
Authority
JP
Japan
Prior art keywords
current
gate circuit
input
resistance
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56142748A
Other languages
Japanese (ja)
Other versions
JPH0234492B2 (en
Inventor
Junichi Sone
曽根 純一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56142748A priority Critical patent/JPS5843630A/en
Priority to EP82108223A priority patent/EP0074604B1/en
Priority to DE8282108223T priority patent/DE3268138D1/en
Priority to US06/415,877 priority patent/US4538077A/en
Priority to CA000411147A priority patent/CA1189916A/en
Priority to AU88311/82A priority patent/AU553981B2/en
Publication of JPS5843630A publication Critical patent/JPS5843630A/en
Publication of JPH0234492B2 publication Critical patent/JPH0234492B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/195Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices
    • H03K19/1954Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices with injection of the control current
    • H03K19/1956Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices with injection of the control current using an inductorless circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To operate a logical gate circuit of the product at a high spped, by supplying a current to 2 Josephson junctions and 3 resistances, respectively, from 2 input lines, and fetching an output from the Josephson junction connected to a connecting point of the resistance. CONSTITUTION:To a Josephson JS junction 30 whose one terminal has been grounded 40, an input line 38 for injecting an input current Ia, and resistances 33, 34 are connected, and to the other terminal of the resistance 33, a JS junction 31 whose one terminal has been grounded, an output line 36 terminated by a load resistance 37, and a resistance 35 are connected. To the other terminals of the resistances 34, 35, a JS junction 32 whose one terminal has been grounded 40, and an input line 39 for injecting a current Ib are connected. The transition current values I01, I02 and I<03> of the JS junctions 30-32 are set to I01=I03=I02/2=I0, and the resistance values r1, r2 and r3 of the resistance 33-35 are set to r1=r3=r2/2. In a state that only one current in the currents Ia, Ib flows, the logical gate is not transferred to a voltage state unless a current exceeding 3Io flows. In case of exceeding a curent Ia=Ib=Io, the logical gate circuit is transferred to the voltage state, has a wide operation margin and high gain, and executes its operation at a high speed.

Description

【発明の詳細な説明】 本発明はジ冒セフンン効果を用いた論理ダート回路に調
し、より具体的には積の論理を行なう電流注入製の論理
ゲート1路KIlする0ジー竜フソシ効果を用−九論理
ゲート回路は例えげ文献アプライド フイーツタス レ
ター誌(ムppHed Pbysl*s L@tt@r
s、) Vol、 33. ?In 8゜pp、 78
1〜yss t−参照すればわかるように、蟲技書分野
では広く知゛られて−る・これら0論理ゲ一ト回路で鉱
、複数個Oジ嘗セフノン接合と、これbを電気的に納会
するインダクタンスからなるループ■賂で構成され九ジ
ー竜フソン干−履論理ゲート1路が、干渉履論理ゲート
ー路への1線の電流注入によりて、または干渉層論理ゲ
ート回路の制御鎗中の入力電流とamIa結倉によりて
スイッチされる。
DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to a logic circuit using the logic effect, and more specifically, the present invention is based on the logic dart circuit using the logic effect, and more specifically, the logic circuit uses the logic gate effect to perform the product logic. -Nine logic gate circuits are illustrated in the literature Applied Featus Letter Magazine (Mupphed Pbysl*s L@tt@r
s,) Vol, 33. ? In 8゜pp, 78
1~yss t- As you can see, it is widely known in the field of technical books that these 0 logic gate circuits can be used to connect multiple O di-Cefnon junctions and electrically A loop consisting of an inductance that is connected to a logic gate is constructed by a loop consisting of an inductance, which is connected to the interference layer by injecting a current into the logic gate circuit, or by injecting a current into the interference layer logic gate circuit. It is switched by the input current and amIa Yukura.

III園は電流注入によ)積の論理を行なう論■ゲート
回路O1l来例を説−する丸めの園で%伽)1&!閤賂
園、(ロ)*a皺論論理−ト回路の制御骨性であり、横
軸、縦軸はそれぞれ論理グー)1回路に注入される2本
のλ力電@ Ia 、 Ibを示す・(a)図において
t綽sll#iそれぞれジ謬セフツノ電流の臨界値がZ
el、I軸であるジーセフノン俵舎12.13はそれぞ
れインダクタンス値L1、I4を有するインダクタンス
、14.15はそれぞれ入力電流Ia、Ibが注入され
る入力電流路、16は出力−路、17は負荷抵抗。
Garden III is a theory that performs product logic by current injection.■Gate circuit O1l is a rounding garden that explains the following example)1&! (b) The control structure of the logic circuit, and the horizontal and vertical axes represent the two λ power supplies @ Ia and Ib injected into one logic circuit, respectively. - In figure (a), the critical value of the error current is Z
12.13 is an inductance having inductance values L1 and I4, respectively, 14.15 is an input current path into which input currents Ia and Ib are injected, 16 is an output path, and 17 is a load. resistance.

18は箒地である・ 上記インダクタンス値−L1.14sジ1七7ノン臨界
電流値lo1、Is舅O輿係は LII@l−LSI・雪           −−−
−−−−−(1)Its(Lt◆Lx )−do   
 −−−−−=−=  (2)を満足するように遥ぶ。
18 is a broomstick. The above inductance value - L1.14s di 177 non-critical current value lo1, Is father-in-law is LII@l-LSI Yuki ---
------(1) Its(Lt◆Lx)-do
−−−−−=−= Move so as to satisfy (2).

上式で一〇 #i磁束量子と呼ばれる自然定数で、10
7pH−mA @度OIlをtり。
In the above formula, 10 #i is a natural constant called magnetic flux quantum, which is 10
7pH-mA @Oil.

伽)図の制御特性Kか−では、図中、斜一部で示される
領域にλ力電流Ia、Ibがあるときは、ジ謬−に7ノ
ン接合10%11紘零電圧状態に@す〜従りて出力線路
16に祉出力電fIL轄流れてなく、皺論理ゲートi路
は論woe状態にある。図中、斜一部でな“領域は′“
″に7/PIi舎10・11が有限電圧状態に遷移し丸
状lIを示、二、従9て出力線路111に紘出力電流が
流れ、鋏−ゲート回路は論1110状11にある。
传) In the control characteristic K in the figure, when there are λ force currents Ia and Ib in the region shown by the diagonal part in the figure, it will be in the 7 non-junction 10% 11 zero voltage state. ~Therefore, no output current fIL flows to the output line 16, and the wrinkle logic gate i is in the logic state. In the figure, the “area” in the diagonal part is “”
At 7/PIi 10 and 11 transition to a finite voltage state and exhibit a round shape 11, a round output current flows through the output line 111, and the scissors-gate circuit is in a 1110 state 11.

積O論lKを行なう論理ゲート回路の制御特性としては
、入力電1111m、またはIleだけ流れている状態
で諌論理ダート闘踏が電圧状態に遷移するに必I!傘入
力電aI・%鵞たは!b a’llk比べ、等しい値O
入力電wth、xh−ともに@れている状態で、鋏論層
グー)lllIIが電圧状態に遷移するに必ll!な入
力電流Ia(−1%)OI[が小11−1−動作賃−ジ
yが大暑< 、*’)論111− ) 1111トl、
、”Ct)’81%大自(大暑適な制御4I性fあると
いえゐ0本論膳ダート■路にか−ては%2りOジ曹セフ
ノy績金16slleジII竜7ノノ臨界電流値O比I
@/I@lが1のと會KIa−IbO秋態で該論理ゲに
置針すれば、入力電流!a%xbがともに流れて−ゐ状
態は(転)−一で表わされ、験O論m管行竜うことがわ
かる・。
As for the control characteristics of the logic gate circuit that performs the product O logic lK, it is necessary for the logic dart to transition to the voltage state when only the input voltage 1111m or Ile is flowing. Umbrella input power aI/%Rokutaha! b a'llk, equal value O
When the input voltages wth and xh- are both in the state, it is necessary for the scissor theory layer (goo)llllII to transition to the voltage state! Input current Ia (-1%) OI
, "Ct) '81% large self (large heat suitable control 4I characteristics f 0 book discussion dirt ■ road is %2 Ojiso cefno y reward money 16slle diII dragon 7nono critical current Value O ratio I
If @/I@l is 1 and the needle is placed on the logic game in the autumn state of KIa-IbO, the input current! It can be seen that when a%xb flows together, the -i state is represented by (transition) -1, and the result is an experimental flow.

以上に遮ぺ&坤<、□本Iゲート■踏は動作マージνが
大暑い、あh−紘論理ゲートー路としてaSSが大暑(
、l!りて高速動作が可能と一5長所を19−IIX%
同時に以下のような欠点も有する。
Above all, interception & gon <, □ book I gate ■ step is operation merge ν is very hot, ah-Hiro logic gate - aSS is very hot (
,l! 15 advantages: 19-IIX% high-speed operation
At the same time, it also has the following drawbacks.

lりの欠点は前記(2)式e**aえめ、電流レベルI
軸と インダクタンス値L1% L会同時に小さくする
ことがで龜ず%l!うて1賂OIl造に大き′&ラグ函
積を要することである・を九倫の欠点は、皺論層ゲート
同賂がインダクタンス値よびジ曽セア。
The disadvantage of the above equation (2) is e**a, and the current level I
You can reduce the shaft and inductance value L1% at the same time without any problems! The drawback of the nine circuits is that it requires a large lag product to construct the OIl layer, and the inductance value and the diode value of the same layer gate are the same.

ソシ鎖合O1l量をと−に含む丸め、高速動作0た、め
減衰させなければならtkい共振を有するヒとである・
さらにζOようta路路銀超電導状態転移すると11、
浮遊の磁束をトラップ、、シやすく、このトラップされ
九徴東和よp誤動作を起こす閃履ヤ′あり九〇 本発−el釣は従来例O論理ゲート回路と同様の広い動
作マージン、高い利it維持しながら、前記欠点を除去
せしめたジ瞼セフノン効果を用いた電流注入製論理ゲー
ト回路をm雫す今ことにあるO 本発@によれば、一方が接地された第1のジ■竜7ノン
接会に、第1の入力−と5jlzおよび第2t)llk
抗〇−瑞と管−統し、一方−IIX接麺された第2のジ
ーセフノン接会には、出力−と、前記Illの抵抗04
h端および籐30紙杭の一端とを接続し、一方が接地さ
れ九gsのジーセ7ノyII金に&!。
It is a human with high resonance that must be attenuated because of the rounding and high-speed operation that includes the amount of chain linkage O1l.
Furthermore, when the ζO path is transferred to the silver superconducting state, 11,
It is easy to trap stray magnetic flux, and it is easy to trap and cause malfunction due to this trapping. According to the present invention, a logic gate circuit made by current injection using the di-cefnon effect, which eliminates the above-mentioned drawbacks while maintaining 7 non-contact, 1st input- and 5jlz and 2nd t)llk
Resistance 〇-Rui and pipe-control, while-IIX connected to the second g.
H end and one end of the rattan 30 paper pile are connected, one end is grounded and 9 gs gise 7 no y II gold &! .

msの入力−と、前記Im!訃1よび前記use紙抗O
働端とを接続し大仁とを41黴とするジ謬慟フソシ曽l
&をMいえ電流注入1論覇ダ一ト回路が得られる・ 以下1本発明を11w管用いてl!−する・第3園は本
斃−〇−実施例である・ジs * 7ソy効*tm−九
電流注入履論麿ダ−トー路管説−すJbえめO園でt(
ロ)−は−路間、伽)■°社その制御s像である@Jj
cシーてI6.11%32はそれぞれジ■−4!7ノシ
畠昇、電流値1oz、1−1I@Iを有するジ@ * 
7ノシ俵金%U%m4 s 3s紘それぞれ抵抗値r9
 rか1e@抗鴨・Uは抵抗値−1有する負荷m抗31
で終錫宴りる出力線、SS、S會はそれヤれ入力偏量H
a s Ikの流れ為入力−、鋳&!談論を表わす・本
輿論例にシーでは前記ジー47ノン臨界電流値、Iop
lts@*夏・Ikよび抵抗値rlq rかgは下記の
調像式を構えずようIC黴竜1れて−る・ Iol m I*3 m I@A置装s    −=”
・−−=−(3)rl  m r@−11/1!   
     −−−−−−−−−−(4)いt3本O入力
電@Ia%Ibのうち、一方だけち例えば入力電流1a
*けが諌−環ゲート回路に注入されたと弯t−想定する
01&t)値を―)式で定義されるIoよりも大きく遺
ぺば、ジ−セフノン接合sOは電圧状態に遷移し、注入
され九入力電流Iatt(4)式%式%(5) (6) の関係式が―たされれば、前記ジ−セフノン接合31.
32111零電E状WiKlbt)、出力1I36 K
 t!出力電流は流れない。
ms input - and said Im! Death 1 and said use paper anti-O
It is a mistake to connect the working side and make the 41st century.
&M no, current injection 1. A logical circuit can be obtained. ・The following 1. Using the present invention with an 11W tube! - The third school is an example of the present example.
B) - is - Rima, G) ■°sha is the control image @Jj
c sea and I6.11%32 respectively have a current value of 1oz, a current value of 1oz, and a current value of 1-1I@I *
7 noshi bale gold%U%m4 s 3s hiro each resistance value r9
r or 1e @ anti-duck/U is load m anti-31 with resistance value -1
The output line that ends at the end, SS, S is the input deviation amount H
a s Ik flow input -, casting &! As an example of a discussion, the G47 non-critical current value, Iop
lts@*Summer・Ik and resistance value rlq r or g should be set up using the following image adjustment formula.
・--=-(3) rl m r@-11/1!
−−−−−−−−−−(4) Out of the 3 input currents @Ia%Ib, only one input current is 1a.
* If the curve t- assumed to be injected into the ring gate circuit remains larger than the Io defined by the equation If the input current Iatt (4) formula % formula % (5) (6) is satisfied, the G-Cefnon junction 31.
32111 zero electric E type WiKlbt), output 1I36K
T! No output current flows.

次に下記の関係式を満尼する入力電[Ibが該論理ゲー
ト回路に注入されると、 Ia A + Ib > Is  −・−−−−−−−
−−−(ηIa + Ib > 2Io   =−−−
−−−=−−・−(8)(7)弐K @ 5て、ジ−セ
フノン接合32が電圧状態に遷移し、入力電流Ia s
 Ibはジ−セフノン接合s1に注入すれゐ・(8)弐
に91.りてジ謬セフノンm合$1も電圧状態に遷移し
、入力電@ Ia%Ibは出力線Uを過うて負IIl誕
抗訂に眞れ込む0入力端子IbがIaよ〕%ghに誼論
理ダーシ回路【注入され丸鳩舎は、上記O1!―でIa
とIbを入れ替えれば同様の説明が威)立つ。
Next, when an input voltage [Ib that satisfies the following relational expression is injected into the logic gate circuit, Ia A + Ib > Is −・−−−−−−−
---(ηIa + Ib > 2Io = ---
---=--・-(8) (7) 2K @ 5 Then, the G-Cefnon junction 32 transitions to the voltage state, and the input current Ia s
Ib is injected into the G-Cefnon junction s1 (8) 91. As a result, the input voltage @Ia%Ib passes through the output line U and enters the negative IIl output voltage.0 input terminal Ib becomes Ia]%gh. Logic dash circuit [Injected round pigeon house is O1 above! -de Ia
A similar explanation can be obtained by replacing Ib with Ib.

gs■伽)は(2)、m、m、(2)式およびIaとI
bを入れ替え良問IIO式よIllられゐ鋏論曹ダート
ー路の制御譬性を示しえもO″eある・本図かられかる
ように入力電流Ia%IbOうち1本だけが流れて−る
状態では、大IさSI@以上の入力電流か流れな−と鋏
論理ダー)alll紘電圧状簡に遷移し1に%I+%・
一方、大暑41)等しい入力電流Ia%Ibが流れてい
ると1a Ia m h m I・以上O入力電流値−
流れれば論理ダー)回路は電圧状態に遷移するOIiう
て、l1l−Ell来例として示し九電流沫入瀝論理ゲ
ートー路七MIIK、本発−O論■ゲートー路は威い動
作マージノ、ダート−路として高−刹得を有し1′1 て訃〕、高速な動作が可能である・さらに、本実施儒O
電線注入腫論理ダートー路では、ジ嘗セ7ツシ臨界電流
値、抵抗鍍銀(萄、(4)弐に示される相対的な閤係式
管沸足すれば嵐(%第1閣の従来例にお妙る前記(匂式
のようall路パラメータO絶対値を規定するような関
係式がなく、従りてリソグラブ/会術の許すllloI
回路O小飄化が可能である◎またインダクタンスを用い
ていない丸めに、インダクタンスとジ−セフノン接合の
キャパンタンスから住する共振現象がなく、回路上、共
mを抑える工夫を施す必**1−・まえ超電導ループ回
路を使2えゲート回路では&い大め、九とえ接地函で浮
遊O1l場をトラップしてしtりたとしても、伺も動作
には影響を受けない・ 本実施例の電流注装置論理ゲート釧路は、その高利lI
)特性から電流増幅器として%使用可能である・第3m
は増幅器として本実施例を用いた鳩舎O構成管示す・菖
2WIAの実施例における、入力電流Ibが流れる入力
lll59#ICは當に一定の電流Igを流してお(0
動作マージンを考慮して、電流値1gを入力電流lm=
00と1101論理ゲート1路O臨昇電流値31o(1
7511に設定する・従って、そOときの動作点拡第2
図の制御414IK$Pいて、41で表わすことができ
る0この状態で本論理ゲート1路を電圧状llK遷移さ
せるに必we最小の入力電流Iムはusl・である。電
圧状態に′会けるジーセフノン接舎01−タ電流を無視
すれば、本論鳳ゲート回踏O出力電流はSI@X O:
1! + OB1* ” LSI5と1k)、電流11
得1G$lIられることKなる@第1閣に示しえ従来例
の電流注入履論理ゲート回路における同様am流**は
、′#を埋6程度であ)、増幅器としてOSS%、本発
1llIO電流注入渥論理ダート回路O方がま畜ゐこと
がわかる・ 1に訃、実際の動作では〜動作マージノ等を考え・入力
電流IAO大11さはO−!IIoよ〕も大暑な値が選
ばれ、ll!うて、電圧状態における本論理ゲート回路
の動作点は88m42に対応するような点に@定される
gs ■ 伽) is (2), m, m, (2) formula and Ia and I
If b is replaced and the equation IIO is used, it is possible to show the control error of the scissors logic Darto path.As can be seen from this figure, only one of the input currents Ia%IbO is flowing. Then, if there is an input current greater than or equal to SI@, the scissors logic circuit transitions to all voltage states and becomes 1%I+%.
On the other hand, 41) If equal input current Ia%Ib is flowing, 1a Ia m h m I・or more O input current value -
If it flows, the circuit transitions to the voltage state. It has a high yield as a road, and is capable of high-speed operation.Furthermore, this implementation
In the electric wire injection tumor logic data path, the critical current value, resistance plated (萄), (4) 2 shows the relative clamping type tube boiling storm (% 1st cabinet conventional example) As mentioned above, there is no relational expression that defines the absolute value of the all-path parameter O, as in the Nishi-style method, and therefore the
It is possible to make the circuit O small ◎ In addition, since rounding does not use inductance, there is no resonance phenomenon that occurs from the inductance and the capantance of the G-Cefnon junction, so it is necessary to take measures to suppress the resonance on the circuit ** 1-・Even if a superconducting loop circuit is used and a stray O1L field is trapped in a grounded box, the operation will not be affected.・This example The current injection device logic gate Kushiro is its usurious lI
) Due to its characteristics, it can be used as a current amplifier.
Figure 2 shows the pigeon house O configuration tube using this embodiment as an amplifier. In the embodiment of the irises 2 WIA, the input llll59#IC through which the input current Ib flows, has a constant current Ig flowing therethrough (0
Considering the operating margin, the current value 1g is input current lm=
00 and 1101 logic gate 1 path O rising current value 31o (1
7511 ・Therefore, the operating point expansion at that time is the second
With the control 414IK$P in the figure, it can be expressed as 41. In this state, the minimum input current Im required to cause the present logic gate 1 circuit to transition to the voltage level IK is usl. If we ignore the current that can be applied to the voltage state, the output current of the main gate is SI@X O:
1! + OB1* ” LSI5 and 1k), current 11
As shown in the first cabinet, the same am current in the conventional current injection logic gate circuit is about 6), OSS% as an amplifier, and 1llIO from the present invention. It turns out that the current injection logic dart circuit O is more stupid.In actual operation, consider the operating margin, etc.The input current IAO is 11, which is O-! IIo] was also chosen with a very hot value, ll! The operating point of this logic gate circuit in a voltage state is determined at a point corresponding to 88m42.

以上に述ぺてきえ如く、本発明のり一七7ノン効!&を
層−九電msi入臘論理ゲート回路によれd1ジ1七7
ソレ集験回路を構成するうえでO基本的なゲート回路で
ある、積の論理ゲート回路をt従来のジーセフノン干論
理論履ゲート回路に劣らぬ、広い動作マージン、高利得
414Ikを維持した・tま、インダクタンスを用いな
い構造の論理ダート回路で実現で龜る。このため、上I
il!O論1ゲートl路は、従来O干渉瀝論理ゲート■
路とJIItkり、回路O小量<’bが可能、共振現象
を避けるための一路上O工夫が不要等の利点も同時に有
する論1ゲート回路である。
As mentioned above, the glue of the present invention is 177 non-effective! & layer - Kyuden msi input logic gate circuit d1 di 177
The product logic gate circuit, which is the basic gate circuit in configuring the integrated circuit, maintains a wide operating margin and high gain of 414Ik, comparable to the conventional logic logic gate circuit. Well, it's much easier to implement it with a logic dart circuit that doesn't use inductance. For this reason, above I
Il! O logic 1 gate l path is conventional O interference logic gate ■
It is a logic 1 gate circuit which also has advantages such as being able to operate with a small amount of circuit O<'b, and requiring no contrivance on the circuit to avoid resonance phenomena.

【図面の簡単な説明】[Brief explanation of the drawing]

′1Il1図はジ■セフソシ効果を用い九電流注入瀝論
理ゲート−路の従来例を説明するためoviaで、−)
拡開路間、伽)は該論理ゲート回路の制御特性を示す。 同図(a)において、10 、11はジ■セアノン接合
、121311イン〆クタンス、14.1S&!入力電
流路%16は出力線、17轄負荷抵抗−48は接地であ
る。岡m1(b)において20は該ゲート−路が積の論
理動作を行な5.ア、オ。 −) 第211は本発明のジ諧セツノン効果を用いた電流注入
飄論理ゲート1絡o−turnsをl!明するための図
で、(a)は回路図、伽)a皺論理ゲート回路の制御4
1惟である。Mll−にお−て巽、31 、32はジー
47ノン俵舎、ss 、 sa%U嬬諷抗、36は出力
線、νは負*m*%88%89は入力−,40社俵地を
示すも岡■(財)ETp%Aて41b4!は鋏論理ゲー
ト回路を電流増幅器として用−た場合O動作点を示す・
第slIは第3−に示す本実−〇−笑施儒である。 電流注入瀝論理ゲート崗路を電流増幅器として用い丸鳩
舎O構成を示す1賂図であゐ〇 1 、::5 4“パ綿 ′IA 1 図 (αン 4 ′(b) 第 2 図 、(α) (b) b 第3図 −145−
Figure '1Il1 is ovia to explain a conventional example of a nine-current injection logic gate circuit using the di-sefsoci effect.
Expanded circuits, 弽) indicate the control characteristics of the logic gate circuit. In the same figure (a), 10 and 11 are di-ceanon junctions, 121311 inductance, and 14.1S&! Input current path %16 is an output line, and load resistor 17 -48 is grounded. 5. In Oka m1(b), 20 performs the logic operation of the product of the gate-path. A, oh. -) No. 211 is l! (a) is a circuit diagram; (a) Control of logic gate circuit 4
It is 1. In Mll-, Tatsumi, 31 and 32 are G47 non-tawarasha, ss, sa%U 嬬薫, 36 is the output line, ν is negative*m*%88%89 is input-, 40 company-tawarasha Mooka■ (Foundation) ETp%Ate41b4! indicates the operating point when the scissor logic gate circuit is used as a current amplifier.
The slI is the Honji-〇-Shoshi Confucianism shown in the 3rd. This is a diagram showing a round pigeon house O configuration using a current injection logic gate circuit as a current amplifier. (α) (b) b Figure 3-145-

Claims (1)

【特許請求の範囲】[Claims] 一方が接地されたl110ジII−にフソン接舎に、籐
10人力線と第1&よび第3の抵抗〇一端とを接続し、
一方が接地され九菖20ジ■竜フソン接会には、出力−
と前記第1の抵抗O他端および第30抵抗の一端とを接
続し、一方が接地された第3のジーセ7ソシ接合KFi
、lM2O人力−と、前記第2および前記第3の抵抗の
他端とを接続し大ことを特徴とするジ嘗セフソン効果を
用いた電流注入蓋論思ゲート回路〇
Connect the rattan 10 power line and one end of the 1st & 3rd resistor to the l110ji II- with one end grounded to the Fuson ground,
One side is grounded and the output is -
and the other end of the first resistor O and one end of the 30th resistor are connected, and one end of the third resistor is grounded.
, lM2O human power - and the other ends of the second and third resistors are connected. A current injection lid logic gate circuit using the Sefson effect
JP56142748A 1981-09-10 1981-09-10 Current injection type logical gate circuit using josephson effect Granted JPS5843630A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP56142748A JPS5843630A (en) 1981-09-10 1981-09-10 Current injection type logical gate circuit using josephson effect
EP82108223A EP0074604B1 (en) 1981-09-10 1982-09-07 Circuit utilizing josephson effect
DE8282108223T DE3268138D1 (en) 1981-09-10 1982-09-07 Circuit utilizing josephson effect
US06/415,877 US4538077A (en) 1981-09-10 1982-09-08 Circuit utilizing Josephson effect
CA000411147A CA1189916A (en) 1981-09-10 1982-09-10 Circuit utilizing josephson effect
AU88311/82A AU553981B2 (en) 1981-09-10 1982-09-10 Josephson junction and gate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56142748A JPS5843630A (en) 1981-09-10 1981-09-10 Current injection type logical gate circuit using josephson effect

Publications (2)

Publication Number Publication Date
JPS5843630A true JPS5843630A (en) 1983-03-14
JPH0234492B2 JPH0234492B2 (en) 1990-08-03

Family

ID=15322658

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56142748A Granted JPS5843630A (en) 1981-09-10 1981-09-10 Current injection type logical gate circuit using josephson effect

Country Status (1)

Country Link
JP (1) JPS5843630A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0625192U (en) * 1991-02-16 1994-04-05 四倉 正勝 Compact disc tray
JPH0524591U (en) * 1991-08-07 1993-03-30 株式会社近畿ゼネラルサービス Compact disk storage jacket

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IBM TECHICAL DISCLOSURE BULLETIN *

Also Published As

Publication number Publication date
JPH0234492B2 (en) 1990-08-03

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