JPS5842712B2 - transistor warmer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transistor circuit that alternately drives a pair of transistors.

Push-pull transistor circuits are often used in DC-AC conversion or DC-DC conversion devices.

FIG. 1 shows a half-bridge type converter, in which a pair of transistors 1, 2 and a pair of capacitors 3, 4 are connected to a DC power supply 5, respectively, and a midpoint between the pair of transistors 1, 2 and a pair of capacitors 3, 4 are connected to a DC power source 5. An output transformer 6 is connected between the intermediate point of 4 and the intermediate point of 4.

A rectifying diode 7.8, a smoothing electrode 9, and a capacitor 10 are connected to the output of the output transformer 6.

In this inverter, by applying a base signal to transistor 1 using terminals 11 and 12, transistor 1 is turned on, and the circuit consisting of transistor 1, transformer 6, and capacitor 4 generates a current in the first direction. flows,
A voltage in the first direction is induced in the secondary winding of the transformer 6.

Also, by applying a base signal to transistor 2 using terminals 13 and 14, transistor 2 is turned on, and a current in the second direction flows in the circuit consisting of capacitor 3, transformer 6, and transistor 2, and the transformer A voltage in the second direction is induced in the secondary winding of 6.

Thereby, an output voltage at a level different from the voltage of the DC power supply 5 can be obtained from the output terminals 15 and 16.

In a circuit that alternately turns on and off a pair of transistors as described above, due to the storage effect of the transistors or other reasons, the pair of transistors 1 and 2 turn on at the same time, forming a short circuit and destroying the transistors. Sometimes.

Of course, if a sufficient no-signal period is provided between the base signals of the transistors 1 and 2, the transistors will not turn on at the same time, but this will make it impossible to increase the conversion frequency.

Furthermore, it becomes impossible to perform significant pulse width control.

The present invention has been made to eliminate the above-mentioned drawbacks, and it is an object of the present invention to provide a transistor circuit that prevents a pair of transistors from being turned on at the same time due to storage effects or the like.

A transistor circuit according to the present invention for achieving the above object is a transistor circuit that alternately turns on and off a first transistor and a second transistor.
a first capacitor connected to the base circuit of the first transistor so as to be charged with the base signal of the transistor and apply a reverse bias voltage to the first transistor after the base signal disappears; and a second capacitor connected to the base circuit of the first transistor. a second capacitor connected to the base circuit of the second transistor so as to be charged with the base signal of the second transistor and apply a reverse bias voltage to the second transistor after the base signal disappears; a first transistor off detection circuit that detects the off state of the transistor based on the fact that the reverse bias current becomes substantially zero; and a first transistor off detection circuit that detects the off state of the transistor based on the fact that the reverse bias current of the second transistor becomes substantially zero. a second transistor off detection circuit that detects off of the transistor; and a second transistor off detection circuit that blocks supply of a base signal to the transistor until an off detection signal is obtained from the first transistor off detection circuit. a first gate circuit that enables supply of a base signal to the second transistor when the off detection signal is obtained from the first transistor off detection circuit; and off detection from the second transistor off detection circuit. Blocking the supply of the base signal to the first transistor until the signal is obtained, and supplying the base signal to the first transistor when the off detection signal is obtained from the second transistor off detection circuit. The present invention is characterized in that it is provided with a second gate circuit that enables this.

In the present invention, the first and second capacitors are, for example, capacitors connected in parallel to a resistance circuit consisting of a diode or the like connected in series to a base circuit.

The first and second transistor-off detection circuits can be configured with, for example, a current transformer or a light emitting element connected to a base circuit, and a circuit that generates an output corresponding to a change in these elements.

The first and second gate circuits may be composed of, for example, NAND gates.

In the present invention, a reverse bias is applied as described above, and during a period when a reverse bias current is flowing, even if a signal that turns on the other transistor is generated, it is not sent to the transistor. so that both transistors are not turned on at the same time.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 shows a converter drive circuit according to one embodiment of the present invention.

The inside of the converter 20, which is shown surrounded by a dotted line, is the same as the circuit shown in FIG.
only is shown.

The first control signal terminal 21 on the left side is a base signal supply terminal for turning on the transistor 1, and the second control signal terminal 22 is a base signal supply terminal for turning on the transistor 2.

In principle, signals are applied alternately to this.

The N-AND gates 23 and 24 are gates for not directly sending the base signals applied from the terminals 21 and 22 to the bases of the X transistors 1 and 2, but only for a period that satisfies a certain condition.

A center-tap type transformer 25 to which the outputs of NAND gates 23 and 24 are connected is used to drive the bases of transistors 1 and 2, and a current adjustment resistor 2 is connected to the center tap.
A power supply terminal 26 is provided via the NAND terminal 6a.
While the output of the gate 25 is at a low level, the positive power supply terminal 26
A circuit is formed with the upper half 27 of the primary winding and the signal driving the transistor 1 is induced in the secondary winding 29, while the other N
During the period when the output of the AND gate 24 is at a low level, a circuit is formed between the positive power supply terminal 26 and the lower half 28 of the primary winding, and a signal for driving the transistor 2 is induced in the secondary winding 30. .

A parallel circuit consisting of a capacitor 31 for reverse biasing the transistor and a dropper diode 32 for charging the capacitor is connected between the secondary winding 29 and the base of the transistor 1.

Similarly, a parallel circuit consisting of a capacitor 33 and a diode 34 is connected between the secondary winding 30 and the base of the transistor 2.

A current transformer 35 coupled to the base circuits of transistors 1 and 2 detects the reverse bias current of transistors 1 and 2, respectively, and one end of the current transformer 35 is connected to the base of a detection transistor 36. , the other end is connected to the base of the detection transistor 37.

A diode 38 is connected in the opposite direction between one end of the current transformer 35 and the ground, and a diode 39 is connected in the opposite direction between the other end and the ground.

Since the emitters of the transistors 36 and 37 are each grounded, the transistor 36 is turned on only when a reverse bias current in the first direction is detected, and the transistor 36 is turned on only when a reverse bias current in the second direction is detected. 37 is turned on.

The collector of transistor 36.37 is resistor 4.0
, 41 to the positive power supply terminals 40', 41', and the JK for controlling the NAND gates 23, 24.
They are connected to the CK terminals of flip-flops 42 and 43, respectively.

The J terminals of the flip-flops 42 and 43 are connected to the positive power supply lines 44 and 45, respectively, and the K terminals are connected to the negative power supply line 4.
6 and 47, respectively.

Further, the outputs of the differentiating circuits 4B and 49 are coupled to the CL terminals of the flip-flops 42.43, and the control signal terminals 22.2
A differential pulse of the rising edge (leading edge) of the base control signal supplied from 1 is applied.

The Q output terminal of the flip-flop 42.43 is coupled to the input of a NAND gate 23.24, and the application of the base signal is controlled by this output.

Next, the circuit operation will be described with reference to waveform diagrams of various parts of the circuit of FIG. 2 shown in FIGS. 3 and 4.

In Figures 3 and 4, A-J indicates voltage waveforms, and K
and L indicate the current waveform.

When a high level base control signal is applied to the terminal 21 at time t1 as shown in FIG.
As shown in FIG. C, a differential pulse is generated at the rising edge (leading edge) of the base control signal, and this is applied as a reset signal to the CL terminal of the flip-flop 43.

As a result, the Q output terminal of the flip-flop 43, which has been at a high level until now, changes to a low level as shown in FIG. 3G, making the NAND gate 24 inoperable.

That is, even if a base signal is applied from the terminal 22, it is not transmitted.

At t, the Q output terminal of the other flip-flop 42 is held at a high level as shown in FIG. Upon receiving the base signal shown in A, its output changes to a low level as shown in FIG.

As a result, the power supply terminal 26 and the upper half 27 of the primary winding and the NA
A circuit is formed from the ND gate 23, and the secondary winding 2
A voltage is induced at 9 that turns on transistor 1.

As a result, a base current flows through the base of transistor 1 as shown in FIG. 3K, and transistor 1 is turned on.

At this time, as shown in the third diagram, transistor 2 is not supplied with base current and is off.

Base current I is applied to transistor 1 through diode 32.
When B1 flows, the capacitor 31 is charged with the illustrated polarity based on the forward voltage drop of the diode 32.

Base control signal applied from terminal 21. disappears at time t2, the voltage across capacitor 31 reverse biases transistor 1.

Even when the base signal disappears and a reverse bias voltage is applied, transistor 1 does not turn off immediately; the base current continues to flow due to the storage effect, and transistor 1 is kept on even after t2.

t3 after the base current in the positive direction falls even at t3
During the period from t4 to t4, a base current in the reverse direction flows as a reverse bias current as shown in FIG. 3K.

The current transformer 35 constantly detects the base currents of the transistors 1 and 2, and generates an output that turns off the detection transistor 36 and turns on the transistor 37 during the period from tl to t3. The collector potential of the transistor 36 becomes a high level as shown in FIG. 3F, and the collector potentials of the transistors 3 and 7 remain low as shown in FIG. 3E.

During the period from t3 to t4, a reverse bias current flows through the base circuit of the transistor 1 as shown in FIG. 3K, so the detection transistor 36 is turned on and the detection transistor 37 is turned off.

As a result, the collector potential of transistor 36 becomes low level, and the collector potential of transistor 37 becomes high level as shown in FIG. 3E.

As shown in FIG. 3E, when a high level signal is generated from t3 to t4, it is applied to the CK terminal of the flip-flop 43, and the Q output terminal of the flip-flop 43 is connected to the falling edge (trailing edge) of the high level signal in FIG. 3E. ) At time t4, the low level changes to the high level as shown in FIG. 3G.

Therefore, after t4, the NAND gate 24 becomes operational.

In other words, after the transistor 1 is completely turned off by the reverse bias applied by the capacitor 31, the NAND gate 24 becomes operational, and the other transistor 2 can be turned on at any time.

In the waveform diagram of FIG. 3, the signal to turn on transistor 2 is not added immediately after the base signal of transistor 1,
It has been added as t.

At t5, when a base control signal is applied to the terminal 22 as shown in FIG.
and will be granted.

Since the NAND gate 24 is in the operable state as described above, its output changes to a low level from t5 to t6, and current flows in the circuit between the power supply terminal 26 and the lower half 28 of the primary winding, and the secondary winding A base drive signal is generated at 30.

At this time, a differential pulse is generated from the differentiating circuit 48 as shown in the third diagram, which is applied to the flip-flop 42 as a reset pulse, and the Q output terminal is switched to a low level at t5, allowing one NAND gate 23 to operate. keep it in good condition.

The voltage across the secondary winding 30 keeps the transistor 2 on, and at this time the drop across the diode 34 charges the capacitor 33.

Even when the base signal disappears at t6, the base current continues to flow in the storage, and during the period from t7 to t, when the base current in the reverse direction, that is, the reverse bias current flows as shown in Figure 3, this time the collector of the detection transistor 36 flows. The potential becomes high level as shown in FIG.
, the level of the Q output terminal of the flip-flop 42 does not change until the fall time t8 of this high level signal, keeping the NAND gate 23 operable.

However, at t8, the level of the Q output terminal is reversed,
NAND gate 23 becomes operational.

Therefore, it becomes possible to turn on transistor 1 again after t8.

By repeating the above operation, a pair of transistors 1
, 2 are turned on and off alternately, and are never turned on at the same time.

That is, after a reverse bias current flows through the conversion transistor 1 or 2 that has been turned on, the base signal of the transistor 2 or 1 that will be turned on next is applied, so that both transistors will not be turned on at the same time.

The waveform shown by the dotted line in FIG. 3 shows the case where the pulse width of the base control signal is increased.

FIG. 4 shows a state in which this pulse width is further increased.

In the case of FIG. 4, after the base control signal supplied from the terminal 21 shown in FIG. 4A falls at tl, the base control signal is supplied from the terminal 22 as shown in FIG. 4B at t2. .

The interval from tl to t2 is extremely small.

In the conventional device, if the interval from tl to t2 is shorter than the storage time of transistor 1, then t
At time point 2, both transistors 1 and 2 are turned on at the same time, causing an overcurrent to flow and destroying transistors 1 and 2.

In contrast, in this device, even though the period up to tl is short, the base signal is not applied to transistor 2 at t2,
As shown in FIGS. 3J and 3L, the base signal is applied at t3 after transistor 1 is completely turned off.

That is, as shown in FIG. 4K, the detection transistor 37 detects a time t3 at which the reverse bias current in the transistor 1 disappears, and at this time t3, the Q output terminal of the flip-flop 43 changes as shown in FIG. 4G. The base signal is applied to transistor 2, switching to a high level and enabling NAND gate 24.

As a result, transistors 1 and 2 will not be turned on at the same time, and transistors 1 and 2 will not be destroyed by overcurrent.

Next, a second embodiment of the present invention will be described with reference to FIG.

However, parts common to those in FIG. 2 are given the same reference numerals and their explanations will be omitted.

The base signal transmission circuit section in the circuit of this embodiment is constructed at the same time as that of the first embodiment, but the detection control circuit section is modified.

A circuit consisting of light emitting diodes 51 and 52 and resistors 53 and 54 with opposite polarity is connected between the base and emitter of the conversion transistors 1 and 2.

Detection phototransistors 55 and 56 forming photocouplers with light emitting diodes 51 and 52 have their emitters grounded, and their collectors are connected to positive power supply terminals 59 and 60 via resistors 57 and 58, respectively, and are connected to inverter 61.
．． There are 62 inputs.

The outputs of inverters 61 and 62 are NAND gates 23 and 2
4 inputs, respectively.

Next, the operation of the above-mentioned circuit will be explained with reference to the waveform diagrams of FIGS. 6 and 7.

In Figures 6 and 7, A-F indicates voltage waveforms, and G
and H indicate the current waveform.

As shown in FIG. 6A, when the base control of the transistor 1 is applied from the terminal 21 during the period from 11 to t2, since the NAND gate 23 is closed during this period, the \base signal is applied as is, 6 As shown in Figure G, the base current I
flows.

Even if the base control signal disappears at t2, 13
A positive base current continues to flow until t4, and a reverse bias current flows during the period from t3 to t4 as in the first embodiment.

When a reverse bias current flows and the transistor 1 is completely turned off at t4, a voltage is applied from the capacitor 31 to the light emitting diode 51, which has been substantially short-circuited by the transistor 1, and the light emitting diode 51 emits light at t4.

The light emission from the light emitting diode 51 is maintained until the period when the transistor 1 is turned on in the next cycle.

When the light emitting diode 51 emits light at t4, the phototransistor 55 is turned on and the input of the inverter 61 becomes low level, so its output becomes high level as shown in FIG. 6, and the NAND gate 24 becomes operational.

As a result, when the base control signal is supplied from the terminal 22 with < 15 as shown in FIG. 6B, the NAND gate 24
A base control signal is transmitted through the transistor 2, and the transistor 2 is turned on.

Even if the base signal disappears at t6, transistor 2 is kept on by the storage, and a reverse bias current begins to flow from t7.

At t8, when the transistor 2 is completely turned off and the reverse bias current becomes zero, the light emitting diode 52 emits light, the phototransistor 56 is turned on, and the inverter 6
The output of 2 becomes high level as shown in Figure 6C, and the NAN
D gate 23 becomes operational.

The waveform shown by the dotted line in FIG. 6 shows the case where the pulse width of the base control signal is changed.

FIG. 7 shows the base control signal supplied to terminal 21 and the terminal 22.
FIG. 4 is a waveform diagram showing a state where the base control signal supplied to the base control signal and the base control signal are very close to each other.

In this case, the base control signal of the transistor 2 is supplied during the period when the base control signal of the transistor 1 disappears at tl and the transistor 1 is turned on in the storage.

Even if the base control signal of transistor 2 is supplied at t2,
It is blocked by NAND gate 24 and is not immediately supplied to transistor 2.

At time t3, when the reverse bias current of the transistor 1 becomes zero and the light emitting diode 51 emits light, the NAND gate 24 becomes operational and a base signal is applied to the transistor 2.

Therefore, transistors 1 and 2 are not turned on at the same time.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-mentioned embodiments, and can be further modified.

For example, a resistor may be connected in place of the diodes 32 and 34.

In short, anything can be used as long as it can charge the capacitors 31 and 33.

In addition, in FIG. 2, one current transformer 35 is used to connect transistors 1 and 2.
It is designed to detect the base current of both
A current transformer may be provided independently.

Furthermore, detection of the base current and control of transmission of the base control signal may be performed by a circuit other than the embodiment.

Alternatively, the base current may be detected on the primary side of the transformer 25.

Moreover, it is applicable not only to half-bridge type converters but also to bridge-connected converters, push-pull amplifier circuits, and any circuits that alternately turn on and off transistors.

In short, the present invention can be applied to any circuit in which it is difficult for a pair or a plurality of transistors to be turned on at the same time.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a DC-DC converter, Fig. 2 is a circuit diagram of a drive control section of a converter according to the first embodiment of the present invention, and Figs. 3 and 4 are diagrams of each part of Fig. 2. Voltage and current waveform diagrams; FIG. 5 is a circuit diagram of the drive control section of the converter according to the second embodiment of the present invention; FIGS. 6 and 7 are voltage and current waveform diagrams of each part of FIG. 2. It is. In addition, in the symbols used in the drawings, 1 and 2 are transistors, 21 and 22 are control signal terminals, and 23 and 24 are NA
ND gate, 25 is a transformer, 31 is a capacitor, 32 is a diode, 33 is a capacitor, 34 is a diode, 3
5 is a current transformer, 36 and 37 are transistors, and 42 and 43 are flip-flops.

Claims (1)

[Claims] 1. In a transistor circuit that alternately turns on and off a first transistor and a second transistor, the first
a first capacitor connected to the base circuit of the first transistor so as to be charged with a base signal of the transistor and apply a reverse bias voltage to the first transistor after the base signal disappears; a second capacitor connected to the base circuit of the second transistor so as to be charged with a base signal of the transistor and apply a reverse bias voltage to the second transistor after the base signal disappears; and a second capacitor connected to the base circuit of the second transistor. a first transistor off detection circuit that detects that the first transistor is off based on the fact that the reverse bias current of the second transistor becomes substantially zero; a second transistor off detection circuit that detects whether the second transistor is off based on the fact that the second transistor is turned off; a first gate circuit that blocks the supply of the signal and enables supply of the base signal to the second transistor when the off detection signal is obtained from the first transistor off detection circuit; The supply of the base signal to the first transistor is blocked until an OFF detection signal is obtained from the transistor OFF detection circuit, and when the OFF detection signal is obtained from the second transistor OFF detection circuit, the supply of the base signal to the first transistor is blocked. A transistor circuit characterized in that it is provided with a second gate circuit that enables supply of a base signal to the transistor.