JPS61218374A - Driving method for inverter - Google Patents

Abstract

PURPOSE:To effectively prevent the simultaneous ON of both two switching elements by interrupting drive signals to the two switching elements while the reverse bias currents of the elements become the prescribed level or higher. CONSTITUTION:The first and second NPN type transistors 11, 12 for forming one and other switching elements are connected in series. The reverse bias currents of the transistors 11, 12 are monitored by photocouplers 23, 25, a drive signal given from an AND gate 18 to the transistor 12 is interrupted while a reverse bias current of the prescribed level or higher is flowed to the transistor 11, and a drive signal given from an AND gate 15 to the transistor 11 is interrupted while the reverse bias current of the prescribed level or higher is flowed to the transistor 12.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is characterized in that two switching elements connected in series between both ends of a DC power supply are driven to switch in a complementary manner, and a pulse waveform is generated at the connection point of both switching elements. The present invention relates to an inverter driving method that produces an inverter output of .

[Conventional technology]

Conventionally, this type of inverter has two switching elements, for example, two NPN transistors, between both ends of a DC power supply (1), that is, between the positive and negative terminals (+), as shown in Figure 3. +2), (31) connected in series, and due to the complementary switching of transistors +2), +3), the connection point between the emitter of transistor (2) and the collector of transistor C3), i.e. at the output terminal (4). , a pulse waveform inverter output is generated.

Note that the collector of the transistor (2) is connected to the positive terminal (+), and the emitter of the transistor (3) is connected to the negative terminal (←).

In addition, transistors (2+, (
3) are connected to the drive signal input terminals (5) and +61 via base resistors (R], ) and (R2), respectively, and the bases of the first and second signals input to the input terminals (5) and (61) are connected to the drive signal input terminals (5) and +61, respectively, through base resistors (R], ) and (R2).
Transistors (2) and (3) each switch according to the second drive signal.

By variably setting the switching frequency of the transistor +21 (3), an inverter output having a pulse waveform of a desired frequency is generated at the output terminal (4).

By the way, when driving the inverter shown in FIG. 3, for example, the method described in Japanese Patent Application Laid-open No. 59-86480 is used.・In order to prevent short circuits due to simultaneous ON of transistors (2) and +3), that is, short circuits of the power supply, during the ON period of the drive signals of both transistors (2) and (3),
It is necessary to provide a simultaneous off time longer than the operation delay time of transistors +2) and (3).

As described in the above-mentioned publication, conventional circuits for driving inverters, that is, the above-mentioned first circuit. The drive circuit that forms the second drive signal is formed using an OR delay circuit, for example as shown in FIG. The reference pulse signal of the reference input terminal (7) originally formed, the integrating resistor (R8) and the capacitor (C
2) gate-processing the reference pulse signal delayed by the OR delay circuit for the first drive signal using an AND gate (8) for the first drive signal to form the first drive signal; An inverted reference pulse signal formed by inverting the reference pulse signal by an inverter (9), an integrating resistor (R4) and a capacitor ( C3
), the inverted reference pulse signal is delayed by the OR delay circuit for the second drive signal, and gate-processed by the ant gate 100 for the second drive signal to form the second drive signal.

In this case, based on the time constants of the OR delay circuit of the resistor (R8) and the capacitor (C2) and the OR delay circuit of the resistor (R4) and the capacitor (C3), the positive voltage is The rise to the on level, that is, the rise from low level to high level, is delayed from the rise of the reference pulse signal, and the rise of the second drive signal is delayed from the fall of the reference pulse signal, and before the rise of both drive signals. A period between simultaneous off levels is formed.

Based on the first and second drive signals, transistors (21 and (31) turn on transistor (2), simultaneously turn off transistors (21 and (3)), and turn on transistor (3).

Transistors +2) and +3) are simultaneously turned off and transistor (2) is turned on repeatedly to perform complementary switching.

[Problem that the invention seeks to solve]

By the way, number one. Transistor (21
, (31) will be explained below.

For example, when the first drive signal becomes an on level of a positive voltage at the time of ta, based on the voltage drop of the resistor (R1), the base voltage Th+ of the transistor (2) and the base II current 11t
+ is a forward bias voltage of about 0.7 V and a positive forward bias current of 10 hm K at ta, as shown in FIG. 5(a), (1)).

In addition, the collector current ICl1j of transistor (2):
As shown in FIG. 5(C), the on period Ton starts from time ta.
The current increases from 0 to a constant positive current after a delay of 0.

Then, at time tb, when the first drive signal becomes the off level of a negative voltage, the base t of the transistor (2)
As shown in Figure 5(b), the reverse bias current becomes a nearly triangular waveform, and after reaching the negative maximum current -bmK, the collector current Ic+ becomes 0 as shown in Figure 5(C). When.

That is, it returns to 0 at time ta, which is delayed by the off period Tof from time tb.

As shown in Fig. 5(a), the base voltage Vln of the lc4 transistor (2) is based on the inherent impedance characteristics, and the base voltage Vln of the lc4 transistor (2) is a resistance from the time tb when the first drive signal becomes off level until the time I\tc. It decreases as the voltage of (R1) drops and reaches the maximum negative voltage at ta.

Since transistor (2) is on from approximately ta to t, 0 o'clock, transistors (2) and (3) can be switched in a complementary manner by providing a simultaneous off period for transistors (2) and (3). , the second drive signal is turned on at time t, 4, which is delayed by the delay time T from time t1 when the first drive signal becomes off level, and the base voltage Vl)2 of the transformer risk (3) is changed to Fig. 5(d). ) as shown in 1.4
Sometimes it is necessary to turn it on with a forward bias voltage of about 0.7 µ.

In addition, the collector current of the transistor (3) also changes depending on the second drive signal, as in the case of the transistor (2), having an on period and an off period. When the signal becomes off level at time te before time ta and the base voltage of the transistor (3) starts to decrease at time te, the time ta for the first drive signal to become on level is set from time te to the delay time Td+. It is necessary to set the time to a time delayed by the delay time Td2.

That is, 1st. Transistor +2 by second drive signal
1, +3) is determined by the level change of the drive signal, the characteristics of the transistor C2J, (3),
Delay time Td+, Td based on drive signal level etc.
Late by 2.

Therefore, in order to switch transistors (2) and (31) in a complementary manner with simultaneous off periods, first and second
It is necessary to delay the rise of the drive signal by the respective delay times Td3Td+.

On the other hand, if the delay times T+J+ and Td2 become longer than necessary, and the simultaneous off period of transistors (2) and +3) becomes longer than necessary, the waveform of the inverter output at the output terminal (4) will change to the waveform of the inverter output at the input terminal (7). Unlike the control signal waveform,
Inverter output with the desired waveform cannot be obtained.

Since the delay time Td, +, Ta2 differs based on the characteristics of the transistor +21, (3), the level of the drive signal, etc., the first. During the simultaneous OFF period in which the second drive signals are simultaneously at the OFF level, transistors (2), (
3), it is necessary to accurately set the period to the minimum necessary period according to the level of the drive signal.

Also, during the simultaneous off period, transistors (2) and (3)
It also changes due to changes over time.

However, as mentioned above, the analog OR delay circuit
1st. When forming the second drive signal, it is difficult to accurately set the simultaneous off period to the minimum necessary period, and in reality, it is difficult to set the simultaneous off period to the minimum necessary period.

The only option is to set the time constant of the OR delay circuit so that the deterioration between the switching characteristics in (3) and the waveform of the inverter output does not become too significant, and to set the simultaneous off period to a fixed period that is almost the minimum necessary. For example, due to an abnormality in the base circuit of transistors (2) and (3),
When transistor (2) or (3) turns off, the reverse bias current decreases and transistor (2) or (3) turns off.
3) is not completely turned off, and the transistor (
When the delay time Td+ or Ta2 in 2) or (3) becomes longer than the simultaneous off period, the transistor (2).

There is a problem in that power supply short circuit occurs due to (3) being turned on simultaneously.

On the other hand, as in the above-mentioned publication, the first .
Even when the second drive signal is formed, problems similar to those described above arise due to changes over time, temperature changes, and the like.

Not only when the switching element is formed by transistors (21 and 31) as shown in Fig. 3, but also when an element such as a gate turn-off thyristor (GTO) is formed, the simultaneous off period is kept to the minimum necessary. There is a problem in that it is not possible to prevent power supply short circuits due to simultaneous on by setting the period.

[Means for solving problems]

The present invention provides an inverter driving method in which two switching elements connected in series between both ends of a DC power source are driven to switch in a complementary manner, and an inverter output having a pulse waveform is generated at a connection point between the two switching elements. The first level changes between on level and off level. The second drive signal is formed with a period in which it becomes off level at the same time, and the both drive signals are respectively supplied to the control terminals of both the switching elements, and when the OFF change occurs at the control terminals of both the switching elements. detecting a period during which the reverse bias current of one of the switching elements exceeds a certain level, and supplying the second drive signal to the other switching element while the reverse bias current of one of the switching elements exceeds the certain level. and prevents the supply of the first drive signal to the one switching element while the reverse bias current of the other switching element exceeds the predetermined level; This is an inverter driving method characterized by performing switching driving with a simultaneous off period set depending on the level of a reverse bias current.

[For production]

Therefore, even if the switching characteristics of both switching elements change due to the characteristics of both switching elements, the level of the drive signal, changes over time, etc., the reverse bias current of one switching element remains constant and the other switching element remains While the reverse bias current of the other switching element is above a certain level, one switching element will not turn on, and the first switching element will not turn on.
Even if the second drive signal sets the simultaneous off period to be shorter than the minimum necessary period, simultaneous on of both switching elements is reliably prevented.

〔Example〕

Next, the present invention will be explained in detail with reference to FIGS. 1 and 2 showing one embodiment thereof.

(Structure) In FIG. 1, al) and oa are the NPN type first .al and oa forming the other switching elements. The collector of the second transistor (1υ) is connected to the positive terminal (+) of the DC power supply, and the emitter of the transistor α is connected to the negative terminal (←) of the DC power supply, and the emitter of the transistor (11) An output terminal 03 is connected to a connection point with the collector of the transistor θ.

θ4) is a reference input terminal into which the reference pulse signal shown in Fig. 2(a) is input, and 00 is a 3 input terminal ((13)
> , (γ), the input terminal (α) is connected to the input terminal 04), and the input terminal (fi) is connected to the input terminal θ4) via the integrating resistor (R1). An integrating capacitor (CI) is connected between the input terminal 04) and the ground terminal OQ, and an OR delay circuit for the first drive signal is formed by the resistor (R1) and the capacitor (CI). ing.

θ is the inverter connected to input terminal 04), 08)
is a second AND gate having three input terminals (αr, φf, (γf), and the input terminal (αf) is connected to the inverter 071, and the input terminal (J3r) is connected to the inverter via the integrating resistor (R2). (]7), and an integrating capacitor (C2) is provided between the input terminal (β) and the ground terminal θ6), and the resistor (R2) and capacitor (C2) are connected to the An OR2 delay circuit is formed.

0 is the first amplifier whose input terminal is connected to the output terminal of Antoge 1-(1■), which is formed by an input/output isolation type amplifier, and whose output terminal is connected to the first drive signal input terminal,
It is connected to the control terminal, ie, the base, of the transistor (]1) via the base resistor (R3).

(21) is a second amplifier whose input terminal A is connected to the output terminal of the antenna gate 1-(18), and is formed by an input/output isolation type amplifier, and whose output terminal is the second drive signal input terminal +221. It is connected to the control terminal of the transistor θ, that is, the base, via a base resistor (R4).

(23) is a light emitting die, +--de (28a), NPN
'yJ9 (7) 7:t l・l・lungister (
23+)) with the first photocoupler formed by
The anode of the diode (23a) is connected to the input resistor (R5
) is connected to the base of the transistor (11) via the phototransistor (23b), and the cathode of the diode (23a) is connected to the input terminal (a).
) is connected to the input terminal (γ terminal), and the emitter of the phototransistor (23b) is connected to the ground terminal θ.
Connected to 0. (R6) has one end as the positive power supply terminal (2
4), and the other end is connected to the collector of the phototransistor (231)).

Inside is a light emitting diode (25a), a second photocoupler formed by an NPN phototransistor (25b), and the anode of the diode (25a) is connected to the base of the transistor θ via an input resistor (R7). At the same time, the cathode of the diode (25a) is connected to the input terminal (221), the collector of the phototransistor (25+)) is connected to the input terminal (γ), and the emitter of the phototransistor (251)) is connected to the input terminal (221). It is connected to the ground terminal 06). One end of (R8) is connected to the collector of the l-transistor (25+1), which is a bias resistor connected to the positive power supply terminal (24 (the other end is FO)).

(Operation) A reference pulse signal is input to input terminal 04) in the same way as input terminal (7) in Figure 3, and at this time, the reference pulse signal is passed through an OR delay circuit of a resistor (R1) and a capacitor (CI). The signal at the input terminal (J3) is delayed from the rising edge of the reference pulse signal to TD+ as shown in Figure 2 (1).
The threshold of the AND gate 05) is delayed by the dashed line in the same figure.

The reference signal of the input terminal θ4) which has been switched is the inverter a'7)
At the same time, the output signal of the inverter θ''I) is delayed by the resistor (R2) and the capacitor (C2) (4 delay circuits), and the signal at the input terminal φf is the falling edge of the reference pulse signal, that is, the inverter 07). The threshold level of the AND gate θ8) is delayed by TD2 from the rising edge of the output signal.

Therefore, based on the reference pulse signal of the input terminal (α) and the delayed signal of the input terminal (J3),
As shown in FIG. 2(C), the first drive signal for the first drive signal has a waveform that rises with a delay of a period TD+ from the rise of the reference pulse signal and falls in synchronization with the fall of the reference pulse signal.
The gate signal is formed, and the ant-game 1-Q8) is connected to the inverted reference pulse signal of the input terminal (A) and the input terminal (F3)
Based on the delayed signal of ', as shown in (d) of the same figure,
A second gate signal for the second drive signal is formed with a waveform that rises with a delay of a period TD2 from the fall of the reference pulse signal and falls in synchronization with the rise of the reference pulse signal.

On the other hand, the light emitting diodes (28a) and (25a) are connected to the transistor (11) and the resistor (R3) when the alpha signal is reversed from on to off.

(R4) Detects the negative reverse bias current flowing through each transistor, and lights up while the reverse bias current of transistor a]) and oa exceeds a certain level.

When the light emitting diodes (23a) and (25a) are turned on, the phototransistors (281) and (251)
) are turned on, and at this time the input terminals (γ) and (γ)
' is held at low level.

Therefore, the photocoupler (23) monitors the reverse bias current of the transistor (11), and the photocoupler (23) monitors the reverse bias current of the transistor (11).
When a reverse bias current of a certain level or higher does not flow through 11), a second gate signal is output from the amplifier (108) to the amplifier output, and a positive current is output from the amplifier (1) to the base of the transistor 0 based on the second gate signal. , while the second drive signal that changes negatively is output and a reverse bias current of a certain level or higher flows through the transistor (11), the ant-gate
- The second gate signal from (1, 8) is completely blocked and the second drive signal is blocked.

Similarly, photocoupler (25j) and transistor 0''
; When the reverse bias current of transistor 4 is monitored, and the transistor 0 is constant and the reverse bias current on betLyL-J does not flow, the first gate signal is output from ant gate 1-(151 to amplifier 09, and the amplifier Scream or La Transistor (11
) is outputted to the base of the AND gate (the first drive signal that changes from positive to negative based on the first gate signal), and while a reverse bias current of more than 1 novel flows through the transistor 04, the The first gate signal is cut off and the first drive signal is cut off.

When the first drive signal is on level, based on the first drive signal level and the resistance value of the resistor (R3), the base current I]31 of the transistor 0υ reaches the positive maximum as shown in FIG. 2(e)K. When the current becomes a forward bias current of 10 Bm and the transistor (1) turns on, and the first drive signal is reversed from the on level to the off level, the base current IBI
becomes a reverse bias current and changes into an almost triangular wave shape, and decreases to the negative maximum current -Bm after a period Tx+ from the fall of the first gate signal, and returns to O after a period TD11, at which time the reverse bias current reaches its maximum It is set based on the current 4-Bm, the level of the first drive signal, and the resistance value of the resistor (R3), and the dashed line in FIG. 2(e) indicates the set detection level -Bx of the reverse bias current. .

Also, the collector current of the transistor θη is the base current 1
Since it changes according to the change in 111, Fig. 5 (0)
The delay periods corresponding to the delay periods Ton and Tof also change based on the base current In+.

By the way, when the base current In+ of the transistor (11) becomes a reverse bias current, the light emitting diode (23a) is forward biased, a forward bias current proportional to the light emitting diode (23a) K base current IBL flows, and the reverse bias current reaches the detection level. -The maximum current is more than Bx and is almost negative.-
During the period TDI+ close to Bm, the light emitting diode (23
&) lights up.

That is, the period 1゛X1 from the fall of the base current IB+
After the reverse bias current increases to the detection level -Bx or more with a delay of 100 seconds, the period TDI+ until the reverse bias current decreases to the detection level -Bx via the negative maximum current -Bm,
The light emitting diode (23a) lights up.

Then, when the light emitting diode (28a) lights up, the phototransistor (281)) turns on, and the AND gate 08)
The input terminal (γr is the period T as shown in FIG. 2(f))
Only D+ is kept at a low level, and during a period Tn+1, the second drive signal is cut off and one transistor Q is kept off.

Therefore, the second gate signal output from the Antogame 108) to the amplifier (A) is as shown in FIG. 2(g).
Compared to the waveform shown in FIG. 2(d) based on the reference pulse signal and the delayed signal, the rising edge is delayed by approximately the period TD11, and as a result, the second drive signal also changes at the timing shown in the same figure @). become

On the other hand, when the second drive signal is on level, the base current IB2 of the transistor 02 becomes positive depending on the second drive signal level and the resistance value of the resistor (R4) as shown in FIG. 2(h). When the forward bias current of the maximum current element Bm becomes, the transistor (A) turns on, and the second drive signal is reversed from the on level to the off level, the base current IB2 becomes a reverse bias current and changes into an almost triangular wave shape. , second
The negative maximum current after period TX2 from the fall of the gate signal -
Bm and returns to 0 after period TD22,
At this time, the reverse bias current is set based on the maximum current element Bm, the level of the second drive signal, and the resistance value of the resistor (R4). Detection level-Bx is shown.

Further, since the collector current Ic2 of the transistor θ changes in accordance with the change in the base current IJ]2, the delay period corresponding to the delay periods Ton and Tof in FIG. 5(C) also changes based on the base current IB2.

Therefore, when the base current IB2 of the transistor 0 becomes a reverse bias current, the light emitting diode (25a) is forward biased, and the base current IB2 of the light emitting diode (25a) becomes a reverse bias current.
A forward bias current proportional to 2 flows, and a reverse bias current exceeds the detection level -Bx, almost reaching the negative maximum current -Bm.
During the period TD22 close to , the light emitting diode (25&)
lights up.

That is, after the reverse bias current increases to the detection level -Bx or higher with a delay of TD22 from the fall of the base current IB2, the reverse bias current decreases to the detection level -Bx via the negative maximum current -Bm. During period TD22, the light emitting diode (25a) lights up.

When the light emitting diode (25a) is turned on, the phototransistor (25b) is turned on, and the input terminal (γ) of the AND gate 051 is turned on during the period TD, as shown in FIG. 2(i).
During the period TD22, the first drive signal is cut off and the transistor 0η is kept off.
I can do it.

Therefore, the first gate signal outputted from the AND gate Q51 to the amplifier 0■ has a waveform as shown in FIG. 2(j) compared to the waveform of FIG. 2(C) based on the reference pulse signal and the delayed signal. , the waveform becomes such that the falling edge is delayed by approximately the period TD22, and as a result, the first drive signal also changes at the timing shown in FIG.

In the above embodiment, an analog OR delay circuit is used to drive the first switching transistors 0η and α.
．． While forming the second drive signal, the photocoupler (2
3+, (25+ monitors the reverse bias current of transistors 0η and α until the reverse bias current of transistor 0υ decreases below the detection level -Bx.

In other words, the supply of the second drive signal to the transistor 0 is cut off until the transistor 01) is completely turned off, and the supply of the second drive signal to the transistor 0 is cut off until the transistor 01) is completely turned off, and until the reverse bias current of the transistor Since the supply of the first drive signal to the transistor 0υ is cut off until the transistor 0υ is completely turned off, if the simultaneous off-level period formed by the OR delay circuit is at least longer than the period TD22°TDI+, the first drive signal ．． The second drive signal is
The transistor (1υ) must be set up to ensure the minimum necessary simultaneous off-level period.

θ4 is fully supplied to each of them, and as a result, the transistor (1
1), O, and 2) are reliably prevented from being short-circuited due to simultaneous ON, and a desired inverter output waveform can be obtained.

In the above embodiments, the switching elements are transistors (]]), (la), but the present invention can of course be applied to cases where the switching elements are formed of various elements such as gate turn-off thyristors.

〔Effect of the invention〕

Therefore, according to the inverter driving method of the present invention, while the reverse bias current of one switching element and the other switching element exceeds a certain level, the switching element of the other one.

the second to one switching element. By blocking each of the first drive signals, it is possible to reliably prevent both switching elements from being turned on simultaneously.

[Brief explanation of drawings]

FIG. 1 is a wiring diagram of one embodiment of the inverter driving method of the present invention, FIGS. 2(a) to (i) are waveform diagrams for explaining the operation of FIG. 1, and FIGS. 3 and 4 are A wiring diagram of a conventional inverter driving method, FIGS. 5(a) to 5(d) are shown in FIG. 3. 5 is a timing chart for explaining the operation of FIG. 4. FIG. Oυ, a...transistor, ai, as...
AND gate, 0s, (a)...amplifier, 131,
(25+...Photocoupler.

Claims (1)

[Claims] (1) In an inverter driving method, two switching elements connected in series between both ends of a DC power supply are driven to switch in a complementary manner, and an inverter output having a pulse waveform is generated at the connection point between the two switching elements. forming first and second drive signals that change between on level and off level with a period in which they are simultaneously off level, and supplying both of the drive signals to control terminals of both of the switching elements, respectively; The period during which the reverse bias current generated in the control terminals of both switching elements at the time of OFF change exceeds a certain level is detected, and while the reverse bias current of one switching element exceeds the certain level, the period when the reverse bias current of the other switching element exceeds the certain level is detected. the second to the switching element;
blocking the supply of the drive signal, and blocking the supply of the first drive signal to the one switching element while the reverse bias current of the other switching element exceeds the certain level; A method for driving an inverter, comprising: performing switching driving with a simultaneous off period set by the level of the reverse bias current.