JPS5842452B2 - Loss of Russia - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital control circuit that digitally calculates camera exposure conditions, and more particularly to a circuit that calculates shutter time and aperture control data at high speed.

In general, the shutter time T is information on the amount of light, and if F is information on the sensitivity of a photoreceptor such as a film, such as ASA (this will be explained below as an example), and information on the aperture, it is given by the following equation.

Note that K is a constant. T=K・(1/L)・(1/AS
A)・F This formula is calculated by multiplying the information on the reciprocal of the light amount (1/L), the reciprocal of the film sensitivity information (1/ASA), and the aperture information F (if the numerical aperture is A, then F=A2). This shows that an appropriate shutter time can be obtained.

Calculation of this shutter time has conventionally been performed using an analog circuit.

However, since the information ratio of the amount of light covers a wide range of 10 to the 6th power or more, each amount of information is compressed logarithmically, multiplication is replaced with addition, and the result is expanded logarithmically.

However, this conventional circuit is extremely troublesome to adjust, and requires stricter requirements regarding accuracy and variation in component characteristics.

If this is not done, errors due to voltage fluctuations and temperature changes will become quite large and will go beyond the allowable error range.

On the other hand, if the circuit is configured digitally, it can be controlled with high precision without imposing strict requirements on the semiconductor components, and can be expected to have great advantages such as much easier adjustment and easier digital display. The problem is that it takes a long time.

This problem will be explained specifically.

Consider a series in which one stage of aperture information F and film sensitivity information ASA is further subdivided into 1/3.

In these numerical sequences, in the case of aperture information F, start from the minimum value, and in the case of film sensitivity information ASA, start from the maximum value to obtain the n1th and n2nd values F (nl) and ASA-1 (n2 ) are expressed in the form, assuming that their initial values are F(0) and ASA-1(0).

The formula for calculating the shutter time is as follows.

T=(K'・(1/L)) ・(2"/3)n"+n2
Here, K is a constant of -F(0)·ASA-1(0).

Here, the shutter time T is converted into a function of the light amount information (1/L,) and O or positive integers nl and n2.

Therefore, it can be seen from the equation that the shutter time can be obtained by calculating a constant of 2 to the 1/3 power for the light amount information.

Generally, multiplication is accomplished by performing repeated additions.

Therefore, for example, if the constant 2 to the 1/3 power is approximated in 3 lines and calculated as 1.26, at least 1 + 2 +
6=9 word times are required, and if this multiplication is repeated nl+n times, the calculation time will be longer than 9·(nl+n2) word times.

In the case of 3-digit arithmetic, conservatively speaking, 7 digit times are required for one word, so the calculation time is 9.(nl
It takes 10n2)·7·4=252(nl+n2) bit times.

For example, if the constant 2 to the 1/3 power is approximated by 2 digits and calculated as 1.3, one multiplication requires at least 1+3=4 word time, and nl+n2 multiplications requires 4・(nl+n2).
Word time is a minimum required.

In the case of 2-digit arithmetic, even conservatively, 5 digit times are required for 1 word, so the calculation time is 4・(
n1+n2)・5・4=80・(nl+n2) bit・
It takes a minimum of time.

On the other hand, when operating a still camera, there is a demand that the time taken by the camera operator to actually start operating the shutter when attempting to photograph a subject should be shorter.

Normally, the conditions for exposure must be determined within about 10 m5 (shutter stroke time) after the shutter button is pressed.

That is, if photometry and calculation results based on the photometry are not obtained within this approximately 10 m5, the camera function will be impaired.

From this point of view, we will calculate and see how much the clock frequency should be in order to obtain a calculation result during this period with normal calculations.

The setting range for aperture and film sensitivity is nl+n2, which is 40.
The above is generally necessary, for example, F number 1.4 to 16
corresponds to n 1 = 24, and n
2 = 18, which corresponds to a total range of 42 steps.

In the case of nl+n2 and 40 steps, the calculation time requires 252×40=10080 bit times or more for 3-digit approximation, and 80×40=3200 bit times or more for 2-digit approximation.

Therefore, the calculation clock frequency must be at least 1.0 MHz for three-digit approximation, and at least 320 KHz for two-digit approximation.

However, in reality, each constant calculation requires time for truncation or rounding, digit alignment, and time for data movement in preparation for the next constant calculation, and when this is taken into account, at least 2 ( nl ten n2) word
I have to help out the time.

In this case, 440 word times are required for 3-digit approximation calculation,
The calculation clock frequency is 1.2 MHz or higher.

Furthermore, 2-digit approximation calculation requires 240 word time and the calculation clock frequency is 480 KHz or more.

This frequency is LSI (Large 5caleI
Even if it is configured with complementary MO8) transistors, the frequency is such that a special high-speed design is required to make the entire circuit operate normally.

Even if it is possible to operate at a high frequency, it is disadvantageous in terms of cost.

When a constant calculation is performed using such a known addition method, errors in the constant are accumulated each time the calculation is performed.

The correct value of 2 to the 1/3 power is 1.259'21, which is 1.
In the case of 26, the error itself is +0.00627%, in the case of 40 steps, the cumulative error is +0.25%, and in the case of 1, 3, the error itself is +3.18%, and 4
The cumulative error in the case of 0 steps is +127%.

The cumulative error of +127% in the case of this two-digit approximation is so large that it completely defeats the purpose of digitizing it.

As described above, the three-digit approximation calculation method has sufficient settlement accuracy, but has a drawback in high speed.

Although the two-digit approximation calculation method has no problem in terms of high speed, the calculation error (or constant error) becomes too large.

Furthermore, the addition method requires at least two registers: one to store the operand and the other to store the result of the operation, and the number of digits for each is smaller than the number of digits for the multiplier + the number of digits for the multiplicand (both In addition, a constant storage register or a counter circuit that generates addition pulses a number of times corresponding to the constant and a complicated control circuit are also required.

The present invention was made in order to solve the above-mentioned problems in digital calculation, and it is possible to accurately calculate data for controlling the exposure mechanism of a camera from information given within a limited short time. It is an object of the present invention to provide an improved data processing circuit.

In order to achieve the above object, the circuit according to the present invention calculates the sum (nl+n2) of the aperture information F and the film sensitivity information ASA.
Immediately after reading the light amount information, ((nl+n2)/
3) Input (() represents O or an integer with the decimal point rounded down) calculation pulses with a duty of -50% of the word time width as calculation pulses divided by 3, and the pulse Execute the double calculation, input the fractional information from another terminal at the same time as the above information pulse, insert the pulse for the correction calculation of the fraction between the double calculation pulses, and the correction calculation is also the double calculation. By approximating , the shutter time can be calculated at high speed and with sufficient accuracy.

The length of the shift register used is such that only one shift register is sufficient for the number of digits of the desired product.

The noteworthy point in the circuit according to the present invention is that 1/2
The third power constant calculation is performed by repeating only the doubling operation, and the correction operation is performed between the regular doubling operations.

With such a configuration, the object of the present invention is completely achieved.

A circuit for digitally calculating data for controlling the exposure mechanism according to the present invention calculates (n
/3) (() represents the integer part) normal pulse and fraction n
a circuit for generating a fractional signal of -3 (n/3), and a means for generating correction calculation pulses having a different phase from the normal pulse, 7 when the fractional signal is 1 and 4 when the fractional signal is 2. ,
an OR gate that receives the normal pulse and the correction calculation pulse; an exponential circuit that generates an exponential correction signal that indicates 10-2 and 10-1 when the correction calculation pulse is 7 and 4, respectively; Light amount information (K/L)
(where K is a constant), and the light amount information (K/L) stored in the storage means is obtained from the logic gate based on the output of the OR gate and the index correction signal from the exponential circuit. The number of times corresponding to the number of pulses
Repeat the doubling operation, and if the fractional signal above indicates O, then (K/L)・2(n/3); if the fractional signal indicates 1, then (K/L)・2[n/”:)+7 .10-2 If the fractional signal indicates 2, (K/L) -2Cn/3)+7. The aperture control information or the shutter time information is obtained from the arithmetic circuit by inserting it between the calculations based on the calculation circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in more detail below with reference to drawings showing embodiments of the present invention.

FIG. 1 shows an example of a circuit configuration for generating double calculation pulses based on external setting information of aperture and film sensitivity.

Mazu F. The ASA information n setting circuit 1 inputs a (11/3) information signal and a fraction n-3·(n/3) information signal to input terminals 2 and 3, respectively, according to the setting value n.

A calculation start signal is input to the input terminal 14, and this signal causes the (n/3) pulse generation circuit 4 and the correction pulse generation circuit 5 to be activated.
and starts.

On the other hand, an arithmetic synchronization pulse is input to input terminal 6, and the 3-bit
The signal is input to ring counter 7.

This arithmetic synchronization pulse is generated all the time because the time it takes for the solute to travel for one hour, fJ1, is 19 hours.

Pulses of one word time width are generated alternately from the output terminals 8, 9, and 10, and do not overlap with each other.

[n/3] pulses from the output terminal 10 are connected to the pulse generating circuit 4, and only [n/3] pulses are generated from the output terminal 15 and input to the OR-gate 11.

- The pulses from the output terminal 9 are connected to the correction pulse generation circuit 5, and the pulses are generated from the output terminal 16 in a number corresponding to the fractional signal.

This pulse output 16 is input to the OR-gate 11, and the 2
It becomes a multiplication pulse and output terminal 1 along with pulse output 15.
Appears in 2.

Pulse outputs 15 and 16, which are synchronized in timing with pulse outputs 9 and 10, never overlap.

Although no calculation pulse is generated at the timing of pulse output 8, it is possible to round down, round down, round down to 5, etc. at this timing.

In other words, the order is to execute the doubling operation twice in a row and rounding once, but since the doubling operation is performed twice, that is, multiplied by 4, only a carry of one digit can occur. By performing rounding at the next timing, the arithmetic register can be made to have the required minimum number of digits.

For example, if you read the light amount data into the calculation register as 2 digits, detect 250 or more where a carry occurs in the next quadruple calculation, and perform rounding to the nearest 5, the calculation register will read the data 3 with a rounding error of less than 2%. It only takes a few digits※※.

Of course, it goes without saying that increasing the number of digits in the arithmetic register will improve accuracy.

Signal waveforms at input terminal 6 and output terminals 8, 9, 10, and 12 are shown in FIG.

Here, the calculation start signal input to the input terminal 14 needs to be a signal synchronized with the calculation synchronization pulse, which is the output pulse 15.
This is natural considering that 16 and 16 must be pulsed completely with a one-word time width.

Note that the doubling operation is completed in one word time, as will be described later.

The number of correction pulses is determined as follows.

In other words, the fraction 2 to the 1/3 power (true value 1.259921) is 2 to the 7th power = 128 and 2 to the 2/3 power (true value 1.587)
401) can be approximated by 2 to the 4th power = 16, and for this reason, if the fraction n-3 (n/3) is 0, it is 0.
If the fraction is 1, 7 correction calculation pulses are generated, and if the fraction is 2, 4 correction calculation pulses are generated.

In this case, as a correction for the exponent, the fraction n −3・(n/3)=
A correction of 10-2 is required for a fraction of 1, and a correction of 10-1 is required for a fraction of 2. Therefore, from the exponential correction pulse output 13, for example, O for a fraction of 1, 1 for a fraction of 2, and 2 for a fraction of O. It is also possible to output several carry pulses to align the exponents.

After all, in the case of F, ASA information n, the following calculation is performed for the light amount information (K'/L): (n = 0 or a positive integer, (n/3, 1 represents O or an integer rounded down to the decimal point) will be done.

As can be seen from this, the errors in the constant are never accumulated, and no matter how many n there are, there is only an error in the constant itself.

That is, for a fraction 1 (i.e. n = 3N+1, N is O or an integer), the error for the constant 2 to the 1/3 power of 27 +1.6%, and a fraction 2 (i.e. n = 3 N+2)
For 24, the error for the constant 2 to the 2/3 power +0.
For an 8% fraction O (that is, n = 3 N ), the error is O.

These are within a practically acceptable error range for cameras.

FIG. 3 shows a more specific example of a circuit configuration in which a double operation pulse is created using external setting information of F and ASA.

The first setting device 21 uses a resistor selection switch or the like to set the output signal of the comparator 17 to high or high according to the calculation start signal.
It is set so that the time width from when it reaches the level to when it falls to the low level corresponds to (n/3).

In this case, if T is the time during which the comparator output 25 is at high level, and τ is one word time, then T and (
n/3) is (n/3)3T<T<((n+3:)
+1)・3τ, that is, T/ 3 r −1< (n/
3]<T/3τ.

Here, let's find the stability with respect to the oscillation frequency.

The l word time τ is naturally inversely proportional to the calculation clock frequency fc.

Therefore, by setting A as a constant and setting τ=A/fc, we also set (n
If the comparator output width corresponding to /3,1=N is TN, then TN-(N+α)・3τ, (o<α<1), so if N is sufficiently large, N=TN/3τ−α2TN/3τ
becomes.

Here, since the comparator output width is set independent of the calculation clock frequency, TN can be considered a constant that is independent of fc.

Therefore, the change in set pulse △N due to frequency fluctuation △f
can be expressed as ΔN=TN·Δf/3A.

On the other hand, if n is directly set in the comparator output and fractional information is also included, the relationship between T and n is TN-(
n+α)・τ, and in exactly the same way, the frequency fluctuation △f
The change in the setting pulse ΔN is ΔN=Tn・△f/A
It can be expressed as

Therefore, it can be seen that frequency stability is improved three times by separating the fraction information and (n/3) information.

This comparator output rises in synchronization with the calculation synchronization pulse by the latch circuit 31.

This output is synchronized with the arithmetic synchronization pulse by the latch circuit 18, enters the gate 22, and is input to the 3-bit ring counter 1.
The double calculation pulse from the output terminal 26 of No. 6 is sent to the calculation circuit by the corresponding number through the OR gate 24 as a complete one word time width pulse.

Since the flip-flop 19 performs a binary operation in which it is inverted at the rising edge of the input pulse, the gate 23 is opened at the same time as the gate 22 is opened, and remains open thereafter.

The fraction outputs 28, 29, and 30 are set, for example, so that only the output corresponding to the fraction becomes a high level and the others become a low level.

Of course, it is also possible to provide only two fraction outputs and use a binary signal to correspond to three fractions.

These output signals are connected to the program input of the 3-bit programmable counter 20, and the signal from the output terminal 27 of the 3-bit ring counter 16, which is input through the gate 23, is connected to the program input of the 3-bit programmable counter 20. , fraction 1
For fractions of 2, only 4 are passed.

This output is sent to the arithmetic circuit through the gate 24 as a double arithmetic pulse.

Further, corresponding to the fraction output, 0 pulses are generated for a fraction O, 2 pulses are generated for a fraction 1, and only 1 pulse is generated for a fraction 2 as exponent position carry down pulses.

Since this programmable counter is a well-known one that can be easily realized, details thereof will be omitted.

FIG. 4 shows the basic configuration of the doubling operation circuit.

The shift register 31 has a length of 4 bits and corresponds to one digit.

Shift register 32 actually has the digit length necessary for the operation.

Light amount information is input to the input terminal 43 as serial data, and when a read control pulse from the input terminal 44 is input, the light amount information is read into the shift register.

Gates 39, 40, 41, and 42 perform switching between reading light amount information and storing information.

A doubling operation pulse is input to the input terminal 34, and the gates 35, 36, 37, and 3B switch between doubling operation and storing the operation result.

In other words, while the calculation pulse is input to the input terminal 34, the shift register 32 has B, C1D (Binary
(Code Decimal) The addition result from the full adder circuit 33 is read, and while there is no calculation pulse, the data from the shift register 31 is read. You will remember it.

Here, the doubling operation converts the contents of the shift register 32 into B,
C, D full adder circuit 3202 connected to human power a and b at the same time,
This is done by returning the result of the addition to the original shift register, which now has twice the value of the previous data.

Therefore, by repeating this operation M times, an operation result of 2M-X can be obtained, assuming that the initial contents of the shift register are X.

In this way, the operation of 2 to the M power of X requires only passing the contents of the register M times, that is, M word time, and requires only one shift register, making the circuit configuration extremely simple.

Let's roughly estimate the calculation time here. If F+ASA information contains up to 40 steps, n=40, Cn/3)=1
It becomes 3.

Since the fraction is 1, the correction calculation is performed 7 times, but since these are inserted between the regular double calculation pulses, the calculation completion time is 3X (n/3) = 3X13 = 39 words.
It's time.

If the fraction is 1, a minimum of 3 x 7 = 21 word times is required, if the fraction is 2, a minimum of 3 x 4 = 12 word times is required, and if the fraction is O, a correction pulse is not required, so n word times are required. It turns out.

Since the maximum constant error is +1.6%, it is not very meaningful to calculate with more than 4 digits, so if the effective digits of the calculation are 3, then 1
Word time is 4 digit time.

Therefore, the computation time is only 39×4×4=624 bit times.

In terms of calculation clock frequency, this is 62.4)G(z
If this is the case, the calculation will be completed within 10 ms.

This is a frequency that can be sufficiently operated using a P-channel MO8, and if a complementary MO8 is used, a special high-speed design is of course not required, and the integrated circuit can fully demonstrate the characteristics of low current consumption and low voltage operation. This frequency is suitable for

As described above, according to the present invention, calculation is performed by repeating only the doubling operation to calculate the shutter time, so only one shift register is required for calculation, and the control circuit is also significantly simplified. The number of circuit elements is greatly reduced.

Since the calculation time is also significantly reduced, it is possible to realize integrated circuits of digital systems at low cost.

Further, since errors caused by calculations are not accumulated depending on the number of calculations, highly accurate calculation results can be obtained.

Furthermore, displaying calculation results and moving data to the exposure control counter can be easily realized, so a fully automatic exposure control system can be easily configured.A block diagram is shown as an example of an aperture-priority automatic exposure control system. is shown in Figure 5.

Furthermore, the present invention provides information on aperture and film sensitivity n [n
/3] and the fraction n-3・(n/3).
3) Since it is possible to insert information between double operations based on information, the operation speed is dramatically improved.

When integrated into an integrated circuit, this can be used as a fractional information input terminal.
This more than makes up for the drawback of requiring an extra book or three.

Also, the number of steps of n is practically n / 3, which is 1
/3, so the external setting circuit becomes simple. Moreover, when creating a signal with a time width proportional to the number of steps and generating (n/3) pulses as shown in Figure 3, the above-mentioned As shown, the frequency stability is improved by a factor of three.

Also, completely digitally, using a counter (
Even when setting n/3), the effect is significant because the counter requires one or two steps less than when setting n.

Note that the constant Kl mentioned at the beginning can be easily included in the light amount information by adjusting the conversion coefficient during photometry to convert the amount of light into an amount of electricity.

Therefore, it goes without saying that calculation of the shutter time does not depend on the absolute values of the aperture and film sensitivity, but rather calculates the relative value from the reference value.

As a final note, I have explained in detail above in relation to the so-called 5 aperture priority automatic exposure control camera, in which the aperture is set in advance and the shutter time is calculated and controlled. The invention can also be applied to so-called shutter-priority automatic exposure control cameras in which the aperture is controlled according to the amount of light.

In other words, the aperture information F is They are related by the following formula.

On the other hand, the shutter time is generally set in a double series, so if you set this to the maximum value of the setting range as step O and start from there, it is T-1 (ns) - T' (0) ・2
It is expressed as n3-T'(0)-(2"/")"ns.

Therefore, the aperture control data is F-1-Kl・(1/L)・(21/3)n2+3n3, and the [n/3] information is (n2/3, l+n3,
Fractional information is ASA information n2 only, fractional information n33 (n2
/3) After that, the aperture control data 1/F can be obtained using the same method as for calculating the shutter time.

Here /-T-'(0')-ASA-1(0), n
s is 0 or a positive integer.

Various modifications can be made to the embodiment circuit described in detail above within the scope of the present invention, and the scope of the present invention extends to all of the claims.

[Brief explanation of drawings]

1, 3, and 4 are configuration diagrams showing embodiments of the present invention, in which FIG. 1 is a block diagram of an input information conversion circuit, and FIG. 3 is a more specific example of the circuit configuration, FIG. 4 is a circuit configuration diagram for explaining the doubling calculation circuit, FIG. 2 shows the basic timing relationship, and FIG. 5 is a block diagram of the entire aperture priority automatic exposure system. 1...F, ASA information n setting circuit, 4...
... (n/3) pulse generation circuit, 5 ... correction pulse generation circuit, 7 ... 3 bit ring counter, 11 ... OR gate, 16 ... ...3
Bit ring counter, 11...Comparator, 18...Latch circuit, 19...Flip-flop, 20...3-bit programmable counter, 21... ...n setting device, 31, 3
2...Shift register, 33...BC
D full adder circuit.

Claims (1)

[Claims] 1. For the sum n of the index of shutter hour information or the index of aperture control information and the index of photoreceptor sensitivity information, (n/3)(
D represents the integer part) and the fraction n-3 (n/
3) a circuit for generating the fractional signal; means for generating seven correction calculation pulses when the fractional signal is 1 and four when the fractional signal is 2; When the correction calculation pulse is 7 and 4, the OR gate receives the correction calculation pulse and the correction calculation pulse is 10-2, respectively.
and 10-1, a storage means for storing the measured light amount information (K/L) (where K is a constant), and the output of the above-mentioned OR gate and the index circuit. Based on the exponent correction signal, the light amount information (K/L) stored in the storage means is repeatedly doubled a number of times corresponding to the number of pulses obtained from the logic gate, and when the fractional signal indicates 0, (K/L) - 2 (n/3), if the fractional signal indicates 1, (K/L)' 2 (n/3) +7 ・1
0-2 When the terminal v signal indicates 2, the clearing circuit performs the calculation (K/L)-z(n/3)+'-to-1, and performs the calculation based on the correction calculation pulse as described above. A circuit for digitally calculating data for controlling an exposure mechanism, characterized in that the circuit is inserted between calculations based on regular pulses, and obtains aperture control information or shutter time information from the calculation circuit.