SU771672A1 - Device for computing logarithmic functions - Google Patents

Description

The invention relates to computing, and in particular to devices · for reproducing and calculating logarithmic functions by the method of piecewise linear approximation.

The device is known for the functional conversion of information signals in the form of unitary codes [1], containing a controlled divider, a counter of sections, a memory block and its control circuit. Such devices, although they provide a piecewise linear approximation with a fixed step in the output variable, however, they have a significant drawback - a tabular definition of the function, which, with increased accuracy requirements, leads to an increase in instrument costs and a decrease in reliability.

The closest in technical essence to the proposed one is a device for reproducing logarithmic functions - an approximating function [21, containing a pulse generator, a key, an argument counter, a result counter, a shift register, the first and second binary multipliers, each of which consists of a counter, a decoder and ele2 OR, whose inputs are connected to the outputs of the decoder, the inputs of which are connected to the outputs of the counter, and the output of the pulse generator is connected to the information input of the key, allowing the input to orogo is an input device for prohibiting the input connected to the output of the counter argument, and an output switch coupled to the inputs of counters of the first and second binary multipliers.

The input of the decoder of the first binary multiplier is connected to the output of the shift register, the input of which is connected to the high-order output of the counter of the second binary multiplier, the output of the OR element of the first binary multiplier is connected to the input of the argument counter.

The disadvantage of this device is the low accuracy due to the fact that the approximating function has a stepped shape.

The purpose of the invention is improving accuracy.

This goal is achieved by the fact that in a device containing a pulse generator, a key, an argument counter, a result counter, a shift register, the first and second binary multipliers, each of which consists of a counter, a decoder and an OR element, the inputs of which are connected to the outputs of the decoder having inputs connected to the outputs of the counter, wherein the pulse generator output is connected to an information input key enabling input kotoro- ₅ is an input device of prohibiting input connected to the output of the argument counter, and output to the beam is connected to the inputs of the counters of the first and second binary multipliers, the input of the decoder of the first binary multiplier 10 is connected to the output of the shift register, the input of which is connected to the output of the high order | counter of the second binary multiplier, output! The OR element of the first binary multiplier is connected to the input of the argument counter; in addition, a third binary multiplier is introduced, which also consists of a counter, a decoder and an OR element, and a correction unit, including a counter, a decoder, a memory block, a trigger, and an adder. In this case, the counter output of the second 20 binary multiplier is connected to the input of the counter of the correction unit, the output of which through the trigger is connected to the first input of the adder. The outputs of the bits of the counter of the correction unit through the decoder of the correction unit and the memory unit 25 are connected to the input of the decoder of the third binary multiplier, the output of the OR element of which is connected to the second input of the adder, the third input of the adder is connected to the information OUTPUT of the second Binary multiplier, and the output of the adder, connected to the input of the result counter.

The structural diagram of the proposed device is shown in the drawing.

The device contains a pulse generator 1; ₃₅ key 2; counter 3 arguments; first binary multiplier 4; shift register 5; second binary multiplier 6; counter 7 result; block 8 correction; the third binary multiplier 9. The correction unit 8 includes ₄₀ counter 10, a decoder 11, a memory unit 12, a trigger 13, and an adder 14 (pulses). Binary ^ multipliers consist of a counter 15, a decoder 16, an OR element 17.

The proposed device operates as follows ₄₅ .

The conversion factor of the counter 3 argument is set equal to the specified value of the argument, a unit is written into the shift register 5, and the trigger 13 is set to a state ₅₀ in which the pulse adder 14 is fixed in the addition mode. On the control inputs of the binary multiplier 9 is installed! code of the first angular coefficient of the correction function. ,

When a start signal is supplied to key 2, it is unlocked and the counting pulses from the output of generator 1 are fed to the input of binary multipliers 4, 6, and 9. The device processes the approximating function in the first section. When working out each correction section, one pulse is supplied to the input of the counter 10, which leads to switching of the codes of angular coefficients at the control inputs of the binary multiplier 9, When working out the first half of the first approximation section and, accordingly, the first half of the correction sections, the correcting pulses received at the input of the adder 14 pulses are summed with incremental pulses. The corrected increment of the function is integrated in the counter 7 of the result. At the moment of completion of the first half of the correction sections, which corresponds to the passage of the maximum error point, a pulse is received at the input of the trigger 13 from the counter 10, as a result of which the trigger 13 is transferred and sets the pulse adder 14 to the subtraction mode. At the moment of completion of the first approximation section and, accordingly, of the second half of the correction sections, the counter 10 and trigger 13 return to their initial state, one is input to the shift register 5, and the device processes the second approximation section.

To fulfill the approximation condition, Ду =. 1p2 at the control inputs of the binary multiplier 6, the code of the number N = 1p2 = 0.693 is set up to the decimal point, due to which, when overflowing, the output of the binary multiplier 6 receives the number of pulses equal to

Ду = 1п2 = 693 ..., and the input to the shift register is one, which means the end of the development of the next approximation section with the step Ду = In2 and provides the required change in the angular coefficient by half in each subsequent section. It can be seen that when the result of the next number of ”pulses Du arrives at the counter input число, the number of pulses arriving at the input of counter 3 of the argument doubles.

A comparison of the proposed and known devices shows that the proposed one is characterized by increased (up to a predetermined value) calculation accuracy, which improves operational characteristics and allows its use in processing information signals with an accuracy of hundredths of a percent.

Claims (2)

1. Brago B.N. Methods and devices for digital information conversion. M., Nedra, 1976, p. 58, rice; 25 2. Melnikov A. A. and others. Processing of frequency and time pulse signals. M., Energie, 1976, p. 96, fig. 8 (prototype).