JPS5838612Y2 - Semiconductor element mounting equipment for three-dimensional planar circuits - Google Patents
Semiconductor element mounting equipment for three-dimensional planar circuitsInfo
- Publication number
- JPS5838612Y2 JPS5838612Y2 JP9521378U JP9521378U JPS5838612Y2 JP S5838612 Y2 JPS5838612 Y2 JP S5838612Y2 JP 9521378 U JP9521378 U JP 9521378U JP 9521378 U JP9521378 U JP 9521378U JP S5838612 Y2 JPS5838612 Y2 JP S5838612Y2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- dimensional planar
- mounting body
- planar circuit
- lead structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】
この考案は、ビームリード構造の半導体素子を、取付体
を介して立体平面回路に容易に取付けられ、るようにし
、立体平面回路のマイクロ波特性を向上させるようにし
た立体平面回路の半導体素子取付装置に関する。[Detailed description of the invention] This invention allows a semiconductor element with a beam lead structure to be easily attached to a three-dimensional planar circuit via a mounting body, and improves the microwave characteristics of the three-dimensional planar circuit. The present invention relates to a semiconductor element mounting device for a three-dimensional planar circuit.
従来、立体Y面回路に周波数変換用の半導体素子を取付
ける装置は、第日図ないし第4図に示すような構成にな
っている。Conventionally, an apparatus for attaching a semiconductor element for frequency conversion to a three-dimensional Y-plane circuit has a configuration as shown in FIGS.
すなわち、それらの図において、1.2は導波管素体で
あり、洞導波管素体1,2を重合して方形導波管が構成
される。That is, in those figures, 1.2 is a waveguide element, and a rectangular waveguide is constructed by superposing the sinusoidal waveguide elements 1 and 2.
3は洞導波管素体1.2にそれぞれ8個ずつ形成された
螺孔であり、洞導波管素体1,2を重合し、各螺孔3に
ねじ(図示せず)を螺合することにより洞導波管素体1
,2が固着される。Reference numeral 3 designates eight screw holes formed in each of the sinusoidal waveguide bodies 1 and 2. The sinusoidal waveguide bodies 1 and 2 are overlapped, and a screw (not shown) is inserted into each screw hole 3. By combining the sinusoidal waveguide body 1
, 2 are fixed.
4は洞導波管素体1,2の各上部にそれぞれ形成された
切欠部であり、後述のフィルタが取付りられる。Reference numeral 4 denotes notches formed in the upper portions of each of the sinusoidal waveguide bodies 1 and 2, into which filters to be described later are attached.
5はマイクロ波フィルタ等が構成された導体薄板であり
、洞導波管素体f、2の間に挟着されている。Reference numeral 5 denotes a thin conductor plate on which a microwave filter and the like are constructed, and is sandwiched between the sinusoidal waveguide body f and 2.
6は導体薄板5に透設された位置決め用の4個の孔であ
り、各社6を洞導波管素体1,2の各螺孔3に重合する
ことにより、導体薄板5が位置決めされる。Reference numeral 6 designates four holes for positioning that are transparently provided in the conductor thin plate 5, and the conductor thin plate 5 is positioned by overlapping each hole 6 with each screw hole 3 of the sinusoidal waveguide element bodies 1 and 2. .
7はポリエチレン等の絶縁体8上に銅等によりフィルタ
回路用の導体パターン9が形成されたフィルタであり、
洞導波管素体1,2の各切欠部4に嵌合されている。7 is a filter in which a conductor pattern 9 for a filter circuit is formed of copper or the like on an insulator 8 such as polyethylene;
It is fitted into each of the notches 4 of the hollow waveguide bodies 1 and 2.
Cは洞導波管素体]。2、導体薄板5およびフィルタ7
により構成された衆知の立体平面回路、IOは導体薄板
5とフィルタ7とを結合するパッケージ入りダイオード
等のパッケージ入り半導体素子、11は半導体素子IO
のペレツト等がパッケージされたパッケージ入り半導体
素子10のパンケージ本体、12は導体薄板5およびフ
ィルタ7の導体パターン9にそれぞれ半田付けにより接
続されたパンケージ入り半導体素子10の2本のリード
線である。C is a sinusoidal waveguide body]. 2. Conductor thin plate 5 and filter 7
IO is a packaged semiconductor element such as a packaged diode that connects a thin conductor plate 5 and a filter 7, and 11 is a semiconductor element IO.
12 are two lead wires of the packaged semiconductor device 10 connected to the thin conductor plate 5 and the conductor pattern 9 of the filter 7 by soldering, respectively.
したがって、周波数変換用として第2図に示すようなパ
ンケージ入り半導体素子10を、半田付けにより導体薄
板5むよびフィルター7に取付けている。Therefore, for frequency conversion, a pancaged semiconductor element 10 as shown in FIG. 2 is attached to the thin conductor plate 5 and the filter 7 by soldering.
しかし、高周波領域において使用した場合、パッケージ
入り半導体素子10のパッケージ本体11の浮遊容量、
リード線I2のインダクタンス等が立体平面回路Cのマ
イクロ波特性に悪影響を与えるという問題点がある。However, when used in a high frequency region, the stray capacitance of the package body 11 of the packaged semiconductor element 10,
There is a problem that the inductance of the lead wire I2 and the like adversely affect the microwave characteristics of the three-dimensional planar circuit C.
そこで、この悪影響を打消するために、パッケージ入り
半導体素子10自体の性能を向上させなければならず、
そのためには、製造工程にち゛いて高度な微細パターン
形成技術が要求される。Therefore, in order to counteract this negative effect, it is necessary to improve the performance of the packaged semiconductor element 10 itself.
For this purpose, advanced fine pattern forming technology is required in the manufacturing process.
また、ビームリード構造の半導体素子を用いて浮遊成分
を減少させることも考えられるが、ビームリード構造の
半導体素子は、非常に微小であるため、現在では主に混
成マイクロ波集積回路形成用素子として用いられ、導波
管に直接取付けることは困難である。It is also possible to reduce stray components by using semiconductor elements with a beam lead structure, but since semiconductor elements with a beam lead structure are extremely small, they are currently mainly used as elements for forming hybrid microwave integrated circuits. It is difficult to attach directly to a waveguide.
この考案は、前記従来の問題点に留意するとともに、ビ
ームリード構造の半導体素子の立体平面回路に取付けた
場合に、そのマイクロ波特性に悪影響を与えないと云う
利点に着目し、微小なビームリード構造の半導体素子を
立体平向回路に容易に取付けられるようにし/ともので
あり、つぎにこの考案を、その実施例を示した第5図以
下の図面とともに詳細に説明する。This idea was developed by taking into consideration the problems of the conventional technology and focusing on the advantage that when attached to a three-dimensional planar circuit of a semiconductor element with a beam lead structure, it does not adversely affect the microwave characteristics of the semiconductor element. This invention is intended to enable a semiconductor element having a lead structure to be easily attached to a three-dimensional planar circuit.This invention will now be described in detail with reference to FIG. 5 and subsequent drawings showing an embodiment thereof.
l実施例を示した第5図ないし第7図において、第1図
ち・よび第4図と同一記号は同一のものを示L−13は
絶縁体であり、例えばアル□す板を高さおよび幅がそれ
ぞれ0.5mmでかつ長さが1.4 rrvnの板状に
成形したものである。l In Figures 5 to 7 showing the embodiment, the same symbols as in Figures 1 and 4 indicate the same things. and a plate shape each having a width of 0.5 mm and a length of 1.4 rrvn.
γ4は絶縁体I3上にそれぞれ電気的に分離するよう形
成された2個の電極パターンであり、Au /N i
/c r iたばA u /N i / Ag −P
b等の材料により形成されている。γ4 is two electrode patterns formed on the insulator I3 so as to be electrically isolated from each other, and Au/N i
/c r i taba A u /N i /Ag -P
It is made of a material such as b.
15は絶縁体13と電極パターンI4とにより構成され
た後述のビームリード構造の半導体素子の取付体であり
、両電極パターン14がツレぞれ導体薄板5トよびフィ
ルタ7の導体パターン9に半田16付けにより電気的に
接続されるよう固着されている。Reference numeral 15 denotes a mounting body for a semiconductor element having a beam lead structure, which will be described later, which is composed of an insulator 13 and an electrode pattern I4. It is fixed so that it is electrically connected by attaching it.
I7ばGaAsミキサーダイオード等のビームリード構
造の半導体素子であり、半導体部I8と2本のリード線
19とにより構成され、両リード線I9が熱圧着ボンデ
ィングによりそれぞれ取付体15の両電極パターンI4
に接続されている。I7 is a semiconductor element with a beam lead structure such as a GaAs mixer diode, and is composed of a semiconductor part I8 and two lead wires 19, and both lead wires I9 are connected to both electrode patterns I4 of the mounting body 15 by thermocompression bonding.
It is connected to the.
つき゛に、前記実施例の取付は順序を説明する。Therefore, the installation order of the above embodiment will be explained below.
前述の第1図および第3図、第4図に示した立体平向回
路Cにむいて、−力の導波管素体口の螺孔3にねじを螺
入するとともに、螺孔3から導出されたねじに導体薄板
5の孔6を挿通して導体薄板5を一方の導波管素体]に
当てがい、つぎにフィルタ7を一力の導波管素体Iの切
欠部4に嵌合させる。Facing the three-dimensional planar circuit C shown in FIG. 1, FIG. 3, and FIG. Insert the lead-out screw into the hole 6 of the thin conductor plate 5 and apply the thin conductor plate 5 to one waveguide element, and then insert the filter 7 into the notch 4 of the waveguide element I. Make it fit.
−力、ビームリード構造の半導体素子11の両リード線
19を熱圧着法によりそれぞれ取付体15の両電極パタ
ーン14に電気的に接続するよう装着する。- Both lead wires 19 of the semiconductor element 11 having a beam lead structure are mounted so as to be electrically connected to both electrode patterns 14 of the mounting body 15 by thermocompression bonding.
この半導体素子17の取付けられた取付体15の両電極
パターン14の各端部を、導体薄板5むよびフィルタI
の導体パターン9に半田16付けする。Connect each end of both electrode patterns 14 of the mounting body 15 to which the semiconductor element 17 is attached to the thin conductor plate 5 and the filter I.
Solder 16 is attached to the conductor pattern 9.
そして、他力の導波管素体2を一方の導波管素体1に重
合するよう固着し、半導体素子17の立体平面回路Cへ
の取付けが完了する。Then, the external waveguide element 2 is fixed to one of the waveguide elements 1 so as to be superimposed, and the attachment of the semiconductor element 17 to the three-dimensional planar circuit C is completed.
すなわち、微小なビームリード構造の半導体素子17が
取付体15を介して容易に立体平面回路Cに取付けられ
る。That is, the semiconductor element 17 having a minute beam lead structure can be easily attached to the three-dimensional planar circuit C via the attachment body 15.
したがって、立体平向回路C内に従来の半導体素子]0
のようなパッケージ本体IIが挿入されないため、立体
平面回路Cのマイクロ派桐性が影響されることがない。Therefore, the conventional semiconductor element in the three-dimensional planar circuit C]0
Since the package main body II such as the one shown in FIG.
なお、取付体■5の絶縁体13が立体平面回路に挿入さ
れるが、実険の結果、120GH2においてり、OX
O,7X 3.5r+m+の取付体]5を用いた場合で
も電波伝搬特性の劣化が全くなかった。In addition, the insulator 13 of the mounting body 5 is inserted into the three-dimensional planar circuit, but as a result of practical safety, it is 120GH2, and the OX
There was no deterioration of the radio wave propagation characteristics at all even when using the mounting body of O,7X 3.5r+m+]5.
また、第8図および第9図のような構成にしてもよい。Alternatively, configurations such as those shown in FIGS. 8 and 9 may be used.
同謁において、第1図ないし第7図と同一記号は同一の
ものを示し、前記実施例と異なる点は、取付体15′を
、第9図に示すような構成にしたことである。In the same audience, the same symbols as in FIGS. 1 to 7 indicate the same things, and the difference from the previous embodiment is that the mounting body 15' is constructed as shown in FIG. 9.
すなわち、両電極パターン14′が絶縁体13から延設
された構成であり、電極パターンf 4’の材料として
は、Cu箔にAuめっきしたもの等を用いるとよい。That is, both electrode patterns 14' are configured to extend from the insulator 13, and the electrode pattern f4' is preferably made of a material such as Cu foil plated with Au.
したがって、前記実施例よりも両電極パターン14′の
導体薄板5ち−よびフィルタ7の導体パターン9への半
田16付けがさらに容易になる。Therefore, the soldering 16 of both electrode patterns 14' to the conductor thin plate 5 and the conductor pattern 9 of the filter 7 becomes easier than in the previous embodiment.
なお、取付体15.15’の形状は、前述の実施例に限
らず、立体平面回路Cへの取付けが容易でかつ寸法の小
さいものが望1しく、立体平面回路Cに応じて適宜成形
すればよく、例えば、第10図に示す取付体15″ の
ように、両電極パターン14# を絶縁体]3の一首か
ら側面にかけて形成した形状にすることもできる。Note that the shape of the mounting body 15, 15' is not limited to the above-mentioned embodiment, but it is preferable that it be easily attached to the three-dimensional planar circuit C and small in size, and may be shaped as appropriate depending on the three-dimensional planar circuit C. For example, both electrode patterns 14# may be formed to extend from one neck of the insulator 3 to a side surface, as in the case of a mounting body 15'' shown in FIG. 10, for example.
また、材料としては、絶縁体]3上に電極パターン14
.14’。In addition, as a material, an electrode pattern 14 on the insulator]3 is used.
.. 14'.
14″を強固に形成できるものであれば特に限定されな
い。There are no particular limitations on the material as long as the material can be firmly formed.
以上のように、この考案の立体平面回路の半導体素子取
付装置によると、絶縁体上に複数個の電極パターンを電
気的に分離して取付体を形成し、各電極パターンに、ミ
キサーダイオード等のビームリード構造の半導体素子を
接続し、取付体を、立体平面回路に電気的に接続して装
着することにより、ビームリード構造の半導体素子を取
付体を介して立体平面回路に容易に取付けることができ
、従来のパッケージ入り半導体素子に比し、ビームリー
ド構造の半導体素子の方が半導体素子としての特性がよ
く、かつパッケージを有しないから立体平面回路のマイ
クロ波射性に影響を与えず、立体平面回路のマイクロ波
特性が格段に向上する。As described above, according to the semiconductor device mounting device for a three-dimensional planar circuit of this invention, a mounting body is formed by electrically separating a plurality of electrode patterns on an insulator, and each electrode pattern is provided with a mixer diode, etc. By connecting the semiconductor element with the beam lead structure and electrically connecting and mounting the mounting body to the three-dimensional planar circuit, it is possible to easily attach the semiconductor element with the beam lead structure to the three-dimensional planar circuit via the mounting body. Compared to conventional packaged semiconductor devices, semiconductor devices with a beam lead structure have better characteristics as a semiconductor device, and because they do not have a package, they do not affect the microwave radiation of a three-dimensional planar circuit. The microwave characteristics of planar circuits are significantly improved.
捷た、ビームリード構造の半導体素子はパッケージが不
要で林から、パッケージ入り半導体素子に比べて安価と
なる。Semiconductor devices with a twisted, beam-lead structure do not require a package, making them cheaper than packaged semiconductor devices.
【図面の簡単な説明】
第1図ないし第4図は従来の立体平面回路の半導体素子
取付装置を示し、第■図は分解斜視図、第2図は半導体
素子の詳細な断面図、第3図は一部拡大図、第4図は第
3図のA−A′線断面図、第5図ないし第7図はこの考
案の立体平面回路の半導体素子取付装置のl実施例を示
し、第5図は要部断面図、第6図および第7図は第5図
のビームリード構造を半導体素子むよび取付体の拡大図
、第8図はこの考案の他の実施fE要部断面図、第9図
は第8図の取付体の′fJ、、7犬図、第10図は取付
体のさらに他の実施例の断面図である。
C・・・立体平面回路、■3・・・絶縁体、14.14
’。
■4″・・・電極パターン、15.15’、15”・・
・取付体、I7・・・ビームリード構造の半導体素子。[Brief Description of the Drawings] Figures 1 to 4 show a conventional semiconductor element mounting device for a three-dimensional planar circuit, Figure 2 is an exploded perspective view, Figure 2 is a detailed sectional view of the semiconductor element, and Figure 3 is a detailed sectional view of the semiconductor element. The figure is a partially enlarged view, FIG. 4 is a sectional view taken along the line A-A' in FIG. 5 is a sectional view of the main part, FIGS. 6 and 7 are enlarged views of the beam lead structure of FIG. 9 is a cross-sectional view of the mounting body shown in FIG. 8, and FIG. 10 is a sectional view of still another embodiment of the mounting body. C... Three-dimensional planar circuit, ■3... Insulator, 14.14
'. ■4"...electrode pattern, 15.15', 15"...
- Mounting body, I7... Semiconductor element with beam lead structure.
Claims (1)
付体を形成し、前記各電極パターンに、ミキサーダイオ
ード等のビームリード構造の半導体素子を接続し、前記
取付体を、立体平面回路に電気的に接続して装着した立
体平面回路の半導体素子取付装置。A mounting body is formed by electrically separating a plurality of electrode patterns on an insulator, a semiconductor element having a beam lead structure such as a mixer diode is connected to each of the electrode patterns, and the mounting body is formed into a three-dimensional planar circuit. Semiconductor element mounting equipment for three-dimensional planar circuits that are electrically connected to and mounted on.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9521378U JPS5838612Y2 (en) | 1978-07-10 | 1978-07-10 | Semiconductor element mounting equipment for three-dimensional planar circuits |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9521378U JPS5838612Y2 (en) | 1978-07-10 | 1978-07-10 | Semiconductor element mounting equipment for three-dimensional planar circuits |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5512647U JPS5512647U (en) | 1980-01-26 |
JPS5838612Y2 true JPS5838612Y2 (en) | 1983-09-01 |
Family
ID=29027946
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9521378U Expired JPS5838612Y2 (en) | 1978-07-10 | 1978-07-10 | Semiconductor element mounting equipment for three-dimensional planar circuits |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5838612Y2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57187003U (en) * | 1981-05-21 | 1982-11-27 |
-
1978
- 1978-07-10 JP JP9521378U patent/JPS5838612Y2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5512647U (en) | 1980-01-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6225146B1 (en) | Lead frame, method of manufacturing lead frame, semiconductor device and method of manufacturing semiconductor device | |
JPH07142669A (en) | Molded semiconductor device | |
JPH0740790B2 (en) | High power power module | |
JPS5838612Y2 (en) | Semiconductor element mounting equipment for three-dimensional planar circuits | |
JPH07321140A (en) | Semiconductor device | |
JPS62257759A (en) | Hybrid integrated circuit high voltage insulated amplifier package and manufacture of the same | |
JPS6250063B2 (en) | ||
JPS63299370A (en) | Semiconductor device for high-frequency | |
JPH05343610A (en) | Hybrid integrated circuit device | |
JPH0322915Y2 (en) | ||
JPS59112701A (en) | Microwave integrated circuit | |
JPH0817960A (en) | Qep structure semiconductor device | |
JPH0319416A (en) | Surface acoustic wave device | |
JPH04186667A (en) | Semiconductor device | |
JP4127589B2 (en) | High frequency semiconductor device package and high frequency semiconductor device | |
JP2604506B2 (en) | Container for semiconductor device | |
JPH02153557A (en) | Resin sealed type semiconductor device | |
JPH0719148Y2 (en) | Microwave circuit package | |
JPS6122344Y2 (en) | ||
JPS6348129Y2 (en) | ||
JPH05211279A (en) | Hybrid integrated circuit | |
JPH066512Y2 (en) | Integrated circuit package | |
JPH0746711B2 (en) | Chip carrier | |
JPH0451488Y2 (en) | ||
JPH0363315B2 (en) |