JPS5837178A - Etching method - Google Patents

Abstract

PURPOSE:To obtain a chemical etching substance having no variance in its etching thickness, by soaking a substance to be etched into an etchant which has been set to a bubbling state by jetting gas through a lot of small holes, and executing the etching. CONSTITUTION:In an etching board 1 made of teflon, etc., scores of pieces of semiconductor substrates 2,... are installed in parallel at intervals of several millimeters in an erect state, and are soaked in an etchant 4 consisting of mixed acid of fluoric acid, nitric acid and acetic acid, etc. On the bottom part of a vessel 3 of the etchant 4, a gas jetting case 5 which has been formed by teflon, etc. and has countless small holes on the surface is provided, and air is fed from a gas feed pipe 6 and is jetted into the etchant 4 from said small holes, by which the etchant 4 is set to a bubbling state. When this state is continued for several minutes, said substrates 2... are subjected to uniform chemical etching.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an etching method V& for finishing, for example, a double-sided semiconductor substrate or a flat surface of a single-sided tube by chemical etching.

In the semiconductor device OJl fabrication process 11, there is a method of selectively etching the entire surface of the semiconductor substrate using a chemical etcher. Examples of processes using this chemical ettender include the following process.

■ A high concentration layer of phosphorus (N") or 1N high concentration layer (Pl) is de/dipped on both sides of the semiconductor substrate. Only one side of the high concentration layer (Pl) is left, and the unnecessary opposite side is covered with several tens of μm. The process of removing etching and using the etched surface as an active area.

■ A process of etching and removing the crushed layer on the surface of the substrate that has been lapped (S1000 Lap) to obtain an etched surface that is close to a mirror surface on which devices can be formed.

It is used in various processes such as

This Kenkar etching finish has the following characteristics.

■ Compared to the mirror polishing method, which mechanically removes seven layers of the silicon surface, the in-plane parallelism of the semiconductor substrate and the degree of mirror polishing are inferior, but it does not require expensive equipment such as a mirror polisher, and is simple and inexpensive. It is possible to work with the equipment.

(2) Since a large number of semiconductor substrates can be processed simultaneously in a relatively short time, it is suitable as a method for manufacturing low-cost semiconductor devices.

(2) An etchant having desired etching properties can be obtained by changing the blending ratio of etchant composition, for example, fluoric acid (IP), nitric acid (BNo.), and acetic acid (CH, C00H).

However, this method of power generation has the following problems.

■ Etching to obtain an etched surface close to a mirror surface causes the peripheral part of the substrate to sag, resulting in poor parallelism.

Since the solder surface becomes rough, it is difficult to align the PEP-f sheets in a subsequent process, and this adversely affects the characteristics of the semiconductor element.

That is, with conventional etching methods, it is difficult to obtain an etched surface that is satisfactory in terms of both parallelism and straightness, and it is extremely difficult to obtain a flatness equivalent to mechanical polishing.

Hereinafter, conventional Oeratin 1 method 1 will be specifically explained. Iris 1
As shown in the figure, dozens of semiconductor substrates 2...- are placed in parallel in an upright position in an O-touching &-) Z made by Tairon. Install at 9 intervals. And this etching &
-) Ji-container inner etchant (for example, IF:H
Mixed acid with a mixing ratio of NO3:CH,C00H=1:2:1)
4 for several minutes (for example, 2 minutes) and then cut to a predetermined thickness (for example, 30 μm).

This is done using conventional etching methods.

When we measure the variation in the flatness, that is, the amount of protrusion, in the plane of the semiconductor substrate when chipping, we find that there is a difference between the peripheral part 1- of the semiconductor substrate 2 and the central part of the substrate, as shown by curve A shown in FIG. A difference of 20μ to 30μ is observed in the amount of cracking and ching.

Such large etchings and cracks in the periphery of the semiconductor substrate 2 become as follows when an actual semiconductor element, for example, an NPN power transistor tube is formed. That is, as shown in FIG.
0-order Kjg2 diagram (b) that forms 1.13 with a thickness of 20 tones
As shown in FIG. 1, a wax layer 14' is formed as a protective layer on the surface of one of the fr-reflection layers 180, and then the other one of the fr-reflection layers 12t1 is etched by the etching method shown in FIG. When etching 30μ to 40 voices,
The surface of the exposed silicon substrate 11 is curved as shown in FIG. 2(b) and has a mountain-like shape due to the characteristics of the curved line shown in FIG. Then, the inner surface of the silicon substrate 11 is coated with a paste 15 and an enzyme using the well-known O technique.

If multiple locations are formed, one layer of N (one layer) in the center will be formed.
There is a large difference between the width t1 of the peripheral pellet and the width 1° of the N single layer of the peripheral pellet], and variations in the surface of the semiconductor substrate 11 cause variations in the characteristics of the semiconductor elements, which in turn causes a decrease in yield.

The present invention has been made in view of the above circumstances, and its purpose is to perform etching by immersing a V-chinda object in an etchant in a d-pring state.
An object of the present invention is to provide an etching method that eliminates the conventional drawbacks and enables uniform etching.

An embodiment of the present invention will be described below with reference to the drawings. The same parts as in FIGS. 1 and 2 will be described with the same reference numerals. In FIG. 4, several tens of semiconductor substrates (for example, silicon substrates) X, - are placed in an upright position parallel to each other at intervals of several millimeters in an etching chamber 1 made of, for example, Teflon. The problem with this invention is that the etchant is in a Δ-pulling state because it is immersed in the etchant installed in this way and then etched.

For example, a gas ejection box 5 having a hole)' having a diameter of about 0.5W is provided. A gas supply Δ Eve 6 for supplying gas, for example, air, is connected to the gas ejection box 5. In the container S in which the gas ejection box I is installed in this way, an etchant (for example, HF:HNo, :cascooax 1:2
: Accommodates 4 (O mixed acid) with a blending ratio of 1. After that, air is supplied from the gas supply pipe f6 and air is ejected from the small hole of the gas ejection box 5 into the chanter 4 to bring the etchant 4 into a uniform FC/ff cylinder state. By submerging a large number of semiconductor substrates 2 into the etching chamber (4) in this pari yy state (4),
, the semiconductor substrate lfA is immersed in the etchant 4 in a cylinder state for several minutes (for example, 2 minutes) and etched to a predetermined thickness, for example, 30 μm. In this case, the etchant 4 is uniformly shaped like a cylinder] 1! As a result, the etchant 4 is agitated and brought into a state of 9, and uniform processing and soldering can be performed on the inner surface of the semiconductor substrate 2.

In this way, when Af shillingoshe and chant 4 create a fast flow, KIJ+% is forced into a uniform state. ζThe results of measuring the variation in the amount of etching within the plane of a semiconductor substrate when etched using the method of the present invention are shown in Figure 3. 0115 or less, a significant improvement is possible. Therefore, it is possible to obtain a chemically etched substrate that has almost no variation in etching thickness (sagging around the IE) and has an etched surface equivalent to that of a mirror substrate produced by a T-polishing machine), and improves semiconductor device characteristics. Variability can be significantly improved.

Hereinafter, an application example of the method of the present invention will be described, for example, a case where the method is applied to a single-sided fabrication of an NPNΔ power transistor and a process of forming a ting-removed substrate.

First, as shown in FIG. 5(a), high concentration (for example, 1X10'') N''-r/dielectric layers 11 and 13t are formed on both sides of a silicon substrate 11 to a thickness of 20 μm.

Next, as shown in FIG. 5(b), a wax layer 14t is formed as a protective layer on the surface of one of the N''r/ref 1f layers 13.
- form and then the other ow”r/zosi.

When the etching layer 12t is etched by the method of the present invention described above, the silicon substrate 11 exposed as shown in FIG. As shown in ), a plurality of pastes 15 and a plurality of pastes Jljl are formed on the inner surface of the silicon substrate 11 using a well-known technique. In this case, since the etched surface of the ss'9'' substrate 11 is flat, it goes without saying that the holes in the center and the holes in the periphery can be made uniform, and the characteristics are also uniform. [K] has the effect of improving yield.

In the above embodiment, when air is supplied, the etchant is brought into a ring state. For your information, although the above embodiment describes etching a semiconductor substrate, the present invention can be applied to etching either an insulator layer or a conductor layer.

As described in detail above, according to the present invention, K1l1. By performing etching by dipping the etching material, it is possible to provide an etching method that eliminates the conventional drawbacks and enables uniform etching.

[Brief explanation of the drawing]

Fig. 1 is a longitudinal cross-sectional side view of an O-electronic etching device to explain the conventional etching method, and Fig. 2 (,) to (,)
Figure 3 is a process explanatory diagram when the conventional etching method is applied to the manufacturing process of t-NPN/#Quala transistor, and Figure 3 is a distribution showing a comparison of the smoothness of the etched surface by the conventional etching method and the etching method of the present invention. 4 is a vertical cross-sectional side view of a chemical processing apparatus for explaining an embodiment of the present invention, and FIGS. It is a process explanatory diagram when applied to a process. 1.-Etching one piece, 2.-Semiconductor substrate, S-container, 4-Etchant, 5.-Gas ejection box, 6-Gas supply Δve, 11...Silicon substrate, 12#13-N+De4 layer, 14-wax layer, 15-paste layer,
16-E5 ivy. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 4 Figure 5

Claims (2)

[Claims] (1) If the mason is in a bubbling state, immerse the material to be etched during chanting and perform etching.
Etching method using mold. (2) The etching method according to claim 1, wherein the means for bringing the etching surface into the Δ cylinder state is carried out by blowing out a gas such as air from a large number of small holes on the etching surface. .