JPS62118528A - Processing of semiconductor device - Google Patents

Processing of semiconductor device

Info

Publication number
JPS62118528A
JPS62118528A JP25897485A JP25897485A JPS62118528A JP S62118528 A JPS62118528 A JP S62118528A JP 25897485 A JP25897485 A JP 25897485A JP 25897485 A JP25897485 A JP 25897485A JP S62118528 A JPS62118528 A JP S62118528A
Authority
JP
Japan
Prior art keywords
capacitor
oxide film
wafer
around
sio2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25897485A
Other languages
Japanese (ja)
Inventor
Koji Furuta
古田 孝司
Hiroki Naraoka
浩喜 楢岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP25897485A priority Critical patent/JPS62118528A/en
Publication of JPS62118528A publication Critical patent/JPS62118528A/en
Pending legal-status Critical Current

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  • Formation Of Insulating Films (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

PURPOSE:To enable even drying up process to be performed while cutting water film evenly from the end of a wafer by a method wherein, in the cleaning process before sir-knife drying process, an oxide film is formed by chemical processing on an exposed substrate surface to be etched while leaving the oxide film. CONSTITUTION:When an MOS capacitor is formed, a LOCOS (SiO2) separating the capacitor and a pattern on an exposed Si substrate surface to be a capacitor coexist together on one main surface of a wafer. This wafer is cleaned up for the minutes in a cleaning solution with mixing ratio of e.g. NH4OH:H2O2:H2 O=1:2:7. An oxide film around 1mum thick is formed on Si by this cleaning process. After sufficient washing, the oxide film is immersed in a solution with mixing ratio of e.g. H2O:HF=500:1 to be etched by around 0.5mum leaving it by around 0.5nm. After sufficient washing, the oxide film is airknife-dried up later to form a capacitor SiO2 and then a polysilicon electrode is formed to form an MOS capacitor.

Description

【発明の詳細な説明】 産業−1−の利用分野 本発明は、仝ト導体集積回路を製造する過程に関するも
のである。特に拡散炉の前工程として、シリコン(Sl
)ウェハーの清浄化を行う方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Application of Industry-1- The present invention relates to a process for manufacturing a non-conductor integrated circuit. In particular, as a pre-process of the diffusion furnace, silicon (Sl)
) relates to a method for cleaning wafers.

従来の技術 半導体ウェハーの大口径化、工場の自動化が進X7でお
り、それに伴い、枚葉式処理工程が増加している。
BACKGROUND OF THE INVENTION 2. Description of the Related Art As the diameter of semiconductor wafers increases and factories become more automated, single-wafer processing processes are increasing.

ンリコンウエハー洗浄後の乾燥においても、現在バッチ
式のスピンドライ方式(遠心脱水法)が2ぺ−7 主流であるが、ウェハーの犬「1径化、工場の自動化へ
の対応には5枚葉式エアーナイフ乾燥(高圧気体を噴き
つける方法)の方が、作業効率−1−1はるかに好適で
ある。
Batch-type spin drying (centrifugal dehydration) is currently the mainstream for drying after cleaning wafers. Leaf air knife drying (method of spraying high-pressure gas) is much more suitable for working efficiency -1-1.

発明が解決しようとする問題点 しかし々がら、乾燥をエアーナイフに変更し、その後キ
ャパシタ5i02を形成し、その上にポリンリコン電極
を形成し、 MOSキャパシタを作り、そのキャパシタ
5i02の収率を測定l〜だところ、従来技術のスピン
ドライ方式を用い、同様に収率を求めたものに比べ、キ
ャパシタSiO2の収率は、顕しく劣っていた。
However, the drying method was changed to an air knife, and then a capacitor 5i02 was formed, a polycone electrode was formed on it, a MOS capacitor was made, and the yield of the capacitor 5i02 was measured. However, the yield of the capacitor SiO2 was significantly inferior to that obtained by similarly determining the yield using the conventional spin dry method.

本発明は、半導体集積回路を製造する過程において、エ
アーナイフ乾燥方式を用いても、キャパシタ5i02の
収率は、スピンドライ方式と同程度本発明シ1:、エア
ーナイフ乾燥前の洗浄において、露出基板面に、化学薬
品処理によって酸化膜を形成したのち、同酸化膜が残置
するようにエッチングし、その後、エア乾燥処l1l−
J−る半導体装置の処理方法である。
In the process of manufacturing semiconductor integrated circuits, even if the air knife drying method is used, the yield of the capacitor 5i02 is the same as that of the spin drying method. After forming an oxide film on the substrate surface by chemical treatment, etching is performed so that the oxide film remains, and then air drying treatment is performed.
This is a method for processing a semiconductor device.

作用 上記手段にJ:って、 it’d来Q1、親水性810
2表面と。
J: According to the above means, it'd be Q1, hydrophilic 810
2 surface.

疎水性Si表面が/I/4在17在日7ウニ・・−一主
面が1化学薬品処理によって形成しノζ酸化膜を残置す
ることにより、ウェハー−主面上を総て親水性5102
によって被うことが可能となり、エアーナイフ乾燥を用
いても、ウェハーの端から均一に水膜が切れていくため
、均一な乾燥が可能となった。
The hydrophobic Si surface is formed by chemical treatment on one main surface and leaves a ζ oxide film, making the entire main surface of the wafer hydrophilic.
Even if air knife drying is used, the water film is evenly cut from the edge of the wafer, making it possible to dry the wafer uniformly.

実施例 以下、本発明の一実施例について訝4明する。Example Hereinafter, one embodiment of the present invention will be explained.

実デバイスにおいて、 MOSキャパシタを形成すると
き、ウェハーの一十面は、キャパシタの分離を行うLo
cos(SiO2)とキャパシタになる81基板露出面
のパターンとが混在する。
In an actual device, when forming a MOS capacitor, ten sides of the wafer are used as Lo for separating the capacitors.
Cos(SiO2) and a pattern on the exposed surface of the 81 substrate which becomes a capacitor coexist.

このウェハーを例えば NH4OH: H2O2: H20=1 :2 ニア 
、 70”(:の液で10分洗浄を行う。このlA7浄
によってSi上に約1 nmの酸化膜を形成させる。十
分に水洗17だ後1例えばH2O:HF二600:1 
の液に1分浸漬を行い、酸化膜を約0.6 nmエツチ
ングし、約0.5nm  残置する。
For example, this wafer is treated with NH4OH:H2O2:H20=1:2 near
, 70" (:). This lA7 cleaning forms an oxide film of about 1 nm on the Si. After thorough water washing, for example, H2O:HF2600:1.
The oxide film is etched by approximately 0.6 nm and approximately 0.5 nm is left behind.

十分水洗した後、エアーナイフ乾燥を行い、その後キャ
パシタ5102を形成し、さらにその上にポリシリコン
電極を形成し、 MOSキャパシタを作る。H2O:H
F=500:1の液に浸漬する時間を変化させ、 MO
Sキャパシタを作成し、キャパシタ5102の収率と、
H2O:HF:600 : 1  液浸漬時間との関係
を調べた結果を図に示す。キャパシタ5102の収率ば
、以下のように求めた。すなわち、Locos(Si0
2)とSlのパターンが混在するPバリ(100)10
〜150m の6インチウェハーに、」−記洗浄を行い
、エアーナイフ乾燥後、キャパシタ5i02を約20n
m形成し、その」二に約o、s nlrのポリシリコン
電極を形成し、 MOSキャパシタを6インチ1ウエハ
ーあたり300個作成した。
After thoroughly washing with water, air knife drying is performed, and then a capacitor 5102 is formed, and a polysilicon electrode is further formed thereon to form a MOS capacitor. H2O:H
By varying the immersion time in the F=500:1 solution, MO
Create an S capacitor, and calculate the yield of capacitor 5102 and
The results of investigating the relationship with H2O:HF:600:1 liquid immersion time are shown in the figure. The yield of capacitor 5102 was determined as follows. That is, Locos(Si0
P burr (100) 10 with a mixture of 2) and Sl patterns
A 6-inch wafer with a length of ~150m was cleaned and dried with an air knife, and then capacitors 5i02 were
300 MOS capacitors were fabricated per 6-inch wafer.

ポリシリコン電極に一15V印加したときに流れる電流
が1 μA以下のMOSキャパシタを良品として、6 
、 キャパシタ5102の収率を求めた。本実施例によると
、 図に示されているように、化学薬品洗浄液(NH40H
:H2O2:H2〇二1 :2 ニア、70’C)によ
って形成した約I Jimの酸化膜が、少しでも残置し
ている状態、すなわちH2O: HF:500:1の浸
漬が3分以内の場合において、キャパシタ5i02の収
率は、従来のスピンドライ方式適用の場合と同等であり
1とりわけ、0.2〜2分以内では、それをしのいで、
最も高くなっている。
A MOS capacitor whose current flows when 15V is applied to the polysilicon electrode is 1 μA or less is considered to be a good product.6
, the yield of capacitor 5102 was determined. According to this example, as shown in the figure, a chemical cleaning solution (NH40H
:H2O2:H2〇21:2 (near, 70'C) in which the oxide film of approximately I Jim remains even a little, that is, when immersion in H2O:HF:500:1 is for less than 3 minutes. In this case, the yield of capacitor 5i02 is equivalent to that of the conventional spin-drying method.1 In particular, within 0.2 to 2 minutes, the yield of capacitor 5i02 is equivalent to
It is the highest.

発明の効果 り上のように、本発明は、半導体集積回路を製造する過
程において、工場の自動化、ウェハーの大口径化に対応
j〜やすいエアーナイフ乾燥方式を用いる場合において
、キャパシタ5i02の収率を高めることに対し、大き
な効果を発揮し、その実用的効果は、特にキャパシタを
メモリーに用いているダイナミックメモリーの製造過程
に用いることにより、ビット不良を減少させるのに非常
に大きな効果がある。
As described above, the present invention improves the yield of capacitor 5i02 when using the air knife drying method, which is easy to adapt to factory automation and large-diameter wafers, in the process of manufacturing semiconductor integrated circuits. The practical effect is particularly great in reducing bit defects when used in the manufacturing process of dynamic memories that use capacitors in the memory.

6ペー/6 pages/

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明実施態様における特性例として。 HF液浸漬時間とキャパシタ5102の収率の関係を示
す特性図である。
The figure is an example of characteristics in an embodiment of the present invention. 5 is a characteristic diagram showing the relationship between the HF liquid immersion time and the yield of the capacitor 5102. FIG.

Claims (1)

【特許請求の範囲】[Claims] 洗浄工程において、化学薬品処理によって酸化膜を形成
したのち、同酸化膜を残置した状態でエア乾燥処理を行
うことを特徴とする半導体装置の処理方法。
A method for processing a semiconductor device, comprising forming an oxide film by chemical treatment in a cleaning step, and then performing air drying treatment with the oxide film remaining.
JP25897485A 1985-11-19 1985-11-19 Processing of semiconductor device Pending JPS62118528A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25897485A JPS62118528A (en) 1985-11-19 1985-11-19 Processing of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25897485A JPS62118528A (en) 1985-11-19 1985-11-19 Processing of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62118528A true JPS62118528A (en) 1987-05-29

Family

ID=17327599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25897485A Pending JPS62118528A (en) 1985-11-19 1985-11-19 Processing of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62118528A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5281544A (en) * 1990-07-23 1994-01-25 Seiko Epson Corporation Method of manufacturing planar type polar transistors and combination bipolar/MIS type transistors
WO1995004372A1 (en) * 1993-07-30 1995-02-09 Semitool, Inc. Methods for processing semiconductors to reduce surface particles
US5404043A (en) * 1990-07-23 1995-04-04 Seiko Epson Corporation Semiconductor devices of the planar type bipolar transistors and combination bipolar/MIS type transistors
US6240933B1 (en) 1997-05-09 2001-06-05 Semitool, Inc. Methods for cleaning semiconductor surfaces

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5281544A (en) * 1990-07-23 1994-01-25 Seiko Epson Corporation Method of manufacturing planar type polar transistors and combination bipolar/MIS type transistors
US5404043A (en) * 1990-07-23 1995-04-04 Seiko Epson Corporation Semiconductor devices of the planar type bipolar transistors and combination bipolar/MIS type transistors
WO1995004372A1 (en) * 1993-07-30 1995-02-09 Semitool, Inc. Methods for processing semiconductors to reduce surface particles
US5489557A (en) * 1993-07-30 1996-02-06 Semitool, Inc. Methods for processing semiconductors to reduce surface particles
US6240933B1 (en) 1997-05-09 2001-06-05 Semitool, Inc. Methods for cleaning semiconductor surfaces
US6830628B2 (en) 1997-05-09 2004-12-14 Semitool, Inc. Methods for cleaning semiconductor surfaces
US6843857B2 (en) 1997-05-09 2005-01-18 Semitool, Inc. Methods for cleaning semiconductor surfaces

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