JPS5835475A - Measuring method for semiconductor device - Google Patents

Measuring method for semiconductor device

Info

Publication number
JPS5835475A
JPS5835475A JP56134302A JP13430281A JPS5835475A JP S5835475 A JPS5835475 A JP S5835475A JP 56134302 A JP56134302 A JP 56134302A JP 13430281 A JP13430281 A JP 13430281A JP S5835475 A JPS5835475 A JP S5835475A
Authority
JP
Japan
Prior art keywords
temperature
active region
consumed power
thermal resistance
difference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56134302A
Other languages
Japanese (ja)
Inventor
Yoshimitsu Sakakawa
坂川 義満
Takeshi Mizusawa
水沢 武
Hiroshi Watanabe
寛 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56134302A priority Critical patent/JPS5835475A/en
Publication of JPS5835475A publication Critical patent/JPS5835475A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

PURPOSE:To determine the thermal resistance of a semiconductor device from the active region thereof to the outside in the state of the working operation of the device, by finding the change in temperature of the active region from the thermal dependency of the characteristic values of the device and the difference in the characteristic values in the state of double operations thereof, and by dividing the change by the difference in a consumed power. CONSTITUTION:An information retention time period t of MOS dynamic RAM shows such thermal dependency as expressed by t=tOeE<a/>KT... (1), wherein t0 is a specific constant, K is a Boltzmann constant, T is a temperature in an active region, and Ea is an activation energy. The dependency of the information retention time period on an ambient temperature is measured by a prescribed signal pattern, and the activation energy in the formula (1) is determined. Then, the thermal resistance R is determined from the consumed power PH in a test signal pattern SH for a large consumed power and from the consumed power PL in a test pattern SL for a small consumed power, and from information retention time periods tH and tL. The thermal resistance is calculated by conducting the operation of R=DELTAt/(PH-PL), where DELTAt is the difference in temperature between the patterns SH and SL.

Description

【発明の詳細な説明】 本発明は実用動作状態において半導体装置の能動領域か
ら外界までの熱抵抗を求める測定方法に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a measuring method for determining the thermal resistance from the active region of a semiconductor device to the outside world in a practical operating state.

従来、この種の測定を行なう場合、半導体装置の能動領
域の温度上昇をPN接合の順方向電流・電圧特性によっ
て測定していた。多くの半導体装置では、実用動作状態
でPN接合に順方向電流を流しその電流・電圧特性を測
定することができないため、一定の発熱をさせた後、順
方向に電圧を印加し、短時間で測定を行なっていた。
Conventionally, when performing this type of measurement, the temperature rise in the active region of a semiconductor device has been measured based on the forward current/voltage characteristics of the PN junction. In many semiconductor devices, it is not possible to pass a forward current through the PN junction during practical operation and measure its current/voltage characteristics. Therefore, after a certain amount of heat is generated, a forward voltage is applied and the was taking measurements.

従って、実用動作と異なる状態が発生し、実用動作状態
における真の温度上昇が測定できない欠点があった。
Therefore, a situation different from that in actual operation occurs, and there is a drawback that the true temperature rise under actual operating conditions cannot be measured.

本発明はこれらの欠点を解決するため、半導体装置の能
動領域の温度上昇を実用動作状態で測定し、能動領域か
ら外界まで(構成素子の部分からその外囲器の周シまで
)の熱抵抗を求めるもので、以下に実施例によって詳細
な説明を行なう。
In order to solve these drawbacks, the present invention measures the temperature rise in the active region of a semiconductor device under practical operating conditions, and calculates the thermal resistance from the active region to the outside world (from the component part to the periphery of its envelope). A detailed explanation will be given below using examples.

〔実施例1〕 本発明をMOSダイナミック形ラフランダムアクセスメ
モリ用した例を説明する。MOSダイナミック形ラフラ
ンダムアクセスメモリ費電力はサイクルタイム等にょシ
実用動作状態で変えられる。また情報保持時間tは一般
に次式のような温度依存性を示す。
[Embodiment 1] An example in which the present invention is applied to a MOS dynamic type rough random access memory will be described. MOS dynamic type rough random access memory cost and power can be changed depending on practical operating conditions such as cycle time. Further, the information retention time t generally exhibits temperature dependence as shown in the following equation.

t = t  ekT          (1)ただ
し、toは半導体装置固有の定数 にはボルツマン定数 Tは能動領域の温度 Eaは活性化エネルギー 一定の試験信号パターンにより情報保持時間の周囲温度
依rY性を測定し、(1)式の活性化エネルギーを求め
る。次に消費電力の大きい試験信号パターンSIIと消
費電力の小さい試験パターンSLでの消費電力PH’P
L及び情報保持時間tH,lLから熱抵抗Rを次式によ
り求める。
t = tekT (1) where to is a constant specific to the semiconductor device, Boltzmann's constant T is the temperature of the active region Ea is the ambient temperature dependence of the information retention time is measured using a test signal pattern with a constant activation energy, Find the activation energy in equation (1). Next, the power consumption PH'P in the test signal pattern SII with the highest power consumption and the test signal pattern SL with the lowest power consumption.
The thermal resistance R is determined from L and the information retention times tH and 1L using the following formula.

R:ΔT/(PHPL)      (2)ただし、Δ
TはパターンSHs  8Lでの温度差で、次式により
求める。
R: ΔT/(PHPL) (2) However, Δ
T is the temperature difference in pattern SHs 8L, and is determined by the following equation.

ただし、TLはパターンSLのときの能動領域温度で、
PLが十分小さいとき周囲温度TaキTLと近似する。
However, TL is the active region temperature at the time of pattern SL,
When PL is sufficiently small, it approximates the ambient temperature Ta.

第1表は二つの動作状態を実現させるだめの試験信号パ
ターン5H1SLの一例を示すものである。
Table 1 shows an example of a test signal pattern 5H1SL that realizes two operating states.

第1表 試験パターンの例 試験メモリセルAに情報を書き込み、一定の非選択期間
の後、情報を読み出し検査する。非選択期間を変え、正
常動作する最大の時間を求め、情報保持時間とする。非
選択期間に、試験メモリセルに影響を与えない他のメモ
リセルBを高速で動作させることにより消費電力の大き
いパターンS□となる。メモリセルAの非選択期間中に
他のすべてのメモリセルも非動作とすれば、消費電力の
小さいパターンSLとなる。
Table 1 Examples of test patterns Information is written to the test memory cell A, and after a certain non-selection period, the information is read out and tested. By varying the non-selection period, find the maximum time for normal operation and use it as the information retention time. During the non-selection period, other memory cells B that do not affect the test memory cell are operated at high speed, resulting in a pattern S□ with large power consumption. If all other memory cells are also rendered inactive during the non-selection period of memory cell A, a pattern SL with low power consumption will be obtained.

以上の方法で熱抵抗を測定したデータを第2表、第3表
に示す。第2表はパターンSLを用い測定した情報保持
時間の温度依存性である。このデータと(1)式から活
性化エネルギーEaを求めると、Eaは0.59oVと
ナツタ。
Tables 2 and 3 show data obtained by measuring thermal resistance using the above method. Table 2 shows the temperature dependence of information retention time measured using pattern SL. When the activation energy Ea was determined from this data and equation (1), Ea was 0.59oV.

第2表 情報保持時間の温度依存性 第3表は情報保持時間を試験信号パターンsH・SLで
測定した場合の消費電力と情報保持時間のデータである
。なお、測定時の温度は室温25℃である。
Table 2 Temperature dependence of information retention time Table 3 shows data on power consumption and information retention time when information retention time was measured using test signal patterns sH and SL. Note that the temperature at the time of measurement was room temperature 25°C.

第3表のデータを用いて、パターンsHとパターンSL
の温度差ΔTを前記(3)式から求めると、ΔT = 
13.2℃となり、またそのΔTと第3表のPH1PL
を用いて、熱抵抗Rを前記(2)式から*めると、R−
50℃/Wとなる。
Using the data in Table 3, pattern sH and pattern SL
When calculating the temperature difference ΔT from the above equation (3), ΔT =
13.2℃, and its ΔT and PH1PL in Table 3
If we calculate the thermal resistance R from the above formula (2) using
It becomes 50°C/W.

ダイナミック形の回路を用いた半導体装置では、実使用
状態でクロック信号を入力しないと消費電力が増加しな
い。また、PN接合に順方向電流を流す従来例の場合、
実使用時とは異なった位置で発熱し、実使用状態に対応
したデータが得られない。これに対し、本発明は上記実
施例に示しだように実使用状態での特性値を用いること
ができるので、このような半導体装置の実使用状態での
熱抵抗評価を適切に行なうことができる。
In a semiconductor device using a dynamic circuit, power consumption does not increase unless a clock signal is input during actual use. In addition, in the case of the conventional example in which forward current flows through the PN junction,
Heat is generated in a location different from that during actual use, making it impossible to obtain data that corresponds to actual usage conditions. In contrast, in the present invention, as shown in the above embodiment, the characteristic values under actual use conditions can be used, so that thermal resistance evaluation of such a semiconductor device under actual use conditions can be appropriately performed. .

〔実施例2〕 本発明をC−MO8IC<相補形MO8集積回路)に適
用した例を説明する。C−MOS ICの消費電力は入
力信号周波数fに依存し、伝搬遅延時間τは温度に依存
する。そこで一定の入力周波数におけるτの温度依存性
を求める。次に同一周囲温度で異なる入力周波数fH,
、fLに対する消費電力PH1PLと伝搬遅延時間τ□
、τ1を求める。τの温度依存性とて□、τ1から二動
作状態の温度差ΔTを求め、(2)式に代入し、熱抵抗
を求める。
[Embodiment 2] An example in which the present invention is applied to a C-MO8 IC (complementary MO8 integrated circuit) will be described. The power consumption of a C-MOS IC depends on the input signal frequency f, and the propagation delay time τ depends on the temperature. Therefore, the temperature dependence of τ at a constant input frequency is determined. Next, different input frequencies fH at the same ambient temperature,
, power consumption PH1PL and propagation delay time τ□ for fL
, τ1 is determined. The temperature dependence of τ is □, and the temperature difference ΔT between the two operating states is determined from τ1 and substituted into equation (2) to determine the thermal resistance.

C−MO3JCでは入出力端子に近いごく一部の回路部
分以外には順方向電流を流すことができない。
In C-MO3JC, forward current cannot flow except in a very small portion of the circuit near the input/output terminals.

本発明は実使用状態での特性値を用いる方法であるので
、このような半導体装置の熱抵抗評価を適切に行なうこ
とができる。
Since the present invention is a method that uses characteristic values under actual use conditions, it is possible to appropriately evaluate the thermal resistance of such a semiconductor device.

以上の測定項目の他に、出力電圧レベル、出力電流、雑
音等、温度依存性を示す測定項目については本発明を適
用することができる。
In addition to the above measurement items, the present invention can be applied to measurement items that exhibit temperature dependence, such as output voltage level, output current, and noise.

以上説明したように、本発明は実使用状態で、通常用い
られる測定項目を用い、熱抵抗を1ft11定する方法
である。このため、特殊な測定機を必要とせず、実使用
状態の発熱分布に即した熱抵抗が得られる利点がある。
As explained above, the present invention is a method for determining thermal resistance by 1 ft11 in actual use using commonly used measurement items. Therefore, there is an advantage that a thermal resistance matching the heat generation distribution under actual use conditions can be obtained without requiring a special measuring device.

−411=−411=

Claims (1)

【特許請求の範囲】[Claims] 消費電力の異なる複数の実用動作状態と温度依存性を示
す特性測定項目を有する半導体装置の測定力法において
、特性値の温度依存性と二動作状態での特性値の差異か
ら能動領域の温度変化を求め、消費電力の差で除算する
ことにより、能動領域から外界までの熱抵抗を求めるこ
とを特徴とする半導体装置の測定方法。
In the measurement force method for semiconductor devices that have characteristic measurement items that show multiple practical operating states with different power consumption and temperature dependence, temperature changes in the active region can be determined from the temperature dependence of characteristic values and the difference between characteristic values in two operating states. 1. A method for measuring a semiconductor device, characterized in that the thermal resistance from the active region to the outside world is determined by calculating and dividing by the difference in power consumption.
JP56134302A 1981-08-28 1981-08-28 Measuring method for semiconductor device Pending JPS5835475A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56134302A JPS5835475A (en) 1981-08-28 1981-08-28 Measuring method for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56134302A JPS5835475A (en) 1981-08-28 1981-08-28 Measuring method for semiconductor device

Publications (1)

Publication Number Publication Date
JPS5835475A true JPS5835475A (en) 1983-03-02

Family

ID=15125102

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56134302A Pending JPS5835475A (en) 1981-08-28 1981-08-28 Measuring method for semiconductor device

Country Status (1)

Country Link
JP (1) JPS5835475A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103411997A (en) * 2013-08-06 2013-11-27 中国科学院微电子研究所 Method for extracting thermal resistance of SOI-MOSFET

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5384685A (en) * 1976-12-30 1978-07-26 Fujitsu Ltd Semicocductor element measuring method
JPS5473580A (en) * 1977-11-24 1979-06-12 Hitachi Ltd Temperature measuring of mis semiconductor unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5384685A (en) * 1976-12-30 1978-07-26 Fujitsu Ltd Semicocductor element measuring method
JPS5473580A (en) * 1977-11-24 1979-06-12 Hitachi Ltd Temperature measuring of mis semiconductor unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103411997A (en) * 2013-08-06 2013-11-27 中国科学院微电子研究所 Method for extracting thermal resistance of SOI-MOSFET

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