JPS5834984B2 - doukisouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for synchronizing two types of frequency signals that are generated separately to the same frequency.

Various devices have been proposed in the past as devices for synchronizing two types of frequency signals, but in all cases, synchronization is often performed with each frequency slightly shifted, and it is difficult to completely match the two frequencies. It was very difficult to do so.

The present invention provides a synchronization device capable of completely matching two frequencies by improving the drawbacks of conventional devices.

The case where the present invention is applied to a synchronization device for a DC motor will be described below.

In FIG. 1, a DC motor 1 is supplied with power from a power source 3 via a control device 2, and the control device 2 controls the voltage or current supplied to the DC motor 1 to rotate the DC motor 1 as described later. Control numbers.

When the DC motor 1 rotates, the pulse generator 4 sends out a pulse train with a repetition frequency proportional to the rotational speed of the DC motor 1.

This pulse train can be generated extremely easily, for example, by electrically detecting the rotational speed of the DC motor 1.

The pulse wave sent from the pulse generator 4 is sent to the subtraction terminal of the reversible counting circuit 5, and the reversible counting circuit 5 subtracts and counts the pulse wave sent from the pulse generator 4.

Further, the pulse train sent from the reference pulse train generation circuit 6 is led to the addition terminal of the reversible counting circuit 5, and this pulse train is added and counted.

The reference pulse train control circuit 6 generates a pulse train to serve as a reference, and the rotation speed of the DC motor 1 is controlled based on this reference pulse train.

The reversible counting circuit 5 performs addition or subtraction counting on the above-mentioned pulse waves, and sends out a carry pulse every time the addition count value exceeds a certain number, and conversely, when the subtraction count value exceeds a certain number, it sends out a carry pulse. Send out a pulse.

The carry pulse of the reversible counting circuit 5 is sent to each reset terminal of the JK flip-flop T and the RS flip-flop 8, and at the same time, it is also sent to the T terminal of the other JK flip-flop 9.

Then, the Q output of the JK flip-flop 9 is sent to the S terminal of the RS flip-flop 10, and when the Q output of the JK flip-flop 9 is inverted from high level to low level, the Q output of the RS flip-flop 10 becomes low level. to be reversed.

Contrary to the above, when a down-down pulse is sent from the reversible counting circuit 5, this down-down pulse is sent to the JK flip-flop 9.
and is sent to the reset terminal of the RS flip-flop 10, and simultaneously sent to the T terminal of the JK flip-flop 7.

The Q output of the JK flip-flop 7 is also sent to the RSS flip-flop 8S terminal.

When the Q output of the TK flip-flop 7 is inverted from a high level to a low level, the RS flip-flop 8 inverts its Q output to a low level.

Therefore, when a carry pulse is sent from the reversible counting circuit 5, the Q output of the R, S flip-flop 8 is immediately reset to a high level, whereas the other RS flip-flop 10 has at least two Its Q output flips to a low level only when successive carry pulses are sent.

Furthermore, when the reversible counting circuit 5 sends out a down-digit pulse, the Q output of the RS flip-flop 10 is immediately reset to a high level, whereas the RS flip-flop 8 receives at least two down-down pulses. Only when it is sent continuously does its Q output flip to a low level.

The Q output of the RS flip-flop 8 is sent to the NAND circuit 11 together with the reference pulse of the reference pulse generation circuit 6.

Therefore, the reference pulse is T(Q of S flip-flop 8
When the output is at a high level, it passes through the NAND circuit 11 and is sent to the S terminal of the RS flip-flop 12.

On the other hand, the Q output of the RS flip-flop 10 is sent to the NAND circuit 13 together with the pulse wave of the pulse generator 4.

Therefore, this pulse wave is the Q of the RS flip-flop 10.
When the output is at a high level, it is sent to the reset terminal of the RS flip-flop 12 after passing through the NAND circuit 13 .

Therefore, the RS flip-flop 12 is connected to the NAND circuit 1
When a reference pulse is sent out from 1, the Q output is inverted to a high 1 level, and when a pulse wave is sent out from the NAND circuit 13, the Q output is reset to a low level.

In the above device, if the repetition frequency of the pulse wave of the pulse generator 4 is lower than the reference pulse of the reference pulse generation circuit 6, the reversible counter 5 sends out a carry pulse. As if this were the case, the Q output of the FtS flip-flop 12 is inverted to a high level.

The Q output of the RS flip-flop 12 is sent to the control device 2, and the control device 2 increases the rotation speed of the motor 1 by controlling the voltage or current supplied to the motor 1 based on the high level output. let

Next, contrary to the above, if the repetition frequency of the pulse wave of the pulse generator 4 is higher than the repetition frequency of the reference pulse,
Since the reversible counter 5 sends out a down-digit pulse, NAND
A pulse wave from the pulse generator 4 is sent from the circuit 13 to the RS flip-flop 12 .

Therefore, the Q output of the RS flip-flop 12 is reset to a low level, and the control device 2 controls the rotational speed of the electric motor 1 to decrease based on this low level output.

When the rotation speed of the electric motor 1 is controlled as described above, the rotation speed of the electric motor 1 and the reference pulse are synchronized as follows.

When the repetition frequency of the pulse wave of the pulse generator 4 is lower than the reference pulse, the reference pulse is sent out from the NAND circuit 11 at this time, but no pulse wave is sent out from the NAND circuit 13.

Then, when the rotational speed of the motor 1 is increased based on the output pulse of the NAND circuit 11, the pulse wave repetition frequency of the pulse generator 4 is increased, and a down-pulse is sent out from the reversible counting circuit 5.

At this time, when the first down-pulse is sent out, the RS flip-flop 10 is immediately reset and its Q output sends out a high level output.

Therefore, a pulse wave is sent out from the NAND circuit 13.

However, the other RS flip-flop 8 is not inverted at the time when the first down-pulse is sent.

Therefore, in this state, pulse waves are sent from both the NANr) circuits 11 and 13, and the Q output of the RS flip-flop 12 is alternately inverted between high level and low level based on these pulses.

Therefore, the control device 2 alternately performs speed increase control and deceleration control of the electric motor 1, and switching between speed increase control and deceleration control is performed at high speed every half cycle of the reference pulse.

As a result, the average value of the speed increase control and deceleration control becomes zero, and the electric motor 1 performs synchronous rotation at a rotational speed having an integer ratio relationship with the repetition frequency of the reference pulse of the reference pulse generation circuit 6.

Furthermore, the pulse repetition frequency of the pulse generator 4 also matches and is synchronized with the repetition frequency of the reference pulse.

As explained above, in the present invention, when the repetition frequency of the pulse wave to be synchronized is higher than the reference pulse train, it is controlled in the direction of decreasing it, and conversely, when it is low, it is controlled in the direction of increasing it. Control operations are performed in three stages so that when the frequencies match, the average value of the control in both directions becomes zero.

Therefore, it is possible to match both frequencies with extremely high precision.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the invention.

Claims (1)

[Claims] 1. In an open circuit device that matches the repetition frequency of a second pulse train to the first pulse train serving as a reference, an addition count (subtraction count) is performed each time the first pulse train is sent out, while the repetition frequency of the second pulse train is Each time the count is subtracted (
a reversible counting circuit that performs an addition count) and sends out a carry pulse every time the addition count value exceeds a certain number, and conversely sends a carry down pulse every time the subtraction count value exceeds a certain number; and the reversible counting circuit. A first logic circuit that is reset by a carry pulse sent from the circuit and whose output is inverted when a plurality of carry down pulses are sent out in succession, and a reset circuit that is reset by a carry down pulse sent from the reversible counting circuit. a second logic circuit whose output is inverted when a plurality of carry pulses are successively transmitted; a first gate that allows the first pulse train to pass when the first logic circuit is reset; a second gate through which the second pulse train passes when resetting the second logic circuit; and a pulse train O which passes through the first gate, thereby increasing the repetition frequency of the second pulse train and which passes through the second gate. and a control circuit that performs control to reduce the repetition frequency of the second pulse train.