JPS5834931A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5834931A JPS5834931A JP13347981A JP13347981A JPS5834931A JP S5834931 A JPS5834931 A JP S5834931A JP 13347981 A JP13347981 A JP 13347981A JP 13347981 A JP13347981 A JP 13347981A JP S5834931 A JPS5834931 A JP S5834931A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- support substrate
- element substrate
- bonded
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
Description
【発明の詳細な説明】
この発明は支持基板に素子基板が取り付けられている半
導体装置番こ関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device in which an element substrate is attached to a support substrate.
第１図囚）、知に従来の支持基板に対する素子基板の取
り付は方法を示す。なお、第１図（Ａ）はその平面図で
あり、同図（Ｂ）は同図（Ａｌのｘ−ｘ’における断面
図である。図中、１は支持基板を示している。この支持
基板１には接合部材２を介して素子基板３が接合されて
いる。このとき、素子基板３．接合部材２．支持基板１
それぞれの素材の線膨張係数、ヤング率等がそれぞれ異
なるために素子基板３には、接合温度と冥使用温度との
差により歪が生じる。この素子基板３に生じる歪は、素
子基板３．接合部材２．支持基板１の素材の線膨張係数
の差が小さい程小さい事は明らかである。FIG. 1) shows a conventional method for attaching an element substrate to a support substrate. In addition, FIG. 1 (A) is a plan view thereof, and FIG. An element substrate 3 is bonded to the substrate 1 via a bonding member 2. At this time, the element substrate 3. the bonding member 2. the support substrate 1.
Since each material has a different linear expansion coefficient, Young's modulus, etc., distortion occurs in the element substrate 3 due to the difference between the bonding temperature and the operating temperature. This strain occurring on the element substrate 3 is caused by the strain occurring on the element substrate 3. Joining member 2. It is clear that the smaller the difference in the linear expansion coefficients of the materials of the support substrate 1, the smaller the difference.
したがって、従来より上記の事を考慮して、支持基板１
の素材として線膨張係数が素子基板３に近い４２アロイ
、コバール等が用いられてきた。しかしながら、これら
の材料は熱伝導率が小さく、素子基板３が取り付けられ
た支持基板１を樹脂封止した場合には、熱抵抗が大きく
なってしまう。そこで、熱抵抗を小さくするために、熱
伝導率の大きい銅系の素材を用いることが考えられるが
、銅系の素材は線膨張係数が大き（、Ｎため、素子基板
内に生じる歪が大きくなり、最悪の場合には素子基板に
割れが生じてしまう。Therefore, conventionally, considering the above, the support substrate 1
42 alloy, Kovar, etc., which have a coefficient of linear expansion close to that of the element substrate 3, have been used as the material. However, these materials have low thermal conductivity, and when the support substrate 1 to which the element substrate 3 is attached is sealed with resin, the thermal resistance becomes large. Therefore, in order to reduce the thermal resistance, it is possible to use a copper-based material with high thermal conductivity, but copper-based materials have a large coefficient of linear expansion (N, so the strain that occurs in the element substrate is large. In the worst case, cracks may occur in the element substrate.
第１表に各種素材の諸性質および樹脂封止した場合の熱
抵抗の一例を示す。Table 1 shows an example of the properties of various materials and the thermal resistance when resin-sealed.
第 １ 表
たとえば、４２アロイを素材とした支持基板１ａを用い
た場合、素子基板３との間に生じる変形が、第２図（Ａ
）に示す程度であるとすると、銅系素材の支持基板１ｂ
を用いた場合の素子基板３との間に生じる変形は、第２
図体）に示すようになる。すなわち、銅系素材の支持基
板１を用いた場合の方がより大きな変形を生じる。なお
、素子基板３には線膨張差による収縮とバイメタル効果
による反りが生じる。Table 1 For example, when using a support substrate 1a made of 42 alloy, the deformation that occurs between it and the element substrate 3 is as shown in Figure 2 (A
), the support substrate 1b made of copper-based material
The deformation that occurs between the element substrate 3 and the second
Figure). That is, larger deformation occurs when the supporting substrate 1 made of a copper-based material is used. Note that the element substrate 3 undergoes shrinkage due to the difference in linear expansion and warpage due to the bimetal effect.
第２表は、３ｍＩａの素子基板を４２アロイあるいは燐
脱酸鋼を素材とした支持基板に、各徨接着材料を用いて
接着した時に、素子基板表面に生じる応力の大きさを示
している。なお、この表において、＋は引張応力を示し
、−は圧縮応力を示している。Table 2 shows the magnitude of stress generated on the surface of the element substrate when a 3 mIa element substrate is bonded to a supporting substrate made of 42 alloy or phosphorus-deoxidized steel using various adhesive materials. In this table, + indicates tensile stress and - indicates compressive stress.
この発明は上記のような事情に鑑みてなされたもので、
素子基板を支持基板に取り付けたときの素子基板に生じ
る歪を緩和することができる半導体装置を提供すること
を目的とする。This invention was made in view of the above circumstances,
It is an object of the present invention to provide a semiconductor device that can alleviate strain that occurs in an element substrate when the element substrate is attached to a support substrate.
以下、図面を参照してこの発明の詳細な説明する。第３
図はこの発明の一実施例の支持基板の平面図である。す
なわち、長方形状の銅系材料からなる支持基板１１には
、その１辺に平行な複数の切り込み１１ａ、１１ｂ、・
・・、１１ｄが形成されている。このように形成された
支持基板１ノ上に、接合部材（接着材料）を介して図示
せぬ素子基板が接合される。このとき、素子基板の下面
に上記切り込み１１ａ、１１ｂ・・・。Hereinafter, the present invention will be described in detail with reference to the drawings. Third
The figure is a plan view of a support substrate according to an embodiment of the present invention. That is, the support substrate 11 made of a rectangular copper-based material has a plurality of notches 11a, 11b, . . . parallel to one side thereof.
..., 11d are formed. An element substrate (not shown) is bonded onto the support substrate 1 formed in this manner via a bonding member (adhesive material). At this time, the above-mentioned cuts 11a, 11b, . . . are formed on the lower surface of the element substrate.
１１ｄの一部あるいは全部が位置するようにすることが
肝要である。そして、例えばこのように支持基板１１に
取り付けられた素子基板の複数の電極と図示せぬ各イン
ナーリードとをワイヤ接続したリードフレームの樹脂封
止を行なう。It is important that part or all of 11d be located. Then, for example, a lead frame in which the plurality of electrodes of the element substrate attached to the support substrate 11 and each inner lead (not shown) are connected by wire is sealed with a resin.
したがって、このような半導体装置では、支持基板１１
の強度が低下しているため、接合される素子基板に対す
る支持基板１１の影響は極めて小さくなる。特に、バイ
メタル効果がさくなるために、接合された素子基板の反
りが小さくなり、極めて安定した特性を出すことができ
る。また、支持基板の素材として銅系の材料を用いてい
るため、熱抵抗を低下させることができる。Therefore, in such a semiconductor device, the support substrate 11
Since the strength of the support substrate 11 is reduced, the influence of the support substrate 11 on the element substrates to be bonded becomes extremely small. In particular, since the bimetal effect is reduced, the warpage of the bonded element substrates is reduced, and extremely stable characteristics can be achieved. Furthermore, since a copper-based material is used as the material for the support substrate, thermal resistance can be reduced.
第４図はこの発明の他の実施例の支持基板の平（２）図
である。すなわち、長方形状の銅系材料からなる支持基
板１２には、図示されるようなうずまき状の切り込み１
２Ｂが形成されている。FIG. 4 is a plan view (2) of a support substrate according to another embodiment of the present invention. That is, the support substrate 12 made of a rectangular copper-based material has a spiral cutout 1 as shown in the figure.
2B is formed.
そして、前記実施例と同様に、この支持基板１２上に接
合部材を弁して素子基板が接合される。この場合にも、
前記実施例と同様な効果を得ることができる。Then, similarly to the embodiment described above, an element substrate is bonded onto this support substrate 12 using a bonding member. Also in this case,
Effects similar to those of the above embodiment can be obtained.
なお、上記実施例では支持基板の素材として銅系の材料
を用いるようにしたが、４２アロイ。In the above embodiment, a copper-based material was used as the material for the support substrate, but 42 alloy was used as the material.
コバール等の材料を用いてもよいものである。A material such as Kovar may also be used.
以上述べたようにこの発明によれば、素子基板を支持基
板に取り付けたときの素子基板に生じる歪を緩和させる
ことができる半導体装置を提供することができる。As described above, according to the present invention, it is possible to provide a semiconductor device that can alleviate the strain that occurs in the element substrate when the element substrate is attached to the support substrate.
第１図＜ＡＩは従来の半導体装置の平面図、第１図（Ｂ
ｌは第１図（Ａ）におけるｘ−ｘ’における断面図、第
２図（Ａ） 、 （Ｂ）はそれぞれ支持基板に異なった
材料を用いた場合の変形を示す図、第３図はこの発明の
一実施例における支持基板の平面図、第４図はこの発明
の他の実施例の支持基板の平面図である。
１・・・支持基板、２・・・接合部材、３・・・素子基
板、１１．１２−・・支持基板、ｌｌａ〜ｌｌｄ、１２
ａ・・・切り込み。
出願人代理人 弁理士 鈴 江 武 章節１図
（Ａ）
（Ｂ）
第２図
（Ａ） （Ｂ）Figure 1 <AI is a plan view of a conventional semiconductor device, Figure 1 (B
l is a cross-sectional view taken along line x-x' in Figure 1 (A), Figures 2 (A) and (B) are diagrams showing deformations when different materials are used for the supporting substrate, and Figure 3 is a cross-sectional view of this. FIG. 4 is a plan view of a support substrate according to an embodiment of the invention. FIG. 4 is a plan view of a support substrate according to another embodiment of the invention. DESCRIPTION OF SYMBOLS 1...Support substrate, 2...Joining member, 3...Element substrate, 11.12-...Support substrate, lla-lld, 12
a...notch. Applicant's agent Patent attorney Takeshi Suzue Chapter 1 Figure 1 (A) (B) Figure 2 (A) (B)
Claims (1)
みが形成された支持基板とを具備したことを特徴とする
半導体装置。1. A semiconductor device comprising an element substrate and a support substrate having a notch formed in a surface to which the element substrate is bonded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13347981A JPS5834931A (en) | 1981-08-26 | 1981-08-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13347981A JPS5834931A (en) | 1981-08-26 | 1981-08-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5834931A true JPS5834931A (en) | 1983-03-01 |
Family
ID=15105734
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13347981A Pending JPS5834931A (en) | 1981-08-26 | 1981-08-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5834931A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015106609A (en) * | 2013-11-29 | 2015-06-08 | サンケン電気株式会社 | Semiconductor device |
-
1981
- 1981-08-26 JP JP13347981A patent/JPS5834931A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015106609A (en) * | 2013-11-29 | 2015-06-08 | サンケン電気株式会社 | Semiconductor device |
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