JPS583420B2 - matrix drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a matrix drive circuit that selectively drives a plurality of loads connected in a matrix.

Conventionally, a matrix circuit converts an input voltage into a digital signal using an AD converter, and decodes the digital signal using a decoder to select rows and columns of the matrix circuit.

The A-D converter has a method of generating pulses with a width proportional to the input voltage and counting the width with a counter.
or (2) a method in which there are as many voltage comparators and reference voltage sources as there are loads and each voltage comparator compares the input voltage with the reference voltage of each reference voltage source, or (2) a successive approximation method is used.

However, in the method (2), the A/D conversion time is slow and an oscillator, timing circuit, etc. are required, resulting in a complicated circuit configuration.

Also, a fairly large capacitor is usually required,
If it is integrated into an integrated circuit, the capacitor will be exposed externally.

Although the A-D conversion time is short in method (2), as the number of loads increases, the number of voltage comparators and reference voltage sources also increases, so it is not suitable for driving many loads.

Although the method (2) allows the A-D conversion time to be shorter than the method (2), the circuit becomes more complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a matrix drive circuit suitable for a photographic information display device of a camera, which improves the above-mentioned drawbacks.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of the present invention, in which E1 to E3 are a first reference voltage source group, E4 to E6 are a second reference voltage source group, and 81
~S4 is a switch Comp1~Comp3 is a first voltage comparator group, Comp4~Comp5 is a second voltage comparator group, dec1 and dec2 are decoders, and M is a circuit in which 4×4 loads are connected in a matrix. This load consists of a light emitting diode, etc., which is placed inside the camera's fine cabinet and displays shooting information.

Figure 2 shows the operation of decoders dec1 and dec2,
FIG. 3 shows the truth table for the entire circuit.

Here, the switches S1 to S4 are turned on when each output of the decoder dec2 is at 0 level, and the voltage relationship of the reference voltage sources E1 to E6 is O<E1<E2<E3<E4<E5<E6E3<E5 −
E4, E3<E6-E,

(1) First, when the input voltage 1N is 0<EIN<E4, the row selection voltage comparators Comp4 to Comp6 compare the reference voltages of the reference voltage sources E4 to E6 with the human voltage, and all outputs become zero.

Decoder dec'l is voltage comparator Comp4~Com
The output of p6 is decoded to drive the first row of matrix circuit M and turn on switch S1.

On the other hand, the voltage comparators Compl to Comp3 for column selection compare the reference voltages of the reference voltage sources E1 to E3 with the input voltages,
The output signal is decoded by decoder dec1.

At this time, if 0<v1N<E1, the voltage comparator Com
The output signals of p1 to Comp3 all become 0, and power is supplied from the decoder dec1 to the first column of the matrix circuit M to drive the load in the first row and first column.

When E1<E1N<E2, the output signal of voltage comparator Comp1 becomes 1, and voltage comparators Comp2, Comp
The output signal of No. 3 becomes O, power is supplied from the decoder dec1 to the second column of the matrix circuit M, and the load in the first row and second column is driven.

When E2<E1N<E3, the voltage comparator Comp,
The output signal of Comp2 becomes 1, and the voltage comparator Comp
The output signal of 3 becomes 0, power is supplied from the decoder dec 1 to the third column of the matrix circuit M, and the load in the first row and third column is driven.

When E3<E1N<E4, voltage comparators Comp1 to C
All the output signals of omp3 become 1, and the decoder dec
1 to the fourth column of the matrix circuit M, and the load in the first row and fourth column is driven.

(2) When the input voltage VtN is E4<E1N<E, the output signal of the voltage comparator Comp4 becomes 1, and the voltage comparison, '
Power is supplied to the second row of the matrix circuit M from the decoder dec2 in which the output signals of the devices Comp5 and Comp6 become 0, and the switch S2 is turned on and the switch S1 is turned on.
, S3, and S4 are turned off.

Therefore, the voltage comparators Comp 1 to Comp3 are given the voltages obtained by adding the voltage of the reference voltage source E4 to the voltages of the reference voltage sources E, . .

That is, when E4<EI N<E, -E, the first column is selected and the load in the second row and first column is driven, and E4+E1<
When E1N<E4+E2, the second. The second column is selected.
The load in the second column of the row is driven by 1, and E4 + E2 < E
When I N < E4 + E3, the third column is selected and the load in the second row and third column is driven, and E4 + E3 < E1N
When <E5, the fourth column is selected and the load in the second row and fourth column is driven.

(3) Similarly, when the input voltage V1N is E5<EIN<E6, the third row of the matrix circuit M is selected, the switch S is turned on and the switches S1, S2, and S4 are turned off.

When E5<E1N<E5+E1, the load in the third row and first column is driven, and E5+E1<E1N<
When E 5 < E 2 , the load in the 3rd row and 2nd column is driven, and E 5 + E 2 < E I N < E 5
+ E3, the load in the third row and third column is driven by 7, and E
5+E3<E 1 N<E6, 3rd row, 4th
The column load is driven.

(4) Furthermore, when the input voltage 1N is E6<E1N, the fourth row of the matrix circuit M is selected, the switch S4 is turned on, and the switches 81 to S3 are turned off.

And when E6<EI N<E6+E1, the 4th row 1st
The column load is driven and E6+E, <EI N<E6+E
2, the load in the 4th row and 2nd column is driven, and E6 +
When E2<E1N<E6+E3, the load in the fourth row and third column is driven by 1, and when E6+E3<E1N, the load in the fourth row and fourth column is driven.

With such a matrix drive circuit, the A-D conversion time is only the delay of the input and output of the voltage comparator, so it is extremely fast, and since the input voltage can be input in a time-division manner, multiple pieces of information can be input at the same time. can be displayed.

Also, the number of voltage comparators and reference voltage sources is (number of rows - 1) + (
The number of columns (number of columns - 1) is sufficient, so the number of columns is very small.

In the conventional method, (number of rows)×(number of columns)−1 of these are required.

For example, if we compare these in a matrix circuit with 4 rows and 4 columns,
In the above example, there are 6 pieces, but in the conventional method there are 15 pieces,
Further, when comparing a matrix circuit with 6 rows and 6 columns, the number is 10 in the above example, but it is 35 in the conventional system, and the effect of the above example increases as the number of matrix circuits increases.

In addition, since it is composed of a voltage comparator, a reference voltage power supply, a decoder, and a switch, the circuit is extremely simple and does not require an oscillation circuit, an integrator, a timing circuit, a counter, etc.

FIG. 4 shows a first embodiment of the invention.

In this embodiment, the decoders deci and dec2 are composed of NAND gates NAND1 to NAND8, and the matrix circuit M is arranged in the viewfinder of the camera and includes light emitting diodes LED11 to LED4 that display photographing information.
It consists of a circuit in which 4 are connected in a matrix.

The reference voltage sources E4 to E6 are composed of a DC power supply and resistors R1 to R6, and are set as R2=R3=R4=R5=R.

The reference voltage sources E1 to E3 are composed of operational amplifiers OP1 and OP2 and resistors R7 to R1o, R7=R8=R9=R1
It is set to 0=R/4.

Switches S1 to S4 are analog switches AS1 and AS8
It consists of

NAND gate NAND that constitutes decoder dec2
The output signals of 1 to NAND4 are inverters IN1 to IN4.
The decoder dec1, which is applied to the analog switches AS1-AS8 through the inverters and selects the row, is composed of NAND gates NAND5-NAND8, and each output is applied to the analog switches AS9-AS of the inverters IN5-IN8.
12 to each column of the matrix circuit M.

A circuit including transistors Q1 to Q3 and resistors R11 to R14 switches analog switches AS9 and AS12 in accordance with the output of the oscillator OSC to blink the light emitting diodes LED11 to LED44.

FIG. 5 shows another embodiment of the invention.

In this embodiment, reference voltage sources E1 to E and transistors Q
4 tQ5, consisting of resistors R15 to R27, R1,=
R16, R2, ~R27=R, R17~R20=R/4
is set to

(However, R17 and R24 may be omitted.) Switch 8
1 to S4 are transistors Q6 to Q8 and diodes D1 to
D6, resistors R28 to R33, and a decoder dec
1, dec2 are transistors Q9 to Q16, resistor R35
, R37, R39, and R41 to R45.

As described above, in the matrix drive circuit according to the present invention, the first voltage comparator group compares each reference voltage of the first reference voltage source group with the input voltage, and the second voltage comparator group compares the input voltage with each reference voltage of the first reference voltage source group. The input voltage is compared with each reference voltage of the reference voltage source group, and the load is selectively driven by the output signals of the first and second voltage comparator groups, and the output state of the second voltage comparator group changes. Since each reference voltage of the first reference voltage source group is changed, A-D
The conversion time is short, the circuit configuration is simple, and a fully integrated circuit is possible.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of the present invention, FIGS. 2 and 3 are diagrams for explaining the same example, and FIGS. 4 and 5 are circuit diagrams showing each embodiment of the present invention. . E1 to E6...Reference voltage source, Compl to Co
mp5...Voltage comparator, decl, dec
2...Decoder, S1-S4...Switch, M...Matrix circuit.

Claims (1)

[Claims] 1 In a circuit that selectively drives multiple loads connected in a matrix according to the value of input voltage, a first reference voltage source group is compared with each reference voltage of this first reference voltage source group and the input voltage. a first voltage comparator group, a second reference voltage group, and this second reference. a second voltage comparator group for comparing each reference voltage of the voltage group with the input voltage; and means for changing each reference voltage of the first reference voltage source group by changing the output state of the second voltage comparator group. and means for selectively driving a load using the output signals of the first voltage comparator group and the second voltage comparator group.