JPS5833876A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the overlay capacity of a bump electrode by forming an impurity region of the second conductive type formed to be disposed outside the end of a Schottky coupling at the inside end. CONSTITUTION:A P type region 33 is formed in an N type epitaxial layer 32 over the outside of the end of a bump electrode 36 from the outside of the end (a) of a Schottky junction 38. Accordingly, in this case, the capacity CPN of a P-N junction 39 between the region 33 and the layer 32 and an overlay capacity C0 becomes in series connection state, and the overlay capacity of a pellet 3 becomes smaller than the conventional overlay capacity. The manufacturing method includes the steps of growing an epitaxial layer 32 on a substrate 31, and frming a P type region 33 of, for example, ring shape over the outside of the end of a region to be formed with a bump electrode 36 from the outside from the end of the region to be formed with the junction 38 in the layer 32. Then, an nsulting film 34 is formed on the surface, a Schottky junction hole is formed at the film 34 by a photoengraving process, Schottky metal is bonded to the hole, and is etched in the prescribed shape.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices, and more particularly to Schottky barrier diodes.

Conventionally, a Schottky barrier diode has a structure as shown in FIG. 1, for example. In the figure, 11 is an N+ type semiconductor (silicon) substrate, 12 is an N-type epitaxial layer, 13 is an electrode, and 16 is an ohmic contact layer.

By the way, Schottky barrier diodes generally have small capacitance, low forward voltage drop, and high speed.

A fast switching response speed is required. Among these, since the Schottky junction has low forward voltage drop and switching response speed, it can be achieved by selecting an appropriate metal. However, if the 4lets L of this Schottky barrier diode are mainly incorporated into a glass-sealed envelope such as JEDEC (Japanese Industrial Standards) No. Do-35 shown in Fig. 2, the overall capacitance iCv will be reduced. becomes difficult to do. This point will be discussed below. In this case, the capacitance cy can be considered to be the sum of the capacitance CP of the capacitor and the case capacitance Cc of the main envelope, and the capacitance CP of the capacitor is the capacitance CJ of the Schottky junction 17 and the bump It can be considered as the sum of the overlay capacitance Co between the electrode 150 and the portion protruding outward from the contact junction 17 and the N-type epitaxial layer 12 directly below it via the insulating film 3.

This can be expressed as Cy = CJ + Co + C.

Empirically, the case capacitance Cc of a Do-35 type envelope having a structure as shown in FIG. 2 is larger than that of the JEDECT To-92 case sealed with epoxy resin. In addition, the required capacitance of a Schottky barrier diode when no voltage is applied is usually G (1.0 νF. Therefore, in order to realize a small capacitance CT, K is the case capacitance C
It is most effective to reduce C.

However, at present, the DC-35 envelope l is the main type of laser diode, so the above-mentioned Pele and Tozic have no choice but to use this part as a common part. For this reason, there has conventionally been a need for a method of reducing the remaining Schottky junction capacitance CJ or the overlay capacitance Co of the bump electrode 16.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device in which the overlay capacitance Co of the bump electrode can be reduced, and therefore a small capacitance Ct can be realized.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In FIG. 3, 31 is an r-type semiconductor (silicon) base;
32 is an N-type epitaxial layer, 33 is a P-type region, 34 is an insulating film, 35 is a Schottky metal provided in the opening of this insulating film S4, and 36 is a bump electrode provided to cover this Schottky metal 35. , 37 are ohmic contact layers.

Here, the height of the bump electrode 36 is usually h>50μ.
According to the current plating method, as shown in FIG. 4, the overlay capacitance C grows 50 μm laterally outward from the end of the Schottky junction 38 (indicated by ■ in the figure).

is this distance (50 μm) from the end ■ of the Schottky junction 38
) up to (bump electrode 36) serves as a counter electrode, and the larger the lateral growth, the larger the overlay capacitance Co becomes.

Therefore, in this Schottky barrier diode, a P region 33 is formed in the N-type epitaxial layer 32 from the outside of the end ■ of the Schottky junction 38 to the outside of the end of the bump electrode 36 (indicated by ■ in the figure). is provided. Therefore, in this case, the capacitance CP)l due to the P-N junction 39 between the P-type region 33 and the N-type epitaxial layer 32 and the overlay capacitance CO are connected in series. The overlay capacitance Co' is smaller than the conventional overlay capacitance Co. On the other hand, the capacitance CJ of the Schottky junction 38 is the same as the conventional one.
T becomes smaller.

Next, with reference to Figure 1, the above 11)
A method of manufacturing a diode will be explained. First, an N-type epitaxial layer 32 is grown on an N+-type semiconductor substrate 31, and the epitaxial layer 32 is coated from outside the end of the region where the Schottky junction 38 is planned to be formed, to the outside of the end of the region where the bump electrode 36 is planned to be formed. For example, a ring-shaped P-type region 3.3 is formed over the entire region. After that, an insulating film 34 is formed on the surface, and PEP (Photo Engraving P
An opening for a Schottky junction is formed in this insulating film 34 using a method (roc@ms). Next, a desired Schottky metal 35 is attached to the opening by vapor deposition or tucking, and then etched into a predetermined shape using PEP.

Then, a cutting electrode 36 is formed by electroplating so as to cover this Schottky metal 35. On the other hand, the base 3
An ohmic contact layer 31 is formed on the back surface of 1 by vapor deposition, plating, or the like.

In the above embodiment, the position of the outer end of the P region 33 was set outside of the end (2) of the bump electrode 36, but this position was determined by the distance between the center of the young electrode 36 and the end (2) It is thought that the above-mentioned effect can be obtained at a position up to about 70 Is.

As described above, according to the present invention, an impurity of the conductivity type opposite to that of the epitaxial layer can be formed in the epitaxial layer from the end of the junction to the outside, and therefore the overall overlay capacitance can be reduced. The device can be realized.

[Brief explanation of the drawing]

Figure 1 shows the conventional system 1. A cross-sectional view showing the element structure of a Schottky barrier diode, FIG. 2 is a cross-sectional view of this diode assembled into a glass-sealed envelope, and FIG. 3 is a Schottky barrier according to an embodiment of the present invention.・A cross-sectional view of the diode, FIG. 4 is a partially enlarged view of FIG. 3. 31...N+ type semiconductor substrate, 32...N type epitaxial layer, 33...P type region, J4-...insulating film, 3
6...Schottky metal, 36...bump electrode, 38
...Si, Toki junction, 39...PN junction. Applicant's agent Patent attorney Takehiko Suzue Figure 1 (16 Figure 2 Figure 3 Figure 5

Claims (1)

[Scope of Claims] b) a first conductivity type semiconductor substrate, a first conductivity type epitaxial layer formed on the semiconductor substrate, an insulating film having an opening and formed on the epitaxial layer, The epitaxial layer 1!1 is connected to the epitaxial layer through the opening of this insulating film.
a Schottky metal forming a Schottky junction, a non-contact electrode formed to cover the Schottky metal, and an inner end located outside the end of the Schottky bond in the epitaxial layer. 1. A semiconductor device comprising: a second conductivity type impurity region; (2) The outer end of the impurity region is located at the outer end of the impurity region. , the semiconductor device according to claim 1, wherein the semiconductor device is located outside a position of 70- of a distance from the center of the toki junction to the center of the expanding electrode and the end of the expanding electrode.