JPS583248A - Manufacture of bipolar semiconductor device - Google Patents

Abstract

PURPOSE:To enable to form an ultrafine isolating region by self-aligning by forming an insulating film of the prescribed thickness on the overall surface including the groove in the vicinity of vertical part formed on a semiconductor substrate having a buried layer and etching until the surface of the substrate is exposed. CONSTITUTION:Grooves 105 (105a, 105b) in the vicinity of vertical part are formed by anisotropic ion etching by utilizing a resist pattern formed on an Si substrate having a buried layer 102, and an SiO2 film 107 is formed by a CVD method including the groove 105 sufficiently thickly as compared with a half (approx. 5,000Angstrom ) of the width of the groove. Subsequently, the surface is formed substantially flat, is then etched until the surface of the substrate is exposed, thereby forming isolation insulating regions 107a, 107b buried in the substrate, an element is thereafter formed in the prescribed steps, and a bipolar semiconductor device is formed. In this manner, the ultrafine isolation structure can be formed by self-aligning, thereby facilitating high integration and performance.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a bipolar semiconductor device,
Especially bipolar I! It relates to isolation technology and advanced manufacturing methods for IC, LIII, etc.

Conventionally, a PNN junction isolation single selective oxidation method has been generally used as a method for isolating elements in the manufacturing process of semiconductor devices, particularly bipolar ICo11. This method will be explained below using a bipolar vertical NPN transistor as an example.

First, as shown in Figure 1(a), <pH silico yj plate l°
A high concentration all buried region 2 is selectively formed, and then a semiconductor layer 1t of 1111 is epitaxially grown, a silicon oxide film of approximately too Deposit an oxidation-resistant V recon nitride film of about 1ooo1.0 Subsequently, silicon oxide film 4 and silicon nitride film JYc are photolithographically etched by 1 repattern to form V recon oxide film patterns dm, 4b, silicon nitride film pattern 1m, form lbt. Continued 1 This silicon oxide IAA turn 4m, 4b.

V silicon nitride film pattern is, as a lbt mask, a
The semiconductor layer Jt#5oooλ of ll is applied, and the same pattern dm and 4b are formed.

As a l*, lbt mask, a region of PIl ε1°tbt was formed by boron ion implantation (as shown in Fig. 1(c)).Next, thermal oxidation was performed in a steam or wet atmosphere. , selectively about 1a@j
A loi/9 silicon oxide film Fa~1@ was grown (as shown in FIG. 1(d)), followed by a V silicon nitride film pattern ja.
, jbt.

For example, remove with hot phosphoric acid V recon electrified film pattern J
Boron O ion implantation V is performed in the area directly under a to form a pace area #tube and further form a vine.
m ml area 1°, etc., of arsenic ion self-imburantity V
After forming a contact Oat in the previously formed v1 oxide film pattern 1m, a Sumitomo electrode 11. Pace electrode 12 and collector electrode 13
A vertical 11 transistor tube was constructed by forming a transistor tube (Fig. 1 (
・) In this case, the element isolation of the NPN) transistor is performed using field oxide films Fa, r@ and PI with a thickness of approximately 1#0.
It has been realized by using the l region 1m, 1b@ and t together, but if the thickness of the 5nWi semiconductor layer #O is about 1 to 2J, field oxidation using the selective oxidation method KL can be performed directly! P
The IIO group fllFc can be brought into contact and the elements can be separated. In addition, even when devices are directly isolated using a field oxide film, a channel stop PI! It is preferable to carry out ion implantation silane to remove impurities.

However, the method of manufacturing bipolar 1C1 using the conventional selective oxidation method described above has various drawbacks as shown below.

FIG. 2 is a detailed view of the O cross-sectional structure when field oxide films Fa and Fk+ are formed by forming all, )j, patterns y#a, and jbt-fJ. Unfortunately, in FIG. 2, v-silane etching of the semiconductor layer 3 is not performed. Generally, in the selective oxidation method, the field oxide film yb is 818
1'i, it is known that the oxidizing agent grows into the area under the pattern 5a (region F in FIG. 2). N4 Length of oF consisting of a portion D1 where an oxide film is formed due to diffusion through the thin 8101 film 41 under the pattern 11, a so-called bird's beak, and a portion Σ where the thick portion of the field oxide film rb wraps around in the lateral direction. For example, Blmb, pattern 51
The thickness of is 10001, and the thickness below it is 1!11011
When the field oxide film Fbl- is grown with a thickness of 1-m in the case of 10001, the width of the field region C is 81.N, and the distance between patterns 5a and 5b is 2mm. m, since F is l gl , it cannot be made smaller than 4-fold, which is a big hindrance to L8!0 integration.For this reason, recently, 81
, N, butter yja, Jbt-thicken, SIO under Kono
Attempts have been made to reduce the thickness of the film to suppress bird's beak (00 in the figure) and to reduce the thickness of the field oxidized NF hO growth layer to suppress the field oxide film's encroachment Ft. However, in the former case, the stress at the edge of the field increases and defects are more likely to occur, and in the latter case, there are problems such as a drop in field inversion voltage and an increase in wiring capacitance in the field part. There is a limit.

When the above-mentioned Bird's Beak Village occurs, the following problems occur. This will be explained to the manufacturing process 1 of a bipolar transistor using the conventional selective oxidation method shown in FIGS. 3(a) and 3(b).
A silicon oxide film 11m, Ilb is formed on the surface of the semiconductor layer 110, which will become a pre-tag region, by a conventional selective oxidation method, and using this oxide film as a mask, a boron ion implantation blind method is performed. III pace area IIjt
Then, as shown in FIG. 3(b), all the emitsuku regions are formed using the diffusion method.
Reference numeral 24 is an insulating film for forming the electrode 1. The main problems with the conventional manufacturing method using the selective acid hydration method are as follows.
The shape of the formed silicon oxide film 11m, Ilb, etc. is designed to reduce stress and the occurrence of defects in the semiconductor region near the bird peak and the shape of the so-called bird peak.
Regarding the shape of the paste region IJ, the main surface force of the semiconductor of the base weld due to the poron O ions and implantation vwn is 1 to the depth t(,c)'' of the O paste weld directly below the peak. If the depth is tD, the value of D will be smaller than CK by the thickness of the oxide film at the node peak.Furthermore, the surface of the silicon oxide film is etched during the etching process during the manufacturing process. Therefore, if a U electrode for pace extraction is formed at the tip of this (contact) peak, At will reach the pace area due to the reaction between a and V recon. The base width of the transistor directly below the main surface of the semiconductor is tA, and the base width immediately below the bird's peak is tB.
As mentioned earlier, the depth of the pace at the Node Peak part is shallow, and the depth of the emitter from the tip of Bird Peak is reduced due to the etching treatment during manufacturing. However, due to the fact that the emitter becomes deeper than other parts, and due to stress and defects generated in the selective oxidation method, abnormal diffusion of the emitter occurs, and the depth of the welding of the emitter becomes deeper, causing the normal pace. 1) The base width B directly below the bird peak is smaller than the width AK, which is undesirable as it causes a failure in the collector-emitter withstand voltage of the NPN transistor. When the one-selective oxidation method is applied to bipolar ICs in this way, it is likely to cause various device defects.

The present invention was made to solve the above problems, and
This invention aims to achieve high integration and high performance by establishing a new element isolation method, and to provide a method for manufacturing a bipolar semiconductor device.The present invention will be described in detail below. After the portion where the groove is to be formed is removed and a mask material, for example, a resist pattern is formed, the portion of the substrate exposed from the mask material is selectively etched to a desired depth to form the groove. In this case, reactive ions are used as the etching means. If etching or one-cut ion etching is used, it is possible to provide a groove with substantially straight side surfaces. The number of O grooves is 1 in the board.
1 or 2 or more grooves may be provided, and the groove osst may be changed.Continuously, after removing the master material, an insulating material is applied on the semiconductor layer including the groove so that it is at least half the short width of the opening of at least one groove. be deposited on the surface to a thickness of at least 1
Fill the two grooves up to the opening with insulating material. Examples of such insulating materials include 810. , 81. N or Mut
In some cases, low-melting insulating materials such as phosphorus sulfide glass and boron silicide glass may be used. As a method for depositing this insulating material, CVD method,
In addition, during this deposition, if the insulating material is deposited to a thickness that is half as small as the short width of the opening in the ft111 section, the insulating material buried in the groove will have an opening. A recessed hole communicating with the groove is formed, and during etching, the insulating material in the groove is etched through the recessed hole.

Note that prior to the deposition of the insulating material, the entire semiconductor layer having the groove, or at least a portion of the groove, may be treated with tll or nitrided to grow an oxide film or nitride film of degree S that does not scratch the groove. I decided to use this one together with Unakata V&.
Therefore, the obtained field region is a part of the semiconductor layer KII.
ILL board density OI! It is composed of an oxide film or nitride film and an insulating material formed by deposition, and has significantly improved element isolation performance compared to a film made of only an insulating material.
1o After the insulating material is further deposited, the whole or part of the surface layer of the insulating film is doped with a low-melting substance such as boron, phosphorus, arsenic, etc., and the insulating film is heated to melt the doped layer. , or the insulating film is partially O
A low-melting insulating material, such as bocyy@chemical glass (B
IG), phosphorus sulfide glass (PIG), or arsenic sulfide glass (IG), etc. are deposited, and this low-melting insulating film is melted. In adopting this method, the deposition conditions of the insulating material are
If the part corresponding to the groove becomes eye-shaped, the concave part can be flattened and flattened, and some of the insulating material that remained during the edging of the fruit surface will become below the level of the opening. It has the effect of preventing inconvenience.

Next, the etching solution is removed in the groove where the semiconductor layer portion other than the groove is exposed without using the insulating film t mask material deposited on the semiconductor layer, thereby forming a field region tube with the insulating material remaining in the groove. As an etching means in this process,
For example, a whole surface etching method using an etching solution or plasma etching method, a reactive ion etching method, etc. can be employed. Thereafter, active elements such as bipolar transistors are formed in the element formation regions separated by the field regions to fabricate a bipolar semiconductor device tSS.

According to the present invention, a groove is provided in a semiconductor layer, and an insulating material is applied to the entire surface of the semiconductor layer, including at least one groove O. After being deposited to a thickness that is more than half the width, an insulating film is formed! By etching in the trenches where the semiconductor layer parts other than the trenches are exposed, it is possible to leave an amount of insulating material in the trenches with self-alignment V without having to worry about mask alignment, and from this it is possible to form a field region, as shown below. It is possible to provide a bipolar semiconductor device having a unique kO effect.

(1) Since the area of the field region is determined by the area of the trench previously provided in the semiconductor layer, the desired fine field region can be easily formed by reducing the area of the trench, resulting in high integration. A bipolar lid semiconductor device can be obtained.

(2) The depth of the field region is determined by the rectilinearity of the groove provided in the semiconductor layer, regardless of the area, so the depth t can be arbitrarily selected, and current leakage between elements can be prevented from occurring in the field region. It is possible to obtain a high-performance O-pibok type semiconductor device with reliable blocking.

(3) After providing the I11 tube and selectively doping the channel stopper impurity into the groove, the impurity region This prevents lateral rediffusion from reaching the buried layer of the element forming region or the active region of the transistor O, thereby effectively preventing reduction in the element forming area O. In this case, if the impurity is doped by ion implantation KL, the impurity ion-implanted layer can be formed at the bottom of the tube groove, and even if the ion-implanted layer is re-diffused, it will still remain in the surface layer of the element formation region (the active part of the transistor). Since there is no collapse due to Kt, it is possible to prevent the effective reduction of the element formation area, and also to prevent the active region of the transistor from being inhibited by the impurity region.

(4) If the field region is formed by leaving the insulating material in all of the grooves, the substrate will be flattened, so it is possible to prevent the occurrence of breakage when forming the electrode wires later.

Next, the second invention of the present application will be explained in detail.

An insulating material is deposited on the semiconductor layer through a process similar to that of the first aspect of the present invention described above so as to have a thickness that is at least equal to the short width of the opening O of one groove provided in the semiconductor layer. Next, at least one of the area of the insulating film including a part of the trench placed in the opening t from the insulating material PC, or the area of the insulating film that is to become a field area other than the trench, is removed. , ``For example, cover with a regimen'' pattern, etc. Next, etching is performed until the mask material and the semiconductor layer portions other than the groove are exposed, and the inside of the groove is kI! A field region is formed by leaving the edge material on the semiconductor layer other than the groove. In this case, the field region formed on the semiconductor layer other than the groove is integrated with the field region of the groove. I also meet those who have been
Thereafter, active elements such as bipolar transistors are formed in the element formation regions separated by the field regions to manufacture a bipolar semiconductor device. .

Therefore, if the second invention of the present application is implemented, in addition to the various effects described above, the field region embedded in the conductor layer and the field region on the semiconductor layer other than the groove portion can be integrated with the field region or A bipolar semiconductor device having separated field regions of different shapes can be obtained.

Next, the present invention is apl bipolar transistor O made W
An example in which iK is applied will be explained with reference to the drawings.Example 10] First, as shown in FIG. , After growing an epitaxial semiconductor layer 103 of Knll to a thickness of about 2.5 pm, the semiconductor layer 1
Eri resist pattern 1o4 by photolithography on 030 surface
m, 104 had +10def remaining amount. Next, this pattern Jung Regis) 104m, 104b.

Using 10dc as a mask, perform anisotropic active ion etching on the semiconductor layer 101f by etching the silicon until it reaches the substrate 101 of sP711.
Therefore, the grooves 101m and 101 have a width of about 1μ and a depth of about 3μ.
bYt is formed and the nW semiconductor layer 101f is separated into islands (as shown in FIG. 4(b)). 1oti*.

It is preferable to form xoibt〇104b,1
e4*t@After Ll, CVD-810゜1n1erts
Element isolation O groove 1m1m, half of 1e5bO width (approximately Io
oo1>x is also deposited sufficiently thickly0 At this time, CV
D-110 is gradually deposited on the inner surface of the groove, and the groove 1t
ll*, 1#lib is enough for 1t, CVD-810
, Membrane J o t.

The surface is flat and buried. Note that during O deposition, high temperatures are used as in the selective oxidation method.

Since long-term O thermal oxidation is not required, PM range 1
Rediffusion to mgm, 106 hardly occurs ◎Continuously, CVD-110, film 101 is coated with ammonium fluoride in the groove part J.
#The entire surface of the silicon semiconductor layer 1010 other than Ja and Jljb was etched until it was exposed. At this time, as shown in FIG.
d) OCVD Blo on the semiconductor layer 1exo
W film 1ov part O film thickness part film part removed, groove part 1m1h,
0 CYD-1110 within 185% remains, thereby forming a trenched field region J in the semiconductor layer 10a.
#Fa and f#Fb are formed.

Next, in the semiconductor region separated by the field regions J#Fa and J#Fb, a pH pace region xezt is formed using poron ion implantation V using the resist block method, and approximately An insulating film 1ett of aoooi is formed, and an opening is made in this insulating film 189 above the diffusion window of the collector and arsenic by photolithography, and ion implantation of arsenic is performed to form a single ivy! III area 110°Nl which becomes the collector extraction part
l region 111 is formed. NextKPII base area 1#
By forming an opening for 1, depositing an electrode material such as U on the semiconductor surface, and patterning this electrode material by photolithography, a pace electrode 112 and an ivy electrode 11 are formed.
J, Collector electrode 114t- is formed to manufacture an APM bipolar transistor (as shown in FIG. Can be made into extremely small areas,
The element isolation region tm occupied in the IC was small, and a high degree of integration was achieved.Also, as shown in Figure 4 (), there is no step difference between the element isolation region and the element formation region, and the electrode is flat. Example 2 First, as in Example 1, the PIl semiconductor substrate z-1
A high sum implantation layer 102 of selective KnllO impurity is formed on the layer 102, and all epitaxial semiconductor layers 203 are formed thereon.
Then, for example, CVD-810,1 is deposited on the semiconductor layer gas, and this pattern is engraved by photolithography.
VD-Blow film pattern yj*4m-204-t mask for semiconductor layer 1st, 4% λ-based reactive on-etching, width is about 1 pitch, depth is about 2
At this time, these grooves gas and tart are connected in a figure-80 shape. The resist pattern 106 is left behind, and the resist pattern 106 is removed by CVD-1.
Using Poron's ion-fighting imbranti V as a 110 membranous putter y1114m-2044 isotube mask, selective 1cpHo regions zera and zorbtN were mapped (as shown in FIG. 6(a)).

■ Next, resist pattern 2 on the surface of the semiconductor layer 201
Remove 06, then heat #a, m to 1, P
By re-diffusing the ill regions 206m and 106h, the n1iO semiconductor layer 1-J, which is the planned element formation area, is
Furthermore, the semiconductor layer gos
Half the width of the groove gas... formed inside (leopard!!0
OOX) z4J4 sufficiently thick, CVD-11i0. membrane 2
Deposit #1. At this time, Fig. 5(b) CV like o
D-1110, the surface of the film is flat, the aforementioned CVD-101 film 5eat, the semiconductor layer zes
In the trench where the o'11 plane is exposed, etching with ammonium fluoride etc. is performed to form the trench part KCVD-81012ea of the semiconductor layer J#1.
Leave m, 20Rh, 20Mm f. Next, after forming a %PIlO base region j11 using poron ion implantation using a resist plotter method, an insulating film 11- of about aooool is formed in the chamber of the semiconductor layer gas.
After forming a tube, selectively remove the insulating film of the electric ivy and the insulating film of about 5001 of the pre-tatable area using a photolithography method, and perform ion implantation V etching etc. of the k element.
Area 211 of Aituta and NainIl. A region 111 of *fM, which becomes a collector extraction portion, is formed. then ptttto
An open tube is formed for the base region 111m, an electrode material such as Ku is deposited on the surface, and this electrode material is pattern-engraved by photolithography to form a pace electrode.
The emitter electrode 114 is formed by forming a full-length electrode.
pa Pypolar cilandystata was constructed (Figure 5)
@)Illustrated) 0 In the above-mentioned fabrication method of Example 10, the element separation of the F range metal is reduced, and an integrated circuit with good flatness and properties can be produced.The features of this example are as follows. , element isolation is achieved by combining the CVD BSCh buried in the groove and the PH10, and furthermore, the base region 209 and the collector electrode extraction region 212 are realized by the CVD BSCh buried in the groove.
-10! It can be formed in a self-aligned manner by engineering, and furthermore, the junction capacitance tube between the pace collectors can be made small.

Example 3 First, as shown in FIG. 6(a), an n-type silicon conductor layer 2 was formed.
The width of the opening was 61mm by photolithography using reactive ion etching.

A groove portion 1611 was provided which intermittently changes to 55158 m at 80 m. Note that the width of the opening in the groove 304 is 81
(0 with the relationship St < Hm, then 810. tl
- Deposited using the cVD method so that the 1/2 area of the opening width of the opening area is slightly thicker by 8 mm, so that the opening width of the groove part 3040 is 81+S1
After fully filling the O part KCVD-810° film and depositing mK on the inner periphery of the opening "S", the semiconductor layer zoz
When etching with ammonium fluoride to the thickness of the upper OCVD-1110g film, as shown in Figure 6 (h) 0, the opening width was Si, the S part remained (KcVD glow film sex), and the same width part (BaK) was removed. A carved shape of an element isolation region with an opening was obtained.

Example 4 First, the element formation pre-chamber part K on the pro semiconductor substrate 11411
mlOII-containing layer aazt on top of mMO
Grow the epitaxial semiconductor layer 411 in the desired area! grooves 4#4*, each having the same width 01111, connected to
41db, 4fld*f (as shown in Figure 7(, ))
0 Then, as shown in FIG. 1(b), the above-mentioned O groove part aeaa
~CVD-110m which is sufficiently thicker than half the width of #4.
Following the deposition of the film 4-5, a resist pattern mega, aeH, tag was left in the desired area by photolithography (as shown in Figure 7 (@)). @f As a master, etch the VD-110m film 4#ri with ammonium fluoride, etc., and use it as an element isolation region.CVD-1101405
m.

405, 4m5m, O field area for wiring J#J4
．． J##., 4081 was formed. In this way, the field region is sufficiently thicker than half the width of the trench, can be formed at any location, and can be used as a wiring region.Example 5 ω First, the top 0 element formation area of the pg semiconductor 5aies is formed. Form a K n tri polarization layer Halt, and then form a K n tri
lli epitaxial semiconductor layers are grown and connected to each other at desired portions, grooves iea*ai each having the same width and number of values are formed.
Epitaxial semiconductor layer 1m with eib and sea@ provided
1h to 5o11 were separated, and a resist pattern of 1501m and 1elhf was formed by photolithography (as shown in FIG. 8) followed by %vyst pattern 1#l.
*, as a 1m1hf mask, the semiconductor layer sos@ts of the field region formation preliminary area was edded to the desired depth, and then the resist pattern was removed (81st
11(h) shown) 0 hit, then groove 1ads~104
・Thickness less than half of O radiation <, CVD-1110, film x #
gtj11mlt (as shown in FIG. 8(0)) 0 Then, as shown in FIG. 8(d), a tiny resist pattern was left by photolithography on the area where the field was to be formed. (Turn 101
Using a mask as a mask, a semiconductor layer 1 of nm thickness is formed using fluoride film or the like.
Etching was performed until the surfaces of the 02m, 102b, and 503 layers were exposed, and an element isolation region 511 and an isolated field region 5asht were formed (as shown in FIG. It can be formed with a thickness larger than that of the semiconductor layer 1t) Ia, 1ll.
Since the surface of lk, 1014 and the surface of field region 5ash can be made at the same level, flatness can be maintained and zero-level disconnection of wiring can be prevented.

Note that the bipolar semiconductor device OI! according to the present invention! 1″
In the m method, P! ! ! ! PIN layer provided on semiconductor substrate, pH semiconductor substrate K
n II epitaxial layer t-2 times stacked or Pal epitaxial on the same substrate! A layer obtained by laminating a axial layer and an *m-epitaki layer may also be used.

In manufacturing the bipolar semiconductor device according to the present invention, as in the above embodiment, <PII semiconductor substrate C) n II
In addition to forming a 1ulk bipolar transistor in the semiconductor layer, for example, Pl! mpn ) Rungis by triple diffusion method on semiconductor substrate! ! It can also be applied when forming.

As described in detail above, according to the present invention, an arbitrary and moldy field region can be formed by self-line mainly in the groove portion f′ provided in the semiconductor layer without taking the mask alignment margin t. We are able to provide a method for manufacturing bipolar semiconductor devices with high integration, high reliability, and high performance.

[Brief explanation of drawings]

Figure 1 (- to (-) are the conventional selective oxidation methods! A cross-sectional view showing the manufacturing process of the vertical type *p*) Kunjista, Figure 2
The figure is a cross-sectional view to explain the problems of the conventional selective oxidation method, and FIG.
Cross-sectional views, FIGS. 4(&) to (・) are cross-sectional views showing the 1lpn bipolar transistor O1l fabrication process in Example IK of the present invention, and FIGS. S(,) to (,) are Example 2 of the present invention.
All (a) and (b) are cross-sectional views showing the manufacturing process of the mpn bipolar transistor in Embodiment 3 of the present invention. FIGS. 7(a) to 0) are cross-sectional views showing step 1 of forming a field range of a 1pfl bipolar transistor in Example 4 of the present invention.
Figures (,) to (-) are cross-sectional views showing the step of forming a field region of an mpn bipolar transistor in Example 5. 1019201.401.5111...Plf semiconductor substrate, ioz, zoz, ioz, 1az-/n+ type assumption layer, zox, zex, xos. aos, 5ash ~ saga-n'tll epitaxial semiconductor layer, Jljfa, 106b, IrO2
, 104, 404h~404e, 504*~MO4e
...Groove, 1#1゜108.408, j06...
・CVD IiO* film, 74FFIl, Ielrk
, 2111m"-1t)Re, 201,401a~4
01e, 106h, 106c - field area, 1
011.209...PW1 region (base), 110°211...n+ type region (emitter region), 111°2
12...n+dust area collector extraction part), 11:I,
113,114,213,114°215... Electrode. Applicant's agent Patent attorney Takehiko Suzue (a) 6th v! J (a) (b) (d) Figure 7

Claims (1)

[Scope of Claims] (1) A step of forming a second conductive type semiconductor layer on the semiconductor substrate of the first conductive gourd, and forming a semiconductor layer of the first conductive type and the second conductive gourd. or the second conductive II
a step of forming a second conductive irrigation region in the O semiconductor layer; and a step of providing at least one groove portion having vertical or nearly vertical side surfaces in a desired portion of the semiconductor layer of the second conductive lid. 1. Depositing an insulating material on the semiconductor layer including the trench to a thickness that is more than half the short width of the opening of at least one trench, and etching the insulating film in a trench where the semiconductor layer is exposed. Insulating material t! in at least one groove! A method for manufacturing a bipolar semiconductor*t characterized by comprising a stone process for forming a field region in which the semiconductor layer remains Claim 1, characterized in that the gold surface of the first semiconductor layer or at least a part of the groove portion is oxidized or oxidized to grow an oxide film or a honeydew film that does not scratch the groove portion. A method of manufacturing the bipolar semiconductor device as described. (3) after providing a groove in the semiconductor layer of the second conductivity type and before depositing the insulating material, selectively doping the groove with impurities having the same conductivity as the semiconductor substrate of the first conductivity type; The bipolar semiconductor device according to claim 1 or 2, wherein the rL9 region formed by this doping is brought into contact with the insulating material of the groove and the first conductive semiconductor substrate. OIL production method. (4) After depositing the insulating material, the entire or part of the surface layer of the insulating film is doped with a low-melting substance, heat treatment is performed to melt the doped layer of the insulating film, and then the insulating film is etched. A method for manufacturing a bipolar original semiconductor device according to any one of claims 1 to 3, characterized in that: (5) After depositing the insulating material t1, a low-melting insulating film is deposited on the entire or part of the insulating film, this low-melting insulating film is melted, and then these insulating films are etched. A method for manufacturing a bipolar semiconductor device according to any one of claims 1 to 3. (6) Step 1 of providing at least one groove portion having a direct or near-direct side surface in a desired portion of the semiconductor layer of the second conductivity type; A step of depositing the insulating film in a layer having a thickness of more than half of the short width of the opening O, and at least injecting the insulating material in the opening trench to form an insulating film O region including a part of the trench or a field region other than the trench. Insulating film O
After covering at least one of the regions with a pipe mask material, the insulating film is etched until the mask material and the O semiconductor layer other than the trench are exposed, and the insulating material is left in the trench to cover the field region t1 and the field region other than the trench. 1. A method for manufacturing a bipolar semiconductor device, comprising a step of forming a tube. (7) After sanding the groove in the semiconductor layer of the second conductive layer and before depositing the insulating material, oxidize or write the etched surface of the semiconductor layer or at least a part of the groove to prevent the groove from being blocked. A method for manufacturing a bipolar conductor device according to claim 6, characterized in that a single oxide film or nitride film is grown.