JPS583246A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate the formation of an exfoliating structure by utilizing the selective etching of an insulating film to thickly form by self-aligning an oxidized film on an isolation. CONSTITUTION:A thick oxidized film 14 of the rescribed pattern is formed on an Si substrate 3, impurity ions are selectively implanted in the desired region to form an isolation region 16 and a collector contacting region 17, and a thinly oxidized film is formed on the regions. Then a nitrided film 18 is formed on a thin oxidized film except the isolation region, the film 14 is entirely removed with the film 18 as a mask, and a thick oxidized film is formed by selective oxidation on the isolation region. In this manner, a semiconductor device of the structure formed thickly in the oxidized film on the isolation can be readily manufactured by self-aligning.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to a method for manufacturing a bipolar semiconductor integrated circuit having a structure in which a surface insulating film is buried inside a semiconductor substrate.

In a bipolar semiconductor integrated circuit, necessary circuit elements such as transistors, resistors, and diodes are formed in an electrically isolated semiconductor region, and the intended electrical circuit is formed on an insulating film that covers the semiconductor surface. You can get it by wiring it like this. Conventionally, this insulation isolation has been performed mostly by PNN association, but recently it has become more and more highly integrated. upon request.

Various isolation binding methods have been proposed.

One of these methods is to use KJa directional etching to form grooves in the laser diode area, and the second method is to convert the silicon semiconductor in the isolation area into a silicon oxide film by thermal oxidation. The third method is to use an insulator isolation run and a junction isolation run in combination, and each method is put into practical use depending on the application. The third method above requires less time for thermal oxidation;
Another advantage is that mask matching is easy. An example of this method is shown in Japanese Patent Publication No. 52-4433'3, and its outline can be explained as follows: For example, as shown in the tIf-1 diagram, N+ buried diffusion 2 is applied to a P-type silicon substrate 1, and N-type silicon 2 after forming 2 pieces of epitaxial F@3
A silicon nitride film 4 is formed on the surface as an oxidation-resistant film.

This nitride film 4 is formed separately so as to cover the isolation region, the collector surface region, and the paste and emitter surface regions.

Next, thermal oxidation is performed to form a buried insulating film 5 as shown in FIG. 2, and then an oxide film 6 is left on the surface as a mask for isolating diffusion to expose the isolation surface area. High precision alignment is not required for mask alignment at this time.

Next, as shown in FIG. 3, the oxide film 6 at the center is partially removed using the same loose mask to form a pace region 7.
Subsequently, as shown in FIG. 4, a part of the base region 7 and the entire collector surface region are exposed and emitter diffusion is performed. It is clear that the above impurity diffusion can be carried out by applying the ion implantation method. In the above manufacturing method, the thick insulating film 5 provides alignment margin, so alignment is easy, and the insulating film 5 is an epitaxial layer. 3, and a PN junction for isolation is located below it.

If the above manufacturing process is carried out using only ion implantation, it is essential to provide a thin isolation film to reduce damage to the semiconductor surface as much as possible. - Providing an insulating film every time a contact diffusion (this is done to reduce the collector series resistance), a space diffusion, and an emitter diffusion will lead to a disadvantageous process. Therefore, ``the non-applicant is %
No. 64,816 discloses a method that can simplify this. With the above isolation structure, it is absolutely impossible in the isolation region! In order to cope with the problem that the parasitic capacitance of the wiring passing through the area increases due to the thinness of the oxidized piece, Japanese Patent Application No. 1983-67611 proposed a method for increasing the insulating oxide group in the isolageron area. Proposed.

This will be briefly explained with reference to FIGS. 4 to 8.
Fourth! Silicon nitride films 4A, 4C, and 4B are left in isolation 9A area E + collector contact area F and space area G as shown in FIG.
0OA field oxide film 5'lr: Formed 9 Then,
Plasma etching is performed, leaving a resist ft on the surface other than 4A, to remove only the silicon nitride film 4A, as shown in Figure fPJ6.

Surface 8 of the isolation affected area using the resist as a mask
Then, phosphorus ions are implanted into the surface 10 under the collector contact region F using the resist 9 as a mask, as shown in FIG.

The remaining nitride films 4C and 4B'e are used as masks to perform thermal oxidation and ion-implanted impurities such as boron and phosphorus are diffused into the substrate to form a P-type isolation region 11 and a collector contact diffusion region 12. At this time, oxidation progresses from the 9th surface, and a sufficiently thick oxide film 13 is formed on the 8th V p-type isolation region 12.

In the process shown in Fig. 6, the nitride film 4A was removed by simple plasma etching, but this can of course be done using normal hot phosphoric acid. It will grow and require a window opening process. In order to omit the vapor phase growth process Fc, the upper layer oxidation Fp which was removed from the nitride film in the process shown in FIG. 4 is left as is.

After the step shown in FIG. 5, only the oxide film on the purple film 4A is etched, and only the nitride film 4A may be removed using 7i acid, but in the step shown in FIG. There is also the problem that ion implantation is difficult because an oxide film remains on the surface.In this process, after the seventh step, all surface oxidation is removed and hardened.

By field oxidation as a 4B't mask.

It is also conceivable to obtain a Naraga similar to that shown in Figure 8.

The present invention further improves the above-mentioned method 1, and makes it possible to easily manufacture a semiconductor device with a structure in which the oxide film on the isolation layer is thick by self-alignment. It is something to do.

In the present invention, a first layer is formed on the surface of the semiconductor substrate, which is thin at least on the isolation region and the paste formation region and thick on the other regions.
forming an insulating film, and forming an insulating film and an etching pattern 1F on at least the first assembly layer facing above the base shape g region;
A second insulating film with a different temperature is buried and formed, and the second insulating film is used as a mask.

The first insulating film containing gold is removed except under the second insulating film.

The method is characterized by including a step of forming an insulating film on the surface of the semiconductor substrate including the isolation region using the remaining first insulating film or the second insulating film as a mask.

The present invention will be described in detail below with reference to embodiments shown in the drawings.

9 to 17 are cross-sectional views of the substrate at each step according to the manufacturing method of the present invention.

(1) See Figure 9 N-type buried diffusion is performed on the P-type silicon substrate surface.

A silicon oxide film 14 of approximately 600 OA is formed on a substrate on which an N-type silicon epitaxial layer 3 is formed, and windows are formed in an iso-rake region E, a collector contact formation region F, and a paste formation region G.

(2) Refer to FIG. 10. Photoresist 15t is contacted and only the isolation area E is opened. Thereafter, boron is implanted into the surface 16.

Similarly, surface 17 of collector contact formation region F
ion implantation of phosphorus.

(4) Refer to FIG. 12, by thermal oxidation and vapor phase growth, an oxidized layer 14a for shin protection is formed at least on the exposed surface of the silicon. Oxide film 14
The thickness may be about 100 OA.

(5) Refer to Figure 13. Spread a silicon nitride film 18 on the entire surface as an oxidation-resistant film at a thickness of about 100
Vapor phase growth is performed on the H level of A. Apply a photoresist 19 and remove the nitride film 18 at least on the isolation region E.
remove. For this etching, plasma etching can be applied. 5i for Brehner type etcher
ft>stN>st, Si>S for barrel type etcher
It is preferable to use a barrel type etcher having an etching rate in the relationship iN >> S l O *.

Since the silicon surface is covered with a protective oxide film 14m, the silicon surface is not etched. point of ren,
If a barrel type etcher is used in the process shown in FIG. 6, silicon will be etched more than necessary, but this problem does not occur in the present invention.

(6) Refer to the mt4 diagram.A photoresist 20 is applied again, and the resist (tV#) on the protrusion is removed by ashing or ion milling with argon or the like.

(7) Refer to Fig. 15 If plasma etching using CFa is performed in the state shown in Fig. 14, the exposed 9-oxide film will be removed as shown in Fig. 15. When using milling, l! Then, ion milling is continued to produce the state shown in FIG. 15.

(8) After removing the resist 20t (see FIG. 10), use the nitride film 18 as a mask to remove all the oxidized $14f (9) Perform selective oxidation using the nitride film 18 as a mask, and remove approximately 60
A field oxide film 21 from 00 to 9000 is formed.

In this thermal oxidation process, the isolation region 221
A collector contact diffusion region 23 is formed in the same manner as in FIG. After that, the chemical film 18 is removed, and the base is diffused.
Apply emitter diffusion etc. to complete the two-body integrated circuit structure.
Although a large integrated circuit can be obtained, the process may be modified with some modifications. In other words, to obtain the structure of FIG. 9, instead of forming and etching the oxide film 14, E.
In each region F and G, a silicon nitride film may be deposited and subjected to selective oxidation to obtain the ws structure shown in FIG.

Further, in place of the ion implantation process & in the steps of FIGS. 10 and 11, well-known diffusion from spin-on glass may be used. In this case, a step of removing the glass film outside the desired diffusion region is necessary.

FIGS. 18 to 23 show semiconductor integrated circuits according to other embodiments of the present invention! To! (1) Refer to FIG. 18. A silicon nitride film 24 having the same cross-sectional shape as FIG. 12 is formed on the surface of the silicon epitaxial layer 3. To achieve this, a silicon nitride film with a thickness of 4000 A may be deposited in advance and etched at predetermined portions, but it is also possible to apply a silicon nitride film with a thickness of 3500 A to only the protrusions. After that, a silicon oxide film may be deposited on the entire surface to a thickness of 50 OA.

(2) Refer to FIG. 19, a second material 25 having different etching characteristics is buried in the groove of the silicon nitride film 24. The second material is photoresist and phosphorus silicate glass.

Silicon oxide Il# (Sift) or the like can be applied.

In this case, lift 1-off, ion milling, and plasma control etching can be applied.

(3) Refer to FIG. 20, apply a photoresist 26, open a window in the isolation region, and remove the second material 25 using the photoresist 26 as a mask. Perform ion implantation with or without removing the thin silicon nitride film covering the silicon surface, and perform the same ion implantation as shown in 1. j Now.

(4) Refer to FIG. 21. In the same manner, mask off the resist 27 and perform the ion implantation 17 at the collector contact portion.

(5) Embed the resist 27 in Fig. 21 of the 22nd tVlu irradiation in the collector contact part of the Merney I site in the same manner as in Fig. 19 of the set
Immediately, leaving the silicon 9 oxide film under the two-layered metal layer 25, everything else is removed.

(6) Referring to FIG. 23, the second material 25 is removed and selective oxidation is performed using the silicon 9-oxide #24 as a mask. In this way, field oxide #21 of uniform thickness is formed even on the isolation region.

In the above embodiment, if the oxidation-resistant film remains under #1, the structure shown in FIG. A three-layer structure of nitride film and silicon oxide film may be used.

The ash example is a process cross-sectional view showing how to obtain a structure substantially the same as that shown in FIG. 19.

(1) Refer to FIG. 24. On the surface of the silicon epitaxial layer 30,
A silicon nitride film 28.500A polycrystalline silicon 2
A silicon nitride film (9) with a thickness of 9,250 OA is formed and etched as a resist aH-v mask onto the silicon nitride film 301 in portions such as the Islay scene region, the collector contact region, the space region, and if necessary the resistor region.

At this time, if a facing electrode type plasma etcher is used, the etching rate of polycrystalline silicon is ti50A/
Since the etching rate of the silicon nitride film is 200 A/min, polycrystalline silicon can be used as a stopper.

The resist 31 is removed after 'f'.

(2) Selectively oxidize the polycrystalline silicon 29 (see FIG. 25). At this time, the thickness of the oxide l layer 320 formed is 1500A. A resist 33 is formed, and the oxide film 32 exposed by opening a window in the isolation region is removed by phosphoric acid etching or the above-mentioned counter electrode type plasma etching. At this time, the silicon oxide film #' is etched at a rate of 1500 A/min.

Next, ion implantation for forming an isolation layer is performed. This step can be replaced by the first method. That is,
The polycrystalline silicon 29 is not selectively oxidized first, and the resist 3
31, polycrystalline silicon 29 is etched as a mask, ions are implanted to form an isolation layer, the resist is removed, and polycrystalline silicon 29 is selectively oxidized to obtain a structure similar to that shown in FIG. be able to.

(3) Hereinafter, the same process as shown in FIGS. 21 to 23 is applied. In this case, 3 ot silicon nitride film
281 An etching process for the polycrystalline silicon 29 is required, but a barrel-type plasma Φ etcher can be used for this to remove the silicon nitride film.

The etching rates for polycrystalline silicon and silicon oxide films are 200 A/min, 2000 A/min, and ~OA/min, respectively.

As explained above, in the present invention, the nitride film formed on the isolation area is removed, the nitride film left on the paste formation area and the collector contact formation area is used as a mask, and the nitride film formed on the isolation area is removed. In a method of manufacturing a semiconductor device in which a thick field oxide film is formed on an exposed surface of silicon, an oxide film providing protrusions is provided on the surface except for an isolation region, a collector contact formation region, and a paste formation region, and then each of the regions is After covering the exposed silicon surface with a thin protective oxide film, silicon nitride yA is provided over the entire surface, and when nitriding is performed on the isolation carbon region, only the nitride film can be removed.

Furthermore, by utilizing the step of the previously formed oxide film, the nitride film can be left only on the collector contact formation region and the paste formation region, and this can be used as a mask to perform the intended field oxidation. .

[Brief explanation of the drawing]

1 to 3 are cross-sectional views of a silicon substrate in the conventional manufacturing process of a semiconductor device, and FIGS. , FIGS. 9 to 17 are plan views showing various parts of the manufacturing process of a semiconductor integrated circuit according to an embodiment of the present invention, and FIGS. 18 to 23 1
Semiconductor collection f#i to 1 which is another embodiment of 9-shot lid 1
Plans showing various parts of the road meeting/case process, Figure 24 to p=2
Figure s is a cross-sectional view of the substrate in the process of aligning the axes of a semiconductor integrated circuit according to another embodiment of the present invention. In the figure, 3 is an N-type epitaxial layer, 14 is an oxide film, and 16 is an oxide film.
is an ion implantation region tx7 for forming an inlay 4 ion implantation region t18,2 for forming a collector contact
4,28.3 (19th M, ff119.20,26,2
7, 31, 33#i photoresist, 21#'i field oxide film, 22#'i, isolation silicon region, 23
25 is a collector contact diffusion region, 25 is an #I2 insulating material gate, 29 is polycrystalline silicon, and 32 is a silicon oxide film.

Claims (1)

[Claims] A first insulating film is formed on the surface of the semiconductor substrate, the first insulating film being thin at least on the isolation region and the paste forming region and thick at the other regions, and the thin first insulating film being at least on the base forming region. A second insulating film having different etching characteristics from the first insulating film is buried and formed thereon, and using the second insulating film as a mask, all of the first insulating film except under the second insulating film is removed. Then, using the remaining first insulating film or second insulating film as a mask. 1. A method of manufacturing a semiconductor device, comprising the step of forming an insulating film on a surface of a semiconductor substrate including an isolation region.