JPS583226A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS583226A
JPS583226A JP10188281A JP10188281A JPS583226A JP S583226 A JPS583226 A JP S583226A JP 10188281 A JP10188281 A JP 10188281A JP 10188281 A JP10188281 A JP 10188281A JP S583226 A JPS583226 A JP S583226A
Authority
JP
Japan
Prior art keywords
film
substrate
mask
diffusion
heat treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10188281A
Other languages
Japanese (ja)
Inventor
Kiyoto Watari
渡り　清人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10188281A priority Critical patent/JPS583226A/en
Publication of JPS583226A publication Critical patent/JPS583226A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer

Abstract

PURPOSE:To prevent the breakage of a film by a method wherein a silicon hydroxide film containing impurities and a solvent is applied on a substrate through a mask with a predetermined pattern and the opening section of the mask is formed in taper shape when the impurities are diffused in the substrate by applying heat treatment. CONSTITUTION:An SiO2 film 2 serving as a diffusion mask is formed on a P type Si semiconductor substrate 1 and etched halfway by using a resist film 13 as a mask. Then, with the film 13 slightly ashed by using plasma-asher, the opening section of the film 13 is expanded. At that time, etching is again performed. After forming an opening pattern with a taper shaped section on the film 2, the substance dissolved Si(OH)4 and As2O3 including an N type impurity in acetone is applied to the surface to form a layer 3. Next, heat treatment is applied to make an N type region 5 by diffusing N type impurity As into the substrate 1. Therefore, a tapered edge 7 exists. Thus, the film 3 will not be broken even if the film 3 contracts at the time of heat treatment.

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法に係１１．４１に基板上
に塗布したシリカフィルムを拡散源として基板内に不純
物拡散する工ＩＩＫ関するものである◎半導体装置の伽
造工＠Ｏ一つに、拡散１薯があるが、例えばバイポーラ
トランジスタの壊没層拡散やコレクタコンタクト拡散等
のように、高濃度の不純物を拡散する場合、一般にシリ
カフィルム轡から０１ｊＩ相拡散が利用されている。こ
れ社気相拡散に比べて拡散抵抗のばらつきが小−ＩＡＩ
／％勢の利点から、高濃度の拡散工１で利用される。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and relates to a process IIK in which impurities are diffused into a substrate using a silica film coated on a substrate as a diffusion source in 11.41. One type of process is diffusion, but when diffusing high-concentration impurities, such as collapse layer diffusion or collector contact diffusion in bipolar transistors, 01jI phase diffusion from a silica film is generally used. has been done. This method has smaller variation in diffusion resistance compared to gas phase diffusion - IAI
/%, it is used in high concentration diffusion process 1.

菖１図の断面１１によ〕その固相拡散の一般例を説明す
る０１はｐＨの半導体基板、２は８ＩＯ８よ〕なる拡散
ｉスフ用被膜で、被＠２上にシリカフィルム４を塗布す
る＠シリカフィルム４は不純物と溶剤を含有するシリコ
ンの水酸化物膜で、例えにスピンコーティングによｊｌ
塗布される。そＯ後熱４６１１を施こして今エア及び拡
散を行なう０その時膜４が収縮してしまい、例えに被膜
２０角２′の薄い部分で切れることがしはしはある０す
なわち破線４で示した様に収縮し、拡散領域５が形成さ
れない部分（Ｉｔ中６）ができてしまい問題となってい
た。この収ＪＩＩは熱処理前Ｏ膜厚ｔ、と熟熟理後の膜
厚ｔ、との比１＊／１＋が、０，６〜０．７になる＠度
に生じる◎ 本発明株上記従来の欠点を除去し、拡散源であるシリコ
ン酸化物の膜の＠縮に伴う切断を防止することを目的と
する・ 本発明線半導体基板上に拡散マスク用被膜を所定のパタ
ーンに形成し、該被膜上に不純物及び溶剤を含有するシ
リコンの水酸化物の膜を撒布し、熱処理を施こして該基
板内に前記禾細物を拡散する工程において、前記拡散マ
スク用被膜の該基板を露出せる部分の断面をテーパ状に
する工程を含むことを特徴とする半導体装置の製造方法
を提供する。A general example of solid phase diffusion will be explained with reference to cross section 11 in Fig. 1. 01 is a pH semiconductor substrate, 2 is a diffusion coating made of 8IO8, and a silica film 4 is applied on the coating @2. @Silica film 4 is a silicon hydroxide film containing impurities and solvent.
applied. After that, heat 4611 is applied, and air and diffusion are performed. At that time, the film 4 shrinks, and for example, the film 20 may break at the thin part of the corner 2', as shown by the broken line 4. This caused a problem in that a portion (6 in It) was formed in which the diffusion region 5 was not formed. This JII occurs when the ratio 1*/1+ of the O film thickness t before heat treatment and the film thickness t after ripening becomes 0.6 to 0.7. Aiming to remove defects and prevent cutting due to shrinkage of the silicon oxide film, which is a diffusion source. A diffusion mask coating is formed in a predetermined pattern on a semiconductor substrate of the present invention, and the coating is A portion of the diffusion mask coating that exposes the substrate in the step of spreading a silicon hydroxide film containing impurities and a solvent thereon and performing heat treatment to diffuse the impurities into the substrate. Provided is a method for manufacturing a semiconductor device, the method comprising the step of tapering the cross section of the semiconductor device.

以下本発明の一実施例を図面に従って詳細に説明する〇 第２図及び第３図は本実施例を説明するための断面図で
第１図と同じ部分には同一符号を付し良。An embodiment of the present invention will be described below in detail with reference to the drawings. FIGS. 2 and 3 are sectional views for explaining this embodiment, and the same parts as in FIG. 1 are denoted by the same reference numerals.

本実施例では第２図に示すように、拡散マスク用の被膜
ｚ（８ｔＯ，膜）の開口部の部分７がテーパー状になる
よう形成している丸め、その上に塗布し九シリコンの水
酸化物ＯＩＩの膜厚が略均−Ｋｌ！布される◎その九め
その後の熱処理時における収縮に伴う従来の如き切断は
生じない０ 従って所望の拡散領域５が形成される０以下により具体
的に説明する〇 第３１１（ａ）参照 Ｐｉｉの８＋半導体基板１上に拡散マスク用の被膜２と
して８ｉ０．膜を形成し、さらにその上−に所定のパタ
ーンのレジスト膜Ｂを形成する〇そしてＳｉｎ、膜２を
途中までエツチングする〇第３図（ｂ）参照 プラズマアッシャ−勢によりレジスト膜Ｂをわずかに灰
化除去する。その結果レジスト膜Ｂの開口部の大きさは
第３図（Ｊｌ）よシ太きくなる〇そとで再度８ｉ０．Ｉ
ＩＺをエツチングする。In this example, as shown in FIG. 2, the opening part 7 of the film z (8tO, film) for the diffusion mask is rounded and formed into a tapered shape. The film thickness of oxide OII is approximately average -Kl! ◎ The conventional cutting due to shrinkage during the subsequent heat treatment does not occur. Therefore, the desired diffusion region 5 is formed. 8+ As a coating 2 for a diffusion mask on a semiconductor substrate 1, 8i0. A film is formed, and then a resist film B with a predetermined pattern is formed on it.Then, the Sin film 2 is etched halfway.See Fig. 3(b).The resist film B is slightly etched using a plasma asher. Ash and remove. As a result, the size of the opening in the resist film B becomes larger than that shown in FIG. 3 (Jl), again at 8i0. I
Etch IZ.

第３図（ｃ）参照 その結果８ｉ０．膜２０基板１を露出するエツジの部分
７で階段上になりテーパーを有する形状となる。次に拡
散マスク用の８ｉ０．膜２上に拡散源となる膜３を撒布
する・この膜４は、シリコンの水酸化物であるｓ　ｔ　
（ＯＨ）、とＮｌｉ不純物として三酸化ヒ素（Ａｓ　ｔ
　Ｏｓ　）とをア七トン等の溶剤で液状にしたものを、
スピンコーティング法で塗布したものである。Refer to FIG. 3(c).Result 8i0. The edge portion 7 of the film 20 that exposes the substrate 1 has a stepped shape and a tapered shape. Next, 8i0 for the diffusion mask. A film 3 that serves as a diffusion source is spread on the film 2. This film 4 is made of silicon hydroxide.
(OH), and arsenic trioxide (As t
Os ) is liquefied with a solvent such as A7Tone,
It was applied using a spin coating method.

その後５００〜９００℃の雰囲気中で３０〜６０分の熱
処理によるキュア工程により溶剤を飛散せしめた後、１
０００〜１２００ｔｌ：ｌｉｆの熱処理１施こして、Ｎ
ｉｌ［の不純物Ａｓ　を基板１内に拡散する。After that, the solvent was scattered by a curing process by heat treatment for 30 to 60 minutes in an atmosphere of 500 to 900°C, and then
After 1 heat treatment of 000 to 1200 tl:lif, N
The impurity As of il[ is diffused into the substrate 1.

ｓｉｏ、膜２のエツジ部７がテーパー状であ鼠ため熱処
理によるシリコンの水酸化物膜３の収縮が起っても切断
されるようなことはなく、所望の拡散を得ることができ
る０ 上記実施例の他に拡散マスク用の被膜２にテーパーを持
たせ本技術は種々考えられるが、そのようなものも本発
明に含ｔｈるものであるＯ以上説−したように本発Ｗ１
４によれば、不純物を含有するシリ−／の水酸化物を拡
散源とする固相拡散において、収縮による一来の問題点
を鱗決することができる◎Since the edge portion 7 of the film 2 is tapered, even if the silicon hydroxide film 3 shrinks due to heat treatment, it will not be cut and the desired diffusion can be obtained. In addition to the embodiments, there are various ways in which the present technology can be applied to the film 2 for the diffusion mask to have a taper, but such technology is also included in the present invention.As explained above, the present invention W1
According to 4, in solid-phase diffusion using silica/hydroxide containing impurities as a diffusion source, it is possible to determine the problems caused by shrinkage.

【図面の簡単な説明】[Brief explanation of the drawing]

籐１図は従来例の断面図、第２図、第３図は本発明の一
実施例を説明する九めの断面図である０図中、ｌは半導
体基板、２Ｆｉ拡散マスク用の被膜、３はシリコンの水
酸化物の膜であるＯ第　Ｚ　口 〜、７／３ ＼ ＼、 、　　　　−、／　　　　　　２Figure 1 is a sectional view of a conventional example, and Figures 2 and 3 are ninth sectional views explaining an embodiment of the present invention. In Figure 0, l represents a semiconductor substrate, a film for a 2Fi diffusion mask, 3 is a film of silicon hydroxide.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に拡散ｉスフ用被ＩＩＩｔ−所定のパター
ンに形成し、皺被躾上に不純物、及び溶剤を含有するシ
リコンの水酸化物の膜を塗布し、熱Ｊ６１１を施こして
該基板内に前記不純物を拡散する工程において、前記拡
散マスク用被膜の該基板を露出せる部分の断面をテーパ
状にする工程を含むことを特徴とする半導体装置の製造
方法０A silicon hydroxide film containing impurities and a solvent is formed on a semiconductor substrate in a predetermined pattern, and a film of silicon hydroxide containing impurities and a solvent is applied to the substrate to form a diffusion layer. A method for manufacturing a semiconductor device 0, characterized in that the step of diffusing the impurity in the film includes the step of tapering a cross section of a portion of the diffusion mask film that exposes the substrate.
JP10188281A 1981-06-30 1981-06-30 Manufacture of semiconductor device Pending JPS583226A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10188281A JPS583226A (en) 1981-06-30 1981-06-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10188281A JPS583226A (en) 1981-06-30 1981-06-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS583226A true JPS583226A (en) 1983-01-10

Family

ID=14312304

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10188281A Pending JPS583226A (en) 1981-06-30 1981-06-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS583226A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02303120A (en) * 1989-05-18 1990-12-17 Rohm Co Ltd Method of forming impurity diffused layer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52127752A (en) * 1976-04-19 1977-10-26 Mitsubishi Electric Corp Pduction of semiconductor unit
JPS53135263A (en) * 1977-04-28 1978-11-25 Nec Corp Production of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52127752A (en) * 1976-04-19 1977-10-26 Mitsubishi Electric Corp Pduction of semiconductor unit
JPS53135263A (en) * 1977-04-28 1978-11-25 Nec Corp Production of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02303120A (en) * 1989-05-18 1990-12-17 Rohm Co Ltd Method of forming impurity diffused layer

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