JPS5831642B2 - information storage processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information storage processing device that reliably controls synchronous reading of serial information stored on a magnetic recording medium and ensures the accuracy of the read information.

When processing information in a computer, etc., the input information to be processed or the processed output information is stored in an external recording medium.
Magnetic recording media such as disks, drums, and tapes are often used.

Coded binary information is serially written and recorded on such magnetic recording media, and the binary information is read out under synchronous control.

When reading recorded binary information from such a magnetic recording medium under synchronous control, since the magnetic recording medium is mechanically driven and the information is read by a stationary magnetic head, an independent external oscillator is required. Even if a read synchronization signal is generated, read synchronization cannot be achieved, and it is actually necessary to synchronously control the synchronous oscillator in accordance with the read information from the magnetic head.

Therefore, in addition to the binary signal that constitutes the information, a synchronization signal that becomes "1" on the record for controlling the readout of this binary signal is simultaneously recorded on the magnetic recording medium, and synchronization is performed using the read synchronization signal. I am trying to control the oscillator.

As a means of recording a synchronization signal on a magnetic recording medium, two recording bands (tracks) that are read and controlled in parallel are set up, and a data bit signal, which becomes a coded binary signal, is recorded in the second track. The synchronous bit signals corresponding to each of the above bits and expressed as "1" on the recording are recorded on the other track, and the external synchronous oscillator is controlled by the synchronous bit signals read out in synchronization with the data bit signals. The information readout is synchronously controlled by the output signal from this oscillator.

However, with this method, in addition to the recording band for recording information on the magnetic recording medium, it is necessary to set up a recording band for recording recurring bits, so it is difficult to use the recording capacity of the recording medium efficiently. In particular, it is necessary to configure the magnetic recording/reading device so that two magnetic heads scan two recording bands simultaneously, which not only complicates the configuration but also requires adjustment of the settings of the two magnetic heads. becomes extremely difficult.

For this reason, it has been considered to combine and record a data bit signal and a synchronization bit signal in series on one recording band.

For example, a synchronization bit signal of "1" is arranged between each information bit arranged in series, and the consecutive bit information read out is distributed and used for information and synchronization. be.

However, in such a recording state, for example, if the information bits are a series of rlJ, the recording bits on the recording medium will be a longer series of "1"s, including those for synchronization, and the bits for information and synchronization will be longer. Bit discrimination becomes difficult.

Furthermore, when using such magnetic recording media, it is not guaranteed that all bits read out are accurate due to defects in the recording medium or other factors, so always check whether the read bit information is accurate. There is a need.

Various parity check means using check information etc. have been considered for this information check, but no matter what kind of check means is used, it is not possible to determine whether each bit is good or bad.

This invention was made in view of the above points, and it enables each bit to be read in an accurate state at all times, and
It is an object of the present invention to provide an information storage processing device using a magnetic recording medium that allows a signal for read synchronization control to be obtained without specifying a synchronization bit.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows its configuration. Coded information signals to be written and recorded are coupled to a data bus 11, and read information signals to be processed by a processing device (not shown) are coupled to a data bus 11.

Reference numeral 12 denotes a magnetic recording medium, for example, a disk, on which the information signals are written and stored. Scanning is performed by a magnetic head, and information writing or reading control is performed on the track.

As mentioned above, this disk 12 has "1" with a signal.
'' and rOJ with no signal, and the read information is supplied to the shaping circuit 15.

This shaping circuit 15 is driven when there is a read command from the processing control device 13, and when a signal of "1" is read from the disk 12, it outputs a pulse-shaped shaped output signal. is generated and supplied to the holding circuit 16.

This holding circuit 16 is given a command at the time of a specific count value of the 20-decimal counter 11, for example, rOJ counting, and stores and holds the combined information.

The 2decimal counter 17 counts the oscillation clock pulses from the oscillator 18, and calculates each information interval of the binary information read from the disk 12, that is, the bit interval of continuous bit information, by the clock pulse of the oscillator 18. It is set to approximately correspond to 20 counts,
The counter IT is reset in response to an information readout output of "1" from the shaping circuit 15.

That is, when reading from the disk 12, the counter 17 is reset and set in synchronization with the read bit every time information reading of "1" is detected. A read bit synchronization signal from disk 12 is assumed.

The output signals of the counter 17 at a particular count value are also counted by a ternary counter 19, which generates one output signal for every 3 counts, that is, every 3 bits read from the disk 12; The counter 20 is incremented.

The count signal from the counter 20 is supplied to the processing control device 13 as a digit synchronization signal, and the specific count signal from the ternary counter 19 is sent to the gate circuit 21 to which write information from the data bus 11 is coupled. Combine with numeric signal.

A write command from the processing control device 13 is coupled to this gate circuit 21, and its output information signal is supplied to the disk 12 as write information.

The read bit information for each bit held in the holding circuit 16 together with the command from the counter 17 is read by the majority circuit 22 according to the command from the counter 17, and the read information is detected in units of multiple bits, for example, 3 bits,
A bit information output signal corresponding to the majority decision content of the plurality of bits is supplied to the data bus 11.

At the same time, the majority decision information is detected by the decoder 23,
A specified start or break code is detected, and upon detection, the gate of an AND circuit 24 to which a synchronization command is coupled from the processing control device 13 is opened.

The output signal from the AND circuit 24 is supplied to the gate circuit 25 together with the bit synchronization signal from the decimal counter 17, and the output signal from the gate circuit 25 is supplied to the ternary and quaternary counters 19 as a digit synchronization signal. , 20 is given a reset command.

FIG. 2 shows in more detail the part related to the gate circuit 21 for writing shown in FIG. 4 lines 11a-1
Consisting of 1d.

The gate circuit 21 includes the lines 112 to 11.
d respective coupled exclusive OR circuits 262 to 26
A count value output signal of "1" from the ternary counter 19 is coupled to the OR circuits 26a to 26d.

The respective output signals from the exclusive OR circuits 26a to 26d are supplied to AND circuits 272 to 27d,
The output signals from the AND circuits 27a to 27d are taken out as write output signals via an OR circuit 28 and an AND circuit 29 whose gate is opened in response to a write command.

The AND circuits 27a to 27d are a quaternary counter 20.
Gates are sequentially controlled by each count value signal of rOJrlJ r2J r3j.

That is, the ternary counter 19 is incremented by the output signal from the 2decimal counter 17, which serves as a bit synchronization signal. A gate signal is supplied only when one count value is "1".

Therefore, for example, if bit information of "1" is coupled to the line 11a, the counting step of the counter 19,
In other words, the exclusive OR circuit 26a corresponds to bit synchronization.
The output signal changes in three stages to "101".

Then, when the count value of the quaternary counter 20, which is incremented every cycle of the count of the ternary counter 19, is "0", it is taken out via the AND circuit 27a, and the AND circuit 29 whose gate is opened by a write command. The signal "101" is supplied to the disk 12 as write information.

Further, the information bit signals of lines llb to 11d are each converted into a 3-bit combination in the same manner as described above, output in accordance with the count value of the counter 20, and supplied to the disk 12.

That is, the write bit information coupled to the data bus 11 is converted into combination information of three divided bits for each bit information, and the three divided bits are two identical signals and one inverted signal. The content of the bit information can be determined based on the content of the majority decision.

Specifically, if 4-bit code information of ``l'-1010'' is coupled to the data bus 11, the bit information of ``1'' is expressed by divided bits of ``l01J'' and rOJ
The bit information is expressed by divided bits of "010", and the whole is output from the AND circuit 29 as serial information of rlolololololoJ, and this is output from the AND circuit 29 as serial information of rlolololololoJ.
This is written to the designated track No. 2.

Similarly, when the encoded 4-bit information is "0000", it is expressed as serially divided bit information of JOlooloolooooIOJ, and when it is "111J", it is expressed as "10110110".
1101'' and is written and recorded on the disk 12.

That is, no matter what the coded bit information is, the binary information recorded on the disk 12 is serial information in which divided bits that are recorded as "1" exist within an interval of at least 2 bits.

Therefore, disc 1 on which such information is written
Even when reading from 2, records of ``1'' are read within at least 2-bit intervals, and the 2decimal counter 1
7, it becomes possible to perform readout bit synchronization control, and readout synchronization control can be performed effectively without having to record a synchronization bit on the disk 12 and take a special means to read it. .

FIG. 3 shows in more detail the part related to the majority circuit 22 in FIG. 1. Since 1-bit information is composed of three divided bits, When using information, a memory 30 is provided in which r3XnJ mnemonics are serially arranged, and the binary information read from the holding circuit 16 is coupled to the leading digit part, and the memory 30 is a 20-decimal memory. The storage binary information is sequentially shifted one digit at a time using a bit-synchronized clock signal from the counter 17.

That is, when the above-mentioned written record information is serially read from the disk 12 while a read command is given from the processing control device 13, an output pulse is generated from the shaping circuit 15 every time the "1" bit is read. is obtained, read and held in the holding circuit 16 in response to a bit synchronization command from the counter 17, and transmitted to the storage body 30 in response to the bit synchronization.

Therefore, bits read from disk 12 are written and shifted serially into storage 30.

This storage body 30 is provided with n majority detection circuits 31a, 31b, .

The detection circuits 31a, 31b, . . . have three storage digits a, b each storing 3-bit binary information.

The read signals of the digits in the AND circuit 32a, which are combined with the read signals from digits a and c on both sides of C, are imparked 3.
The AND circuits 32b and 32c are provided with AND circuits 32b and 32c to which the signals are detected and supplied as gate signals through digits a and 3, and read signals of digits a and b are respectively supplied.
The output signal of c is taken out via an OR circuit 34.

That is, the OR circuit 34 outputs the contents of at least two matching binary information among the binary information stored in each of the digits a, b, and C, and the gate circuit 21 outputs the contents of one bit. It functions to convert information converted into a combination of three divided bits into one bit information from both three divided bits.

And n majority detection circuits 31a. 31b... detects n bits of bit information in parallel, and decoder 23
The decoder 23 detects the specified start code and the like. Although not particularly shown, it is coupled to the data bus 11 and used as read information for processing.

The detection output of the decoder 23 such as a start code is outputted by giving a gate command to the gate circuit 25 via the AND circuit 24 and resetting the counters 19 and 20 in bit synchronization. It is used to synchronize information reading start control by instructing character separation, etc.

That is, according to the device configured as described above, the information format written on the disk 12 is such that there is definitely "1" information at small intervals, so as mentioned above, the bit specifically for synchronization is Bit synchronization control can be reliably performed during reading without writing, and writing and reading control for the disk 12 is sufficiently simplified, making drive control easier.

Further, at the time of reading, a combination of three divided bits is detected, and bit information is reproduced by majority detection of the three divided bits.

Therefore, even if bit damage occurs due to an accident on the side, the original bit information can be reliably reproduced.

For example, as is clear from the majority detection circuit 31a shown in FIG. 3, as long as the divided bits to be inverted are specified,
Even if any one of the three divided bits is damaged, the original bit information can be reliably reproduced.

That is, the read bit information is reliably reproduced bit by bit, and the reliability of the read information is significantly improved.

As described above, according to the present invention, information can be written and recorded on a magnetic recording medium such as a disk without being particularly aware of a synchronization signal, and the drive of the magnetic recording device for this purpose is This can be highly effective in simplifying control and the like.

Furthermore, even during reading, read bit synchronization control can be easily and reliably performed using the read bits.

What is even more important is that one bit of information is made up of three divided bits, so even if a bit is damaged during the recording or playback process, it can be reliably reproduced as accurate bit information. This is possible, and the effect on improving the reliability of information processing control is significant.

In particular, assuming an actual information recording means for this value, 2
There are almost no cases where more than one bit is damaged in succession, and in the case of the present invention, where damage of one bit can be completely erased, the reliability of the read information is almost perfect.

Although the embodiment has been described in which one of the three divided bits is inverted for bit information, the same implementation is possible even if two of the divided bits are set to be inverted.

In addition, in the embodiment, the center bit of the three divided bits is inverted with respect to both sides, but the same effect can be obtained by setting the one-power bit on both sides to be inverted with respect to the other two bits. It can be implemented in

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating an information storage processing device according to an embodiment of the present invention, FIG. 2 is a diagram illustrating a write gate circuit section of the above embodiment, and FIG. 3 is a diagram illustrating a majority circuit section. This is a diagram. 11...Data bus, 12...Disk, 13...Processing control device, 15...
Shaping circuit, 16...Holding circuit, 17, 19, 2
0... Counter, 18... Oscillator, 2
1... Gate circuit (writing), 22...
...Majority circuit, 23...Decoder, 26a~
26d...Exclusive OR circuit, 30...
-Memory body, 31a, 31b...Majority detection circuit.

Claims (1)

[Claims] 1 Information recording means that uses a magnetic recording medium that uses data information in which bits consisting of binary information of "1" or rOJ are serialized, and performs readout synchronization control for each "1" signal of written bit information. means for forming information bits constituting data information by a combination of three divided bits consisting of two identical binary signals and one binary signal obtained by inverting this binary signal; 3
means for serially writing information bits consisting of three divided bits onto a magnetic recording medium; means for reading three divided bits forming the information bits from the magnetic recording medium as a unit; The information bits are read by means for inverting and correcting the inverted divided bits among the three divided bits, and by means for detecting coincidence of at least two of the three binary signals read by this means. 1. An information storage processing device, comprising: means for determining a synchronization bit, and is configured to obtain at least one synchronization bit among the three divided bits.