JPS5831545A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5831545A JPS5831545A JP56129050A JP12905081A JPS5831545A JP S5831545 A JPS5831545 A JP S5831545A JP 56129050 A JP56129050 A JP 56129050A JP 12905081 A JP12905081 A JP 12905081A JP S5831545 A JPS5831545 A JP S5831545A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- jig
- internal terminal
- heat
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/79—Apparatus for Tape Automated Bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法にがかり、とくＫ Ｔ
Ａ Ｂ （Ｔａｐｅ Ａｕｔｏｍａｔｅｄ Ｂｏｎｄｉ
ｎｇ ）法によって組み立てられる半導体装置の製造方
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
A B (Tape Automated Bondi
The present invention relates to a method for manufacturing a semiconductor device assembled by the ng) method.
ＴＡＢ法は、ガえばａｇ１図（ａ）に示すように、絶
□［８７４／Ｌ’Ａ Ｉ ＫＷ＆Ｆｊられ友デバイス・
ホール２に支持枠３に支えられた金属細条（＝リード）
４を突出させ、このリードの先端に半導体テップ５を縁
続するものである。半導体チップとリードとの媛絖社、
通常、チップの電極を金で突起状に形成し、これに銅箔
をエツチングし、表面に爺中錫をめっきして形成したリ
ードを、熱と圧力を加えてＡｕ／Ａｕの熱圧７１ま几は
Ａｕ／ａｎの共晶合金に↓１蛍統する。The TAB method, as shown in Figure ag1 (a),
□[874/L'A I KW&Fj friend device/
Metal strip (= lead) supported by support frame 3 in hole 2
4 is made to protrude, and a semiconductor tip 5 is connected to the tip of this lead. Hidensha with semiconductor chips and leads,
Usually, the electrodes of the chip are formed into protrusions using gold, copper foil is etched onto the protrusions, and the surface is plated with copper tin to form leads. Heat and pressure are applied to the leads to form Au/Au thermal pressures of up to 71%. The temperature is ↓1 for the Au/an eutectic alloy.
以上のようにして接続された半導体チップは、支持枠３
と一体の筐ま（ｂ）図のように切断し、これを飼えば第
２図のように、セラミック基板６に組み込んで牛導体；
ＩＩ装置として使われる。The semiconductor chips connected in the above manner are attached to the support frame 3.
If you cut the integral housing as shown in Figure (b) and raise it, as shown in Figure 2, it will be assembled into a ceramic substrate 6 to form a cow conductor;
Used as II device.
この場合、まず半導体チップ５をセラミック基板６の中
央に開けられた凹部（＝キャビティ）７の底に例えばロ
ク材８などで固着し、次にリード４の外方ｌ１ｌＩを内
部層子９に接続する。この縁続の様子を第３図に示した
。第３図は、第２図のキャビティ内の一部を斜視図で描
いたものである。In this case, first, the semiconductor chip 5 is fixed to the bottom of a recess (=cavity) 7 made in the center of the ceramic substrate 6 with a locking material 8, and then the outer l1lI of the leads 4 are connected to the inner layer 9. do. Figure 3 shows this relationship. FIG. 3 is a perspective view of a part of the interior of the cavity shown in FIG. 2.
但し、繁雑を避ける為にリード及び内部端子は数不しか
描ムていない。However, to avoid clutter, only a few leads and internal terminals are drawn.
半導体チップ５はリード４と内部端子９と位置合わせし
次状態でキャビティ内に固層されｔ後、加熱・加圧治具
ｌｏにょ如、図中に破巌で示したようにして熱と圧力が
印加され、接続が行なわれるー。After the semiconductor chip 5 is aligned with the leads 4 and internal terminals 9 and solidified in the cavity in the next state, heat and pressure are applied using a heating/pressing jig as shown in the figure. is applied and the connection is made.
この接続は、一般にリードには金または錫めっきを、内
部端子には錫やハンダめり１！ｉをして共晶合金または
低融点金属による溶融法により行なわれる。For this connection, the leads are generally plated with gold or tin, and the internal terminals are plated with tin or solder. This is carried out by a melting method using a eutectic alloy or a low melting point metal.
溶融法による確実なＷ！続を行なうには、第４図に示す
ように、内部端子部の金属がリードの側面に濡れる状態
、いわゆるメニスカス１１が出来る状態になっていなけ
ればならない、このためには、内部端子部の金属が十分
に融ける必要がめるが、ａｇ３図に示すような従来の加
熱法では、内部端子の金属が十分に融けず、接続不良が
生ずることが６っｔ。Reliable W by melting method! In order to continue, as shown in Figure 4, the metal of the internal terminal part must be in a state where it wets the side surface of the lead, creating a so-called meniscus 11. However, with the conventional heating method as shown in Figure AG3, the metal of the internal terminals may not be sufficiently melted, resulting in poor connections.
本発明は、従来の上記の欠点を除去する目的でなされ次
もので、リードの末端よ）も外側の領域にまで熱を印加
する仁とによシ、内部端子の金属を十分に融かし、メニ
カスを確実に生せしめようとするものでるる。The present invention has been made to eliminate the above-mentioned drawbacks of the conventional method. , there are things that try to make menicus grow reliably.
すなわち本発明は、半導体チップの突起電極に接続δれ
几金属細条の外方端部をセラミック基板の内部端子に治
具によプ熱と圧力を加えて靜融優枕する１楊に於いて、
前記治具の外縁が前記蓋属細条の末端よ）も外側に位置
するようにして熱と圧力を印加するととｔＩ！＃黴とす
る半導体装置の製造方法にるる。That is, the present invention involves the process of applying heat and pressure to the outer end of the metal strip connected to the protruding electrode of the semiconductor chip and applying heat and pressure to the internal terminal of the ceramic substrate using a jig to gently melt the outer end. There,
When heat and pressure are applied so that the outer edge of the jig is positioned outside the end of the lid strip, tI! # A method for manufacturing semiconductor devices using mold.
以下に、本発明の実施例を図面を用いて詳細に説明する
。Embodiments of the present invention will be described in detail below with reference to the drawings.
第５図に、リード４の末端４′を超える領域（破−で示
す）を第３図に示し友ようにして加熱・加圧治具によｐ
熱を印加して接続した的を平面図で示し友。但し、この
場合もリードは数本のみを描き、他は省略してるる。こ
のように、リードの末ｇ４ｔ−超える領域まで加熱する
ことにょｐ１加熱・加熱治具の輻射熱に工９内部端子に
めっき嘔れている瀘属の殆んどが融け、リードの側面に
十分なメニスカスとなって確実な接続ができる。In Fig. 5, the area (indicated by a broken line) beyond the end 4' of the lead 4 is shown in Fig.
A plan view shows the targets connected by applying heat. However, in this case, only a few reeds are drawn and the others are omitted. In this way, by heating the end of the lead to an area exceeding g4t, most of the metal plated on the internal terminal of workpiece 9 will be melted by the radiant heat of the heating jig, and enough metal will be applied to the side of the lead. It becomes a meniscus and makes a reliable connection.
他の災麺ガ金第６図に斜視図で示し几、この場合もリー
ドは数本のみ示し、他は省略しである。Another example is shown in a perspective view in Figure 6; in this case too, only a few leads are shown and the others are omitted.
半導体チップの載置は上述のようなキャビティ内だけに
限らない、リード４ｔｆｌｉｅ図のように成形した上で
平坦なセラミック基板上に固層し、半導体チップ５の各
辺に沿って外周囲に配列された内部接続熾子９にリード
を接続する場合も、本発明 ′が実施できる。図中に破
縁で示し九領域を加熱・加圧治具で熱と圧力を印加すれ
ば同様な効果を得ることができる。The mounting of the semiconductor chip is not limited to the cavity as described above, but the lead 4tflie is formed as shown in the figure and then fixed on a flat ceramic substrate, and arranged around the outer periphery along each side of the semiconductor chip 5. The present invention can also be carried out when connecting a lead to the internal connection wire 9 that has been provided. A similar effect can be obtained by applying heat and pressure to nine areas indicated by broken edges in the figure using a heating/pressing jig.
以上の実Ｎ例では、リードと内部端子との接続は一辺ず
つ行なう方法で説明し友が、二辺ずつあるいは四辺同時
に行なう方法でも、本発明が適用できることは言うまで
もない。In the above examples, the connection between the leads and the internal terminals is made on one side at a time, but it goes without saying that the present invention is also applicable to connections on two sides or all four sides at the same time.
以上、詳細に説明し九ように、本発明によれば、リード
と内部端子の確実なＷｌ状ができ、ＴＡＢ法による牛導
゛体装置の製造歩留と信頼１［ｔ−大幅にアップさせる
ことができるようになった。As explained above in detail, according to the present invention, a reliable WL shape of the leads and internal terminals can be achieved, and the manufacturing yield and reliability of the conductor device using the TAB method are greatly increased. Now I can do it.
ｆｇ１図はＴＡＢ＠を説明する斜視図、第２図紘ＴＡＢ
法によって組み立てられた半導体装置ｔを示す断面図、
第３図は、従来の製造方法を示す斜視図、ａｉＴＪ図は
リードと内部端子の理想的な接続状態を示す断面図、第
５図は不発明の実Ｎ例を示す平面図、第６図は本発明の
他の実Ｎ例を示す斜視図である。
同、図において、
１・・・・・・絶縁性フィルム、２・・・・・・デバイ
ス・ホール、３・・・・・・支持枠、４・・・・・・リ
ード、４′・・・・・・リードの末端、５・・・・・・
半導体チップ、６・・・・・・セラミック・ケース、７
・・・・・・キャビティ、８・・・・・・ロウ材、９・
・・・・・内部端子、１０・・・・・・加熱・加圧治具
、１１・・・・・・メニスカスである。
′＄ １ 図
第３図Figure 1 is a perspective view explaining TAB@, Figure 2 is Hiro TAB
A cross-sectional view showing a semiconductor device t assembled by the method,
FIG. 3 is a perspective view showing the conventional manufacturing method, the aiTJ diagram is a sectional view showing the ideal connection state between the lead and the internal terminal, FIG. 5 is a plan view showing an example of non-invention, and FIG. 6 FIG. 2 is a perspective view showing another example N of the present invention. In the same figure, 1...Insulating film, 2...Device hole, 3...Support frame, 4...Lead, 4'... ...End of lead, 5...
Semiconductor chip, 6...Ceramic case, 7
...Cavity, 8...Brazing material, 9.
...internal terminal, 10 ... heating/pressure jig, 11 ... meniscus. '$ 1 Figure 3
Claims (1)
部をセラミック基板の内部層子に治Ａｌ１ｃよｐ熱と圧
力を加えて溶融綾状する工程に於いて、前記治具の外縁
が前記瀘Ｘ細条の末踊よｐも外側に位置するようにして
熱と圧力上印加することを待献とする半導体装置の製造
方法。In the step of melting the outer end of the metal strip connected to the protruding electrode of the semiconductor chip onto the inner layer of the ceramic substrate by applying heat and pressure to the inner layer of the ceramic substrate, the outer edge of the jig is A method of manufacturing a semiconductor device, wherein heat and pressure are applied so that the ends of the X stripes are also located outside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56129050A JPS5831545A (en) | 1981-08-18 | 1981-08-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56129050A JPS5831545A (en) | 1981-08-18 | 1981-08-18 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5831545A true JPS5831545A (en) | 1983-02-24 |
Family
ID=14999841
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56129050A Pending JPS5831545A (en) | 1981-08-18 | 1981-08-18 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5831545A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5355965A (en) * | 1976-10-29 | 1978-05-20 | Nec Corp | Manufacture of semiconductor device |
-
1981
- 1981-08-18 JP JP56129050A patent/JPS5831545A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5355965A (en) * | 1976-10-29 | 1978-05-20 | Nec Corp | Manufacture of semiconductor device |
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