JPS5831093Y2 - Sonar device vibration receiving circuit - Google Patents

Sonar device vibration receiving circuit

Info

Publication number
JPS5831093Y2
JPS5831093Y2 JP1981187150U JP18715081U JPS5831093Y2 JP S5831093 Y2 JPS5831093 Y2 JP S5831093Y2 JP 1981187150 U JP1981187150 U JP 1981187150U JP 18715081 U JP18715081 U JP 18715081U JP S5831093 Y2 JPS5831093 Y2 JP S5831093Y2
Authority
JP
Japan
Prior art keywords
circuit
receiver
variable gain
delay circuit
gain amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1981187150U
Other languages
Japanese (ja)
Other versions
JPS57116871U (en
Inventor
憲示 松田
卓夫 鳥海
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP1981187150U priority Critical patent/JPS5831093Y2/en
Publication of JPS57116871U publication Critical patent/JPS57116871U/ja
Application granted granted Critical
Publication of JPS5831093Y2 publication Critical patent/JPS5831093Y2/en
Expired legal-status Critical Current

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  • Measurement Of Velocity Or Position Using Acoustic Or Ultrasonic Waves (AREA)
  • Control Of Amplification And Gain Control (AREA)

Description

【考案の詳細な説明】 本考案は水中に音波を発射し、その反射波を利用して目
標物を探知するソーナー装置の受振回路に関するもので
ある。
[Detailed Description of the Invention] The present invention relates to a receiver circuit for a sonar device that emits sound waves underwater and uses the reflected waves to detect a target.

従来、ソーナー装置の受振系における自動利得制御回路
の構成は、受波器からの受振信号を増幅回路で一旦増幅
し、各受波器の受振信号出力を遅延回路網により全て同
位相で合成した後の受振出力をもって各受波器の受振出
力に対して自動利得制御を行なっている。
Conventionally, the configuration of the automatic gain control circuit in the reception system of a sonar device was to first amplify the reception signal from the receiver using an amplifier circuit, and then combine the reception signal outputs of each receiver with the same phase using a delay circuit network. Automatic gain control is performed on the received output of each receiver using the later received output.

一般にノーナーでは方位方向の表示を微細に分割してき
め細かい画面を得るために前記の遅延回路網の出力チャ
ンネル数は入力チャンネル数よりも多い。
In general, in a nonar, the number of output channels of the delay circuit network is greater than the number of input channels in order to finely divide the display of the azimuth direction and obtain a detailed screen.

従来は前述の如く、各受波器の受振信号出力を全て同位
置で合成する遅延回路網の後段に自動利得制御回路を設
けていたため、前記した遅延回路網の出力はチャンネル
数が多くなり、自動利得制御を行なうチャンネル数が多
(なって各チャンネル特性を揃えることがむずかしく、
かつ使用部品数が多くなり構成が複雑になるという欠点
があった。
Conventionally, as mentioned above, an automatic gain control circuit was provided after the delay circuit network that synthesized all the received signal outputs of each receiver at the same position, so the output of the delay circuit network described above had a large number of channels. There are a large number of channels that require automatic gain control (so it is difficult to align the characteristics of each channel,
Another disadvantage is that the number of parts used increases and the configuration becomes complicated.

また、遅延回路網の入力レベルの変化範囲は受波音圧レ
ベルに応じて広くなるのでディジタル回路で遅延回路網
を構成した場合にはA −D変換器のピッド数を多くし
ないと良好な性能を得ることができなかった。
In addition, the range of change in the input level of the delay circuit becomes wider depending on the received sound pressure level, so if the delay circuit is configured with a digital circuit, good performance will be achieved unless the number of pins in the A-D converter is increased. I couldn't get it.

さらに、遅延回路網の後に設ける増幅回路の特性として
入出力直線性の範囲の広いものが要求され、受振系の構
成が複雑かつ大きくなり、高価なものになるという欠点
があった。
Furthermore, the characteristic of the amplifier circuit provided after the delay circuit network is that a wide range of input/output linearity is required, resulting in the disadvantage that the configuration of the vibration receiving system becomes complicated, large, and expensive.

本考案は前記従来技術の欠点を除去することを目的とし
、その特徴とするところは、遅延回路網で各受波器の受
振信号出力を全て同位相で合成する以前に、自動利得制
御を行なうようにしたことである。
The purpose of the present invention is to eliminate the drawbacks of the prior art described above, and its feature is that automatic gain control is performed before all received signal outputs of each receiver are combined in the same phase using a delay circuit network. This is what I did.

まず、第1図のブロック図に従って従来回路を簡単に説
明する。
First, a conventional circuit will be briefly explained according to the block diagram of FIG.

第1図において、1.2.3は受波器、4,5゜6は増
幅器、7は遅延回路、8,9.10は可変利得増幅回路
、lL12,13は制御回路であって、受波器1,2.
3からの発振信号は増幅回路4,5.6で増幅された後
遅延回路網7に入力される。
In Fig. 1, 1.2.3 is a receiver, 4, 5.6 is an amplifier, 7 is a delay circuit, 8, 9.10 is a variable gain amplifier circuit, and 1L12, 13 is a control circuit. Wave device 1, 2.
The oscillation signal from 3 is amplified by amplifier circuits 4, 5.6 and then input to delay circuit network 7.

遅延回路網Iではある基準面に対して生ずる各受波器へ
の信号到達時間差をり、C等の遅延素子を通すことによ
り各受波器の受振信号を全て同位相で合成する。
In the delay circuit network I, the difference in signal arrival time to each receiver that occurs with respect to a certain reference plane is calculated, and by passing through a delay element such as C, the received signals of each receiver are all synthesized in the same phase.

その遅延回路網7の出力信号は可変利得増幅回路a、s
、ioに送られ、可変利得増幅回路の出力の一部を制御
回路11,12゜13の入力として制御電圧をつくり自
動利得制御を行ない、残響に対して可変利得増幅回路8
,9゜100出力レベルが一定になるように動作するも
のである。
The output signal of the delay circuit network 7 is the variable gain amplifier circuit a, s.
, io, and a part of the output of the variable gain amplifier circuit is input to the control circuits 11, 12 and 13 to create a control voltage and perform automatic gain control, and the variable gain amplifier circuit 8
, 9°100 so that the output level remains constant.

しかし、同回路方式によると前述したような問題があっ
た。
However, this circuit system has the above-mentioned problems.

次に本考案を第2図〜第5図に従って詳細に説明する。Next, the present invention will be explained in detail with reference to FIGS. 2 to 5.

第2図は本考案の一実施例を示す自動利得制御回路の構
成図であり、同図に示すように受波器1゜2.3からの
受振信号は打体利得増幅回路14゜15.16で増幅さ
れた後、遅延回路網7に加えられる。
FIG. 2 is a block diagram of an automatic gain control circuit showing an embodiment of the present invention, and as shown in the figure, the received signal from the wave receiver 1.2. After being amplified at 16, it is applied to delay network 7.

このとぎ、可変利得増幅回路14,15゜16の出力の
一部を制御回路17,18.19の入力とし、可変利得
増幅回路14,15.16毎に自動利得制御を行なうよ
うにしである。
At this time, a part of the outputs of the variable gain amplifier circuits 14, 15, 16 are input to the control circuits 17, 18, 19, and automatic gain control is performed for each variable gain amplifier circuit 14, 15, 16.

これによって、残響に対して各可変利得増幅回路14゜
15.16の出力レベルが一定になるように制御する。
As a result, the output level of each variable gain amplifier circuit 14, 15, and 16 is controlled to be constant against reverberation.

遅延回路網Iではある基準面に対して生ずる各受波器へ
の信号到達時間差をり、C等の遅延素子を通すことによ
り補償して各受波器の受振信号出力を全て同位置で合成
し、その出刃を増幅回路20,21 .22で増幅して
次段へ送る。
In the delay network I, the difference in signal arrival time to each receiver that occurs with respect to a certain reference plane is compensated for by passing through delay elements such as C, and the received signal outputs of each receiver are all combined at the same position. Then, the blades are transmitted to amplifier circuits 20, 21 . 22 and sends it to the next stage.

同構成によると、前記した従来技術における種種の問題
を解決できると共に、ダイナミックレンジを大きくとる
ことができる。
According to this configuration, various problems in the prior art described above can be solved, and a dynamic range can be increased.

また、第3図は本考案の第2の実施例を示したものであ
り、各チャンネル中の最大出力信号レベルによって利得
制御を行なう場合の例である。
Further, FIG. 3 shows a second embodiment of the present invention, and is an example in which gain control is performed according to the maximum output signal level in each channel.

受波器1.2.3からの受振信号は、可変利得増幅回路
14.15.16で増幅された後、遅延回路網γに加え
られる。
The received signal from the receiver 1.2.3 is amplified by the variable gain amplifier circuit 14.15.16 and then applied to the delay network γ.

このとき、可変利得増幅回路14.15.16の出力の
一部を増幅検波回路23.24.25で増幅し、検波し
た後、アナログ・ゲート回路26.27.28で各チャ
ンネル中の最大出力信号を検出し、高入力インピーダン
スの直流増幅回路29でインピーダンス変換と増幅を行
ない、時定数回路30で信号の性質に適した時定数を設
定して全ての可変利得増幅回路14゜15.16の利得
を制御する。
At this time, a part of the output of the variable gain amplifier circuit 14, 15, 16 is amplified and detected by the amplification detection circuit 23, 24, 25, and then the maximum output in each channel is detected by the analog gate circuit 26, 27, 28. The signal is detected, the high input impedance DC amplifier circuit 29 performs impedance conversion and amplification, the time constant circuit 30 sets a time constant suitable for the characteristics of the signal, and all variable gain amplifier circuits 14, 15, 16 Control gain.

同方式によると、可変利得増幅回路14,15゜16の
出力信号レベルの最大値は一定になり、かつチャンネル
間の入力信号のレベル差がそのまま出力信号レベルの差
となって現われる。
According to this method, the maximum value of the output signal level of the variable gain amplifier circuits 14, 15, and 16 becomes constant, and the level difference in the input signal between channels directly appears as the difference in the output signal level.

そして、遅延回路網7では、ある基準面に対して生ずる
各受波器への信号到達時間差をり、C等の遅延素子を通
すことにより、各受波器の受振信号出力を全て同位相で
合成し、その出力を増幅回路20.2L22で増幅して
次段へ送る。
Then, in the delay circuit network 7, by calculating the difference in signal arrival time to each receiver that occurs with respect to a certain reference plane, and passing it through a delay element such as C, the received signal output from each receiver is all in the same phase. The output is amplified by the amplifier circuit 20.2L22 and sent to the next stage.

同回路方式においても遅延回路網7の前段で各可変利得
増幅回路の利得制御を行なっているので、ダイナミック
レンジを大きくとることができる。
In this circuit system as well, since the gain control of each variable gain amplifier circuit is performed before the delay circuit network 7, a large dynamic range can be achieved.

さらに、第4図は本考案の第3の実施例を示したもので
あり、第2の実施例では各チャンネル中の最大出力信号
レベルによって利得制御したが、同実施例は各チャンネ
ルの平均出力信号レベルによって利得制御を行なう場合
の例である。
Furthermore, FIG. 4 shows a third embodiment of the present invention. In the second embodiment, the gain was controlled by the maximum output signal level in each channel, but in this embodiment, the gain was controlled by the average output signal level of each channel. This is an example of gain control based on signal level.

受波器1.2.3からの受振信号は可変利得増幅回路1
4.15.16で増幅された後、遅延回路網7に加えら
れる。
The received signal from the receiver 1.2.3 is sent to the variable gain amplifier circuit 1.
After being amplified at 4.15.16, it is applied to the delay network 7.

このとき、可変利得増幅回路14゜15.16の出力の
一部を増幅検波回路23 、24゜25で増幅し検波し
た後、平均値回路31,32゜33で各チャンネルの出
力レベルの平均値を得て、高入力インピーダンスの直流
増幅回路29でインピーダンス変換と増幅を行ない、時
定数回路30で信号の性質に適した時定数を設定して全
ての可変利得増幅回路14.15,16の利得を制御す
るというものである。
At this time, after a part of the output of the variable gain amplifier circuit 14°15.16 is amplified and detected by the amplification/detection circuits 23 and 24°25, the average value of the output level of each channel is calculated by the average value circuits 31 and 32°33. The high input impedance DC amplifier circuit 29 performs impedance conversion and amplification, and the time constant circuit 30 sets a time constant suitable for the characteristics of the signal to adjust the gains of all variable gain amplifier circuits 14, 15, and 16. The idea is to control the

なお、ここで平均値回路は抵抗器を使用したものについ
て説明したが、各チャンネルの出力をアナログ加算器で
加算した後、抵抗器等による分割器で除算しても行なえ
る。
Although the average value circuit using resistors has been described here, it can also be performed by adding the outputs of each channel using an analog adder and then dividing the result using a divider such as a resistor.

また、平均値回路をテイジタル化して、ディジタルによ
って自動利得制御を行なうことも出来る。
It is also possible to digitalize the average value circuit and perform automatic gain control digitally.

以上述べたよう□、本考案によるソーナー装置の受振回
路によれば、遅延回路網の前段に自動利得制御回路を設
け、遅延回路網により各受波器の受振信号を同位相で合
成する以前に、自動利得制御を行なうように構成したの
で、遅延回路網から受波器側のチャンネル数が、遅延回
路網から出力増幅回路側のチャンネル数より少ない場合
に自動利得制御を行なうチャンネル数が少なくて済み、
また、遅延回路網の入力レベルの変化範囲を小さく出来
るので、ディジタルで各受波器の受振信号出力を同位相
にする場合にA−D変換器のビット数を少なくしても同
等の性能を得ることが出来る。
As mentioned above, according to the receiver circuit of the sonar device according to the present invention, an automatic gain control circuit is provided before the delay circuit network, and before the delay circuit network synthesizes the receiver signals of each receiver in the same phase. Since the configuration is configured to perform automatic gain control, if the number of channels from the delay circuit network to the receiver side is smaller than the number of channels from the delay circuit network to the output amplifier circuit side, the number of channels for which automatic gain control is performed is small. Done,
In addition, since the range of change in the input level of the delay circuit network can be reduced, when digitally setting the received signal output of each receiver in the same phase, the same performance can be achieved even if the number of bits of the A-D converter is reduced. You can get it.

さらに遅延回路網の後に設ける増幅回路の入出力直線性
の範囲を余り必要ともしない。
Furthermore, the input/output linearity range of the amplifier circuit provided after the delay circuit network is not required to be large.

さらにまた、本考案によれば、増幅回路、遅延回路、自
動利得制御回路2含んだ受振系を小形で経済的に制作出
来る等と数多くの利点な有し、ダイナミックレンジの大
きいソーナー装置の受振回路な得ることができる。
Furthermore, the present invention has many advantages such as being able to economically produce a vibration receiving system including an amplifier circuit, a delay circuit, and an automatic gain control circuit 2 in a small size. You can get it.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の自動利得制御回路の構成法を説明するた
めのフロック図、第2図〜第4図は本考案による自動利
得制御回路の構成法の実施例を示すブロック図であり、
第2図は各チャンネル毎に自動利得制御を行なう場合の
例、第3図は各チャンネル中の最大出力信号レベルによ
って利得制御ヲ行なう場合の例、第4図は各チャンネル
の平均出力信号レベルによって利得制御を行なう場合の
例である。 1〜3・・・・・・受波器、4〜6,20〜22・・・
・・・増幅回路、1・・・・・・遅延回路網、8〜10
.14〜16・・・・・・可変利得増幅回路、11〜1
3.17〜19・・・・・・制御回路、23〜25・・
・・・・増幅検波回路、26〜28・・・・・・アナロ
グ・ゲート回路、29・・・・・・直流増幅回路、30
・・・・・・時定数回路、31〜33・・・・・・平均
値回路。
FIG. 1 is a block diagram for explaining a conventional method of configuring an automatic gain control circuit, and FIGS. 2 to 4 are block diagrams showing embodiments of a method of configuring an automatic gain control circuit according to the present invention.
Figure 2 is an example of automatic gain control for each channel, Figure 3 is an example of gain control based on the maximum output signal level of each channel, and Figure 4 is an example of automatic gain control based on the average output signal level of each channel. This is an example of performing gain control. 1-3...Receiver, 4-6, 20-22...
... Amplifier circuit, 1 ... Delay circuit network, 8 to 10
.. 14-16...Variable gain amplifier circuit, 11-1
3.17-19...control circuit, 23-25...
...Amplification detection circuit, 26-28...Analog gate circuit, 29...Direct current amplifier circuit, 30
...Time constant circuit, 31-33...Average value circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 水中に音波を発射し、その音波の反射を利用して目標物
を探知するソーナー装置の発振回路であって、複数個の
受波器と、該受波器を介して得た受振信号を増幅する可
変利得増幅回路と、該可変利得増幅回路を介して得た受
振信号出力を同位相で合成するための遅延回路と、該遅
延回路を介して同位相で合成した受振信号出力を増幅す
る増幅回路と、前記可変利得増幅回路の出力の一部を入
力として、該可変利得増幅回路の出力レベルが信号の性
質に適した時定数で一定となるように制御するための前
記遅延回路の前段に設けた制御回路とを備えて成り、前
記遅延回路により各受波器の受振信号出力を全て同位相
で合成する前段において自動的に利得制御を行なうよう
に構成したことを特徴とするソーナー装置の受振回路。
This is an oscillation circuit for a sonar device that emits sound waves into the water and uses the reflection of the sound waves to detect targets.It includes multiple receivers and amplifies the received signal obtained through the receivers. a variable gain amplifier circuit, a delay circuit for combining the received signal outputs obtained through the variable gain amplifier circuit in the same phase, and an amplifier for amplifying the received signal outputs synthesized in the same phase through the delay circuit. circuit, and a stage preceding the delay circuit for controlling the output level of the variable gain amplifier circuit to be constant with a time constant suitable for the nature of the signal, using a part of the output of the variable gain amplifier circuit as an input. and a control circuit provided in the sonar device, wherein the sonar device is configured to automatically perform gain control in a stage before combining the received signal outputs of each receiver in the same phase using the delay circuit. Receiver circuit.
JP1981187150U 1981-12-17 1981-12-17 Sonar device vibration receiving circuit Expired JPS5831093Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981187150U JPS5831093Y2 (en) 1981-12-17 1981-12-17 Sonar device vibration receiving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981187150U JPS5831093Y2 (en) 1981-12-17 1981-12-17 Sonar device vibration receiving circuit

Publications (2)

Publication Number Publication Date
JPS57116871U JPS57116871U (en) 1982-07-20
JPS5831093Y2 true JPS5831093Y2 (en) 1983-07-09

Family

ID=29989714

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981187150U Expired JPS5831093Y2 (en) 1981-12-17 1981-12-17 Sonar device vibration receiving circuit

Country Status (1)

Country Link
JP (1) JPS5831093Y2 (en)

Also Published As

Publication number Publication date
JPS57116871U (en) 1982-07-20

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